1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd4_program.h"
38 #include "fd4_emit.h"
39 #include "fd4_texture.h"
40 #include "fd4_format.h"
41
42 static void
delete_shader_stateobj(struct fd4_shader_stateobj * so)43 delete_shader_stateobj(struct fd4_shader_stateobj *so)
44 {
45 ir3_shader_destroy(so->shader);
46 free(so);
47 }
48
49 static struct fd4_shader_stateobj *
create_shader_stateobj(struct pipe_context * pctx,const struct pipe_shader_state * cso,enum shader_t type)50 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
51 enum shader_t type)
52 {
53 struct fd_context *ctx = fd_context(pctx);
54 struct ir3_compiler *compiler = ctx->screen->compiler;
55 struct fd4_shader_stateobj *so = CALLOC_STRUCT(fd4_shader_stateobj);
56 so->shader = ir3_shader_create(compiler, cso, type, &ctx->debug);
57 return so;
58 }
59
60 static void *
fd4_fp_state_create(struct pipe_context * pctx,const struct pipe_shader_state * cso)61 fd4_fp_state_create(struct pipe_context *pctx,
62 const struct pipe_shader_state *cso)
63 {
64 return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
65 }
66
67 static void
fd4_fp_state_delete(struct pipe_context * pctx,void * hwcso)68 fd4_fp_state_delete(struct pipe_context *pctx, void *hwcso)
69 {
70 struct fd4_shader_stateobj *so = hwcso;
71 delete_shader_stateobj(so);
72 }
73
74 static void *
fd4_vp_state_create(struct pipe_context * pctx,const struct pipe_shader_state * cso)75 fd4_vp_state_create(struct pipe_context *pctx,
76 const struct pipe_shader_state *cso)
77 {
78 return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
79 }
80
81 static void
fd4_vp_state_delete(struct pipe_context * pctx,void * hwcso)82 fd4_vp_state_delete(struct pipe_context *pctx, void *hwcso)
83 {
84 struct fd4_shader_stateobj *so = hwcso;
85 delete_shader_stateobj(so);
86 }
87
88 static void
emit_shader(struct fd_ringbuffer * ring,const struct ir3_shader_variant * so)89 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
90 {
91 const struct ir3_info *si = &so->info;
92 enum a4xx_state_block sb = fd4_stage2shadersb(so->type);
93 enum adreno_state_src src;
94 uint32_t i, sz, *bin;
95
96 if (fd_mesa_debug & FD_DBG_DIRECT) {
97 sz = si->sizedwords;
98 src = SS4_DIRECT;
99 bin = fd_bo_map(so->bo);
100 } else {
101 sz = 0;
102 src = SS4_INDIRECT;
103 bin = NULL;
104 }
105
106 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + sz);
107 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
108 CP_LOAD_STATE4_0_STATE_SRC(src) |
109 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
110 CP_LOAD_STATE4_0_NUM_UNIT(so->instrlen));
111 if (bin) {
112 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
113 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER));
114 } else {
115 OUT_RELOC(ring, so->bo, 0,
116 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER), 0);
117 }
118
119 /* for how clever coverity is, it is sometimes rather dull, and
120 * doesn't realize that the only case where bin==NULL, sz==0:
121 */
122 assume(bin || (sz == 0));
123
124 for (i = 0; i < sz; i++) {
125 OUT_RING(ring, bin[i]);
126 }
127 }
128
129 struct stage {
130 const struct ir3_shader_variant *v;
131 const struct ir3_info *i;
132 /* const sizes are in units of 4 * vec4 */
133 uint8_t constoff;
134 uint8_t constlen;
135 /* instr sizes are in units of 16 instructions */
136 uint8_t instroff;
137 uint8_t instrlen;
138 };
139
140 enum {
141 VS = 0,
142 FS = 1,
143 HS = 2,
144 DS = 3,
145 GS = 4,
146 MAX_STAGES
147 };
148
149 static void
setup_stages(struct fd4_emit * emit,struct stage * s)150 setup_stages(struct fd4_emit *emit, struct stage *s)
151 {
152 unsigned i;
153
154 s[VS].v = fd4_emit_get_vp(emit);
155 s[FS].v = fd4_emit_get_fp(emit);
156
157 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
158
159 for (i = 0; i < MAX_STAGES; i++) {
160 if (s[i].v) {
161 s[i].i = &s[i].v->info;
162 /* constlen is in units of 4 * vec4: */
163 s[i].constlen = align(s[i].v->constlen, 4) / 4;
164 /* instrlen is already in units of 16 instr.. although
165 * probably we should ditch that and not make the compiler
166 * care about instruction group size of a3xx vs a4xx
167 */
168 s[i].instrlen = s[i].v->instrlen;
169 } else {
170 s[i].i = NULL;
171 s[i].constlen = 0;
172 s[i].instrlen = 0;
173 }
174 }
175
176 /* NOTE: at least for gles2, blob partitions VS at bottom of const
177 * space and FS taking entire remaining space. We probably don't
178 * need to do that the same way, but for now mimic what the blob
179 * does to make it easier to diff against register values from blob
180 *
181 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
182 * is run from external memory.
183 */
184 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
185 /* prioritize FS for internal memory: */
186 if (s[FS].instrlen < 64) {
187 /* if FS can fit, kick VS out to external memory: */
188 s[VS].instrlen = 0;
189 } else if (s[VS].instrlen < 64) {
190 /* otherwise if VS can fit, kick out FS: */
191 s[FS].instrlen = 0;
192 } else {
193 /* neither can fit, run both from external memory: */
194 s[VS].instrlen = 0;
195 s[FS].instrlen = 0;
196 }
197 }
198 s[VS].constlen = 66;
199 s[FS].constlen = 128 - s[VS].constlen;
200 s[VS].instroff = 0;
201 s[VS].constoff = 0;
202 s[FS].instroff = 64 - s[FS].instrlen;
203 s[FS].constoff = s[VS].constlen;
204 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
205 s[HS].constoff = s[DS].constoff = s[GS].constoff = s[FS].constoff;
206 }
207
208 void
fd4_program_emit(struct fd_ringbuffer * ring,struct fd4_emit * emit,int nr,struct pipe_surface ** bufs)209 fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit,
210 int nr, struct pipe_surface **bufs)
211 {
212 struct stage s[MAX_STAGES];
213 uint32_t pos_regid, posz_regid, psize_regid, color_regid[8];
214 uint32_t face_regid, coord_regid, zwcoord_regid;
215 enum a3xx_threadsize fssz;
216 int constmode;
217 int i, j;
218
219 debug_assert(nr <= ARRAY_SIZE(color_regid));
220
221 if (emit->key.binning_pass)
222 nr = 0;
223
224 setup_stages(emit, s);
225
226 fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
227
228 /* blob seems to always use constmode currently: */
229 constmode = 1;
230
231 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
232 if (pos_regid == regid(63, 0)) {
233 /* hw dislikes when there is no position output, which can
234 * happen for transform-feedback vertex shaders. Just tell
235 * the hw to use r0.x, with whatever random value is there:
236 */
237 pos_regid = regid(0, 0);
238 }
239 posz_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DEPTH);
240 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
241 if (s[FS].v->color0_mrt) {
242 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
243 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
244 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
245 } else {
246 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
247 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
248 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
249 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
250 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
251 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
252 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
253 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
254 }
255
256 /* TODO get these dynamically: */
257 face_regid = s[FS].v->frag_face ? regid(0,0) : regid(63,0);
258 coord_regid = s[FS].v->frag_coord ? regid(0,0) : regid(63,0);
259 zwcoord_regid = s[FS].v->frag_coord ? regid(0,2) : regid(63,0);
260
261 /* we could probably divide this up into things that need to be
262 * emitted if frag-prog is dirty vs if vert-prog is dirty..
263 */
264
265 OUT_PKT0(ring, REG_A4XX_HLSQ_UPDATE_CONTROL, 1);
266 OUT_RING(ring, 0x00000003);
267
268 OUT_PKT0(ring, REG_A4XX_HLSQ_CONTROL_0_REG, 5);
269 OUT_RING(ring, A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz) |
270 A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
271 A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
272 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
273 * flush some caches? I think we only need to set those
274 * bits if we have updated const or shader..
275 */
276 A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
277 A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
278 OUT_RING(ring, A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
279 A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
280 A4XX_HLSQ_CONTROL_1_REG_COORDREGID(coord_regid) |
281 A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(zwcoord_regid));
282 OUT_RING(ring, A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(63) |
283 0x3f3f000 | /* XXX */
284 A4XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid));
285 OUT_RING(ring, A4XX_HLSQ_CONTROL_3_REG_REGID(s[FS].v->pos_regid) |
286 0xfcfcfc00);
287 OUT_RING(ring, 0x00fcfcfc); /* XXX HLSQ_CONTROL_4 */
288
289 OUT_PKT0(ring, REG_A4XX_HLSQ_VS_CONTROL_REG, 5);
290 OUT_RING(ring, A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(s[VS].constlen) |
291 A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
292 A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(s[VS].instrlen) |
293 A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(s[VS].instroff));
294 OUT_RING(ring, A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(s[FS].constlen) |
295 A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
296 A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(s[FS].instrlen) |
297 A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(s[FS].instroff));
298 OUT_RING(ring, A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(s[HS].constlen) |
299 A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
300 A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(s[HS].instrlen) |
301 A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s[HS].instroff));
302 OUT_RING(ring, A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(s[DS].constlen) |
303 A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
304 A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(s[DS].instrlen) |
305 A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s[DS].instroff));
306 OUT_RING(ring, A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(s[GS].constlen) |
307 A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
308 A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(s[GS].instrlen) |
309 A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s[GS].instroff));
310
311 OUT_PKT0(ring, REG_A4XX_SP_SP_CTRL_REG, 1);
312 OUT_RING(ring, 0x140010 | /* XXX */
313 COND(emit->key.binning_pass, A4XX_SP_SP_CTRL_REG_BINNING_PASS));
314
315 OUT_PKT0(ring, REG_A4XX_SP_INSTR_CACHE_CTRL, 1);
316 OUT_RING(ring, 0x7f | /* XXX */
317 COND(s[VS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER) |
318 COND(s[FS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER) |
319 COND(s[VS].instrlen && s[FS].instrlen,
320 A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER));
321
322 OUT_PKT0(ring, REG_A4XX_SP_VS_LENGTH_REG, 1);
323 OUT_RING(ring, s[VS].v->instrlen); /* SP_VS_LENGTH_REG */
324
325 OUT_PKT0(ring, REG_A4XX_SP_VS_CTRL_REG0, 3);
326 OUT_RING(ring, A4XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
327 A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
328 A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
329 A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
330 A4XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
331 A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
332 COND(s[VS].v->has_samp, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE));
333 OUT_RING(ring, A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(s[VS].constlen) |
334 A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(s[VS].v->total_in));
335 OUT_RING(ring, A4XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
336 A4XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
337 A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(s[FS].v->varying_in));
338
339 struct ir3_shader_linkage l = {0};
340 ir3_link_shaders(&l, s[VS].v, s[FS].v);
341
342 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
343 uint32_t reg = 0;
344
345 OUT_PKT0(ring, REG_A4XX_SP_VS_OUT_REG(i), 1);
346
347 reg |= A4XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
348 reg |= A4XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
349 j++;
350
351 reg |= A4XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
352 reg |= A4XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
353 j++;
354
355 OUT_RING(ring, reg);
356 }
357
358 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
359 uint32_t reg = 0;
360
361 OUT_PKT0(ring, REG_A4XX_SP_VS_VPC_DST_REG(i), 1);
362
363 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc + 8);
364 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc + 8);
365 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc + 8);
366 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc + 8);
367
368 OUT_RING(ring, reg);
369 }
370
371 OUT_PKT0(ring, REG_A4XX_SP_VS_OBJ_OFFSET_REG, 2);
372 OUT_RING(ring, A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
373 A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[VS].instroff));
374 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
375
376 if (emit->key.binning_pass) {
377 OUT_PKT0(ring, REG_A4XX_SP_FS_LENGTH_REG, 1);
378 OUT_RING(ring, 0x00000000); /* SP_FS_LENGTH_REG */
379
380 OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG0, 2);
381 OUT_RING(ring, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
382 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
383 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(0) |
384 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(0) |
385 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
386 A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
387 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE);
388 OUT_RING(ring, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s[FS].constlen) |
389 0x80000000);
390
391 OUT_PKT0(ring, REG_A4XX_SP_FS_OBJ_OFFSET_REG, 2);
392 OUT_RING(ring, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
393 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[FS].instroff));
394 OUT_RING(ring, 0x00000000);
395 } else {
396 OUT_PKT0(ring, REG_A4XX_SP_FS_LENGTH_REG, 1);
397 OUT_RING(ring, s[FS].v->instrlen); /* SP_FS_LENGTH_REG */
398
399 OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG0, 2);
400 OUT_RING(ring, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
401 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
402 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
403 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
404 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
405 A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
406 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
407 COND(s[FS].v->has_samp, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE));
408 OUT_RING(ring, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s[FS].constlen) |
409 0x80000000 | /* XXX */
410 COND(s[FS].v->frag_face, A4XX_SP_FS_CTRL_REG1_FACENESS) |
411 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG1_VARYING) |
412 COND(s[FS].v->frag_coord, A4XX_SP_FS_CTRL_REG1_FRAGCOORD));
413
414 OUT_PKT0(ring, REG_A4XX_SP_FS_OBJ_OFFSET_REG, 2);
415 OUT_RING(ring, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
416 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[FS].instroff));
417 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
418 }
419
420 OUT_PKT0(ring, REG_A4XX_SP_HS_OBJ_OFFSET_REG, 1);
421 OUT_RING(ring, A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
422 A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[HS].instroff));
423
424 OUT_PKT0(ring, REG_A4XX_SP_DS_OBJ_OFFSET_REG, 1);
425 OUT_RING(ring, A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
426 A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[DS].instroff));
427
428 OUT_PKT0(ring, REG_A4XX_SP_GS_OBJ_OFFSET_REG, 1);
429 OUT_RING(ring, A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
430 A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[GS].instroff));
431
432 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL2, 1);
433 OUT_RING(ring, A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(0) |
434 COND(s[FS].v->total_in > 0, A4XX_RB_RENDER_CONTROL2_VARYING) |
435 COND(s[FS].v->frag_face, A4XX_RB_RENDER_CONTROL2_FACENESS) |
436 COND(s[FS].v->frag_coord, A4XX_RB_RENDER_CONTROL2_XCOORD |
437 A4XX_RB_RENDER_CONTROL2_YCOORD |
438 A4XX_RB_RENDER_CONTROL2_ZCOORD |
439 A4XX_RB_RENDER_CONTROL2_WCOORD));
440
441 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT_REG, 1);
442 OUT_RING(ring, A4XX_RB_FS_OUTPUT_REG_MRT(nr) |
443 COND(s[FS].v->writes_pos, A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z));
444
445 OUT_PKT0(ring, REG_A4XX_SP_FS_OUTPUT_REG, 1);
446 OUT_RING(ring, A4XX_SP_FS_OUTPUT_REG_MRT(nr) |
447 COND(s[FS].v->writes_pos, A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
448 A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid));
449
450 OUT_PKT0(ring, REG_A4XX_SP_FS_MRT_REG(0), 8);
451 for (i = 0; i < 8; i++) {
452 enum a4xx_color_fmt format = 0;
453 bool srgb = false;
454 if (i < nr) {
455 format = fd4_emit_format(bufs[i]);
456 if (bufs[i] && !emit->no_decode_srgb)
457 srgb = util_format_is_srgb(bufs[i]->format);
458 }
459 OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
460 A4XX_SP_FS_MRT_REG_MRTFORMAT(format) |
461 COND(srgb, A4XX_SP_FS_MRT_REG_COLOR_SRGB) |
462 COND(emit->key.half_precision,
463 A4XX_SP_FS_MRT_REG_HALF_PRECISION));
464 }
465
466 if (emit->key.binning_pass) {
467 OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
468 OUT_RING(ring, A4XX_VPC_ATTR_THRDASSIGN(1) |
469 0x40000000 | /* XXX */
470 COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
471 OUT_RING(ring, 0x00000000);
472 } else {
473 uint32_t vinterp[8], vpsrepl[8];
474
475 memset(vinterp, 0, sizeof(vinterp));
476 memset(vpsrepl, 0, sizeof(vpsrepl));
477
478 /* looks like we need to do int varyings in the frag
479 * shader on a4xx (no flatshad reg? or a420.0 bug?):
480 *
481 * (sy)(ss)nop
482 * (sy)ldlv.u32 r0.x,l[r0.x], 1
483 * ldlv.u32 r0.y,l[r0.x+1], 1
484 * (ss)bary.f (ei)r63.x, 0, r0.x
485 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
486 * (rpt5)nop
487 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
488 *
489 * Possibly on later a4xx variants we'll be able to use
490 * something like the code below instead of workaround
491 * in the shader:
492 */
493 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
494 for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
495 /* NOTE: varyings are packed, so if compmask is 0xb
496 * then first, third, and fourth component occupy
497 * three consecutive varying slots:
498 */
499 unsigned compmask = s[FS].v->inputs[j].compmask;
500
501 uint32_t inloc = s[FS].v->inputs[j].inloc;
502
503 if ((s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) ||
504 (s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
505 uint32_t loc = inloc;
506
507 for (i = 0; i < 4; i++) {
508 if (compmask & (1 << i)) {
509 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
510 //flatshade[loc / 32] |= 1 << (loc % 32);
511 loc++;
512 }
513 }
514 }
515
516 gl_varying_slot slot = s[FS].v->inputs[j].slot;
517
518 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
519 if (slot >= VARYING_SLOT_VAR0) {
520 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
521 /* Replace the .xy coordinates with S/T from the point sprite. Set
522 * interpolation bits for .zw such that they become .01
523 */
524 if (emit->sprite_coord_enable & texmask) {
525 /* mask is two 2-bit fields, where:
526 * '01' -> S
527 * '10' -> T
528 * '11' -> 1 - T (flip mode)
529 */
530 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
531 uint32_t loc = inloc;
532 if (compmask & 0x1) {
533 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
534 loc++;
535 }
536 if (compmask & 0x2) {
537 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
538 loc++;
539 }
540 if (compmask & 0x4) {
541 /* .z <- 0.0f */
542 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
543 loc++;
544 }
545 if (compmask & 0x8) {
546 /* .w <- 1.0f */
547 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
548 loc++;
549 }
550 }
551 }
552 }
553
554 OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
555 OUT_RING(ring, A4XX_VPC_ATTR_TOTALATTR(s[FS].v->total_in) |
556 A4XX_VPC_ATTR_THRDASSIGN(1) |
557 COND(s[FS].v->total_in > 0, A4XX_VPC_ATTR_ENABLE) |
558 0x40000000 | /* XXX */
559 COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
560 OUT_RING(ring, A4XX_VPC_PACK_NUMFPNONPOSVAR(s[FS].v->total_in) |
561 A4XX_VPC_PACK_NUMNONPOSVSVAR(s[FS].v->total_in));
562
563 OUT_PKT0(ring, REG_A4XX_VPC_VARYING_INTERP_MODE(0), 8);
564 for (i = 0; i < 8; i++)
565 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
566
567 OUT_PKT0(ring, REG_A4XX_VPC_VARYING_PS_REPL_MODE(0), 8);
568 for (i = 0; i < 8; i++)
569 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
570 }
571
572 if (s[VS].instrlen)
573 emit_shader(ring, s[VS].v);
574
575 if (!emit->key.binning_pass)
576 if (s[FS].instrlen)
577 emit_shader(ring, s[FS].v);
578 }
579
580 void
fd4_prog_init(struct pipe_context * pctx)581 fd4_prog_init(struct pipe_context *pctx)
582 {
583 pctx->create_fs_state = fd4_fp_state_create;
584 pctx->delete_fs_state = fd4_fp_state_delete;
585
586 pctx->create_vs_state = fd4_vp_state_create;
587 pctx->delete_vs_state = fd4_vp_state_delete;
588
589 fd_prog_init(pctx);
590 }
591