1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
4 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
5 * (C) Copyright 2008 Armadeus Systems nc
6 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <environment.h>
13 #include <malloc.h>
14 #include <memalign.h>
15 #include <miiphy.h>
16 #include <net.h>
17 #include <netdev.h>
18 #include "fec_mxc.h"
19
20 #include <asm/io.h>
21 #include <linux/errno.h>
22 #include <linux/compiler.h>
23
24 #include <asm/arch/clock.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/mach-imx/sys_proto.h>
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 /*
31 * Timeout the transfer after 5 mS. This is usually a bit more, since
32 * the code in the tightloops this timeout is used in adds some overhead.
33 */
34 #define FEC_XFER_TIMEOUT 5000
35
36 /*
37 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
38 * 64-byte alignment in the DMA RX FEC buffer.
39 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
40 * satisfies the alignment on other SoCs (32-bytes)
41 */
42 #define FEC_DMA_RX_MINALIGN 64
43
44 #ifndef CONFIG_MII
45 #error "CONFIG_MII has to be defined!"
46 #endif
47
48 #ifndef CONFIG_FEC_XCV_TYPE
49 #define CONFIG_FEC_XCV_TYPE MII100
50 #endif
51
52 /*
53 * The i.MX28 operates with packets in big endian. We need to swap them before
54 * sending and after receiving.
55 */
56 #ifdef CONFIG_MX28
57 #define CONFIG_FEC_MXC_SWAP_PACKET
58 #endif
59
60 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
61
62 /* Check various alignment issues at compile time */
63 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
64 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
65 #endif
66
67 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
68 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
69 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
70 #endif
71
72 #undef DEBUG
73
74 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
swap_packet(uint32_t * packet,int length)75 static void swap_packet(uint32_t *packet, int length)
76 {
77 int i;
78
79 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
80 packet[i] = __swab32(packet[i]);
81 }
82 #endif
83
84 /* MII-interface related functions */
fec_mdio_read(struct ethernet_regs * eth,uint8_t phyaddr,uint8_t regaddr)85 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
86 uint8_t regaddr)
87 {
88 uint32_t reg; /* convenient holder for the PHY register */
89 uint32_t phy; /* convenient holder for the PHY */
90 uint32_t start;
91 int val;
92
93 /*
94 * reading from any PHY's register is done by properly
95 * programming the FEC's MII data register.
96 */
97 writel(FEC_IEVENT_MII, ð->ievent);
98 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
99 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
100
101 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
102 phy | reg, ð->mii_data);
103
104 /* wait for the related interrupt */
105 start = get_timer(0);
106 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
107 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
108 printf("Read MDIO failed...\n");
109 return -1;
110 }
111 }
112
113 /* clear mii interrupt bit */
114 writel(FEC_IEVENT_MII, ð->ievent);
115
116 /* it's now safe to read the PHY's register */
117 val = (unsigned short)readl(ð->mii_data);
118 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
119 regaddr, val);
120 return val;
121 }
122
fec_mii_setspeed(struct ethernet_regs * eth)123 static void fec_mii_setspeed(struct ethernet_regs *eth)
124 {
125 /*
126 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
127 * and do not drop the Preamble.
128 *
129 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
130 * MII_SPEED) register that defines the MDIO output hold time. Earlier
131 * versions are RAZ there, so just ignore the difference and write the
132 * register always.
133 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
134 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
135 * output.
136 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
137 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
138 * holdtime cannot result in a value greater than 3.
139 */
140 u32 pclk = imx_get_fecclk();
141 u32 speed = DIV_ROUND_UP(pclk, 5000000);
142 u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
143 #ifdef FEC_QUIRK_ENET_MAC
144 speed--;
145 #endif
146 writel(speed << 1 | hold << 8, ð->mii_speed);
147 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
148 }
149
fec_mdio_write(struct ethernet_regs * eth,uint8_t phyaddr,uint8_t regaddr,uint16_t data)150 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
151 uint8_t regaddr, uint16_t data)
152 {
153 uint32_t reg; /* convenient holder for the PHY register */
154 uint32_t phy; /* convenient holder for the PHY */
155 uint32_t start;
156
157 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
158 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
159
160 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
161 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
162
163 /* wait for the MII interrupt */
164 start = get_timer(0);
165 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
166 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
167 printf("Write MDIO failed...\n");
168 return -1;
169 }
170 }
171
172 /* clear MII interrupt bit */
173 writel(FEC_IEVENT_MII, ð->ievent);
174 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
175 regaddr, data);
176
177 return 0;
178 }
179
fec_phy_read(struct mii_dev * bus,int phyaddr,int dev_addr,int regaddr)180 static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
181 int regaddr)
182 {
183 return fec_mdio_read(bus->priv, phyaddr, regaddr);
184 }
185
fec_phy_write(struct mii_dev * bus,int phyaddr,int dev_addr,int regaddr,u16 data)186 static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
187 int regaddr, u16 data)
188 {
189 return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
190 }
191
192 #ifndef CONFIG_PHYLIB
miiphy_restart_aneg(struct eth_device * dev)193 static int miiphy_restart_aneg(struct eth_device *dev)
194 {
195 int ret = 0;
196 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
197 struct fec_priv *fec = (struct fec_priv *)dev->priv;
198 struct ethernet_regs *eth = fec->bus->priv;
199
200 /*
201 * Wake up from sleep if necessary
202 * Reset PHY, then delay 300ns
203 */
204 #ifdef CONFIG_MX27
205 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
206 #endif
207 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
208 udelay(1000);
209
210 /* Set the auto-negotiation advertisement register bits */
211 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
212 LPA_100FULL | LPA_100HALF | LPA_10FULL |
213 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
214 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
215 BMCR_ANENABLE | BMCR_ANRESTART);
216
217 if (fec->mii_postcall)
218 ret = fec->mii_postcall(fec->phy_id);
219
220 #endif
221 return ret;
222 }
223
224 #ifndef CONFIG_FEC_FIXED_SPEED
miiphy_wait_aneg(struct eth_device * dev)225 static int miiphy_wait_aneg(struct eth_device *dev)
226 {
227 uint32_t start;
228 int status;
229 struct fec_priv *fec = (struct fec_priv *)dev->priv;
230 struct ethernet_regs *eth = fec->bus->priv;
231
232 /* Wait for AN completion */
233 start = get_timer(0);
234 do {
235 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
236 printf("%s: Autonegotiation timeout\n", dev->name);
237 return -1;
238 }
239
240 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
241 if (status < 0) {
242 printf("%s: Autonegotiation failed. status: %d\n",
243 dev->name, status);
244 return -1;
245 }
246 } while (!(status & BMSR_LSTATUS));
247
248 return 0;
249 }
250 #endif /* CONFIG_FEC_FIXED_SPEED */
251 #endif
252
fec_rx_task_enable(struct fec_priv * fec)253 static int fec_rx_task_enable(struct fec_priv *fec)
254 {
255 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
256 return 0;
257 }
258
fec_rx_task_disable(struct fec_priv * fec)259 static int fec_rx_task_disable(struct fec_priv *fec)
260 {
261 return 0;
262 }
263
fec_tx_task_enable(struct fec_priv * fec)264 static int fec_tx_task_enable(struct fec_priv *fec)
265 {
266 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
267 return 0;
268 }
269
fec_tx_task_disable(struct fec_priv * fec)270 static int fec_tx_task_disable(struct fec_priv *fec)
271 {
272 return 0;
273 }
274
275 /**
276 * Initialize receive task's buffer descriptors
277 * @param[in] fec all we know about the device yet
278 * @param[in] count receive buffer count to be allocated
279 * @param[in] dsize desired size of each receive buffer
280 * @return 0 on success
281 *
282 * Init all RX descriptors to default values.
283 */
fec_rbd_init(struct fec_priv * fec,int count,int dsize)284 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
285 {
286 uint32_t size;
287 ulong data;
288 int i;
289
290 /*
291 * Reload the RX descriptors with default values and wipe
292 * the RX buffers.
293 */
294 size = roundup(dsize, ARCH_DMA_MINALIGN);
295 for (i = 0; i < count; i++) {
296 data = fec->rbd_base[i].data_pointer;
297 memset((void *)data, 0, dsize);
298 flush_dcache_range(data, data + size);
299
300 fec->rbd_base[i].status = FEC_RBD_EMPTY;
301 fec->rbd_base[i].data_length = 0;
302 }
303
304 /* Mark the last RBD to close the ring. */
305 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
306 fec->rbd_index = 0;
307
308 flush_dcache_range((ulong)fec->rbd_base,
309 (ulong)fec->rbd_base + size);
310 }
311
312 /**
313 * Initialize transmit task's buffer descriptors
314 * @param[in] fec all we know about the device yet
315 *
316 * Transmit buffers are created externally. We only have to init the BDs here.\n
317 * Note: There is a race condition in the hardware. When only one BD is in
318 * use it must be marked with the WRAP bit to use it for every transmitt.
319 * This bit in combination with the READY bit results into double transmit
320 * of each data buffer. It seems the state machine checks READY earlier then
321 * resetting it after the first transfer.
322 * Using two BDs solves this issue.
323 */
fec_tbd_init(struct fec_priv * fec)324 static void fec_tbd_init(struct fec_priv *fec)
325 {
326 ulong addr = (ulong)fec->tbd_base;
327 unsigned size = roundup(2 * sizeof(struct fec_bd),
328 ARCH_DMA_MINALIGN);
329
330 memset(fec->tbd_base, 0, size);
331 fec->tbd_base[0].status = 0;
332 fec->tbd_base[1].status = FEC_TBD_WRAP;
333 fec->tbd_index = 0;
334 flush_dcache_range(addr, addr + size);
335 }
336
337 /**
338 * Mark the given read buffer descriptor as free
339 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
340 * @param[in] prbd buffer descriptor to mark free again
341 */
fec_rbd_clean(int last,struct fec_bd * prbd)342 static void fec_rbd_clean(int last, struct fec_bd *prbd)
343 {
344 unsigned short flags = FEC_RBD_EMPTY;
345 if (last)
346 flags |= FEC_RBD_WRAP;
347 writew(flags, &prbd->status);
348 writew(0, &prbd->data_length);
349 }
350
fec_get_hwaddr(int dev_id,unsigned char * mac)351 static int fec_get_hwaddr(int dev_id, unsigned char *mac)
352 {
353 imx_get_mac_from_fuse(dev_id, mac);
354 return !is_valid_ethaddr(mac);
355 }
356
357 #ifdef CONFIG_DM_ETH
fecmxc_set_hwaddr(struct udevice * dev)358 static int fecmxc_set_hwaddr(struct udevice *dev)
359 #else
360 static int fec_set_hwaddr(struct eth_device *dev)
361 #endif
362 {
363 #ifdef CONFIG_DM_ETH
364 struct fec_priv *fec = dev_get_priv(dev);
365 struct eth_pdata *pdata = dev_get_platdata(dev);
366 uchar *mac = pdata->enetaddr;
367 #else
368 uchar *mac = dev->enetaddr;
369 struct fec_priv *fec = (struct fec_priv *)dev->priv;
370 #endif
371
372 writel(0, &fec->eth->iaddr1);
373 writel(0, &fec->eth->iaddr2);
374 writel(0, &fec->eth->gaddr1);
375 writel(0, &fec->eth->gaddr2);
376
377 /* Set physical address */
378 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
379 &fec->eth->paddr1);
380 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
381
382 return 0;
383 }
384
385 /* Do initial configuration of the FEC registers */
fec_reg_setup(struct fec_priv * fec)386 static void fec_reg_setup(struct fec_priv *fec)
387 {
388 uint32_t rcntrl;
389
390 /* Set interrupt mask register */
391 writel(0x00000000, &fec->eth->imask);
392
393 /* Clear FEC-Lite interrupt event register(IEVENT) */
394 writel(0xffffffff, &fec->eth->ievent);
395
396 /* Set FEC-Lite receive control register(R_CNTRL): */
397
398 /* Start with frame length = 1518, common for all modes. */
399 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
400 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
401 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
402 if (fec->xcv_type == RGMII)
403 rcntrl |= FEC_RCNTRL_RGMII;
404 else if (fec->xcv_type == RMII)
405 rcntrl |= FEC_RCNTRL_RMII;
406
407 writel(rcntrl, &fec->eth->r_cntrl);
408 }
409
410 /**
411 * Start the FEC engine
412 * @param[in] dev Our device to handle
413 */
414 #ifdef CONFIG_DM_ETH
fec_open(struct udevice * dev)415 static int fec_open(struct udevice *dev)
416 #else
417 static int fec_open(struct eth_device *edev)
418 #endif
419 {
420 #ifdef CONFIG_DM_ETH
421 struct fec_priv *fec = dev_get_priv(dev);
422 #else
423 struct fec_priv *fec = (struct fec_priv *)edev->priv;
424 #endif
425 int speed;
426 ulong addr, size;
427 int i;
428
429 debug("fec_open: fec_open(dev)\n");
430 /* full-duplex, heartbeat disabled */
431 writel(1 << 2, &fec->eth->x_cntrl);
432 fec->rbd_index = 0;
433
434 /* Invalidate all descriptors */
435 for (i = 0; i < FEC_RBD_NUM - 1; i++)
436 fec_rbd_clean(0, &fec->rbd_base[i]);
437 fec_rbd_clean(1, &fec->rbd_base[i]);
438
439 /* Flush the descriptors into RAM */
440 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
441 ARCH_DMA_MINALIGN);
442 addr = (ulong)fec->rbd_base;
443 flush_dcache_range(addr, addr + size);
444
445 #ifdef FEC_QUIRK_ENET_MAC
446 /* Enable ENET HW endian SWAP */
447 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
448 &fec->eth->ecntrl);
449 /* Enable ENET store and forward mode */
450 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
451 &fec->eth->x_wmrk);
452 #endif
453 /* Enable FEC-Lite controller */
454 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
455 &fec->eth->ecntrl);
456
457 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
458 udelay(100);
459
460 /* setup the MII gasket for RMII mode */
461 /* disable the gasket */
462 writew(0, &fec->eth->miigsk_enr);
463
464 /* wait for the gasket to be disabled */
465 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
466 udelay(2);
467
468 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
469 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
470
471 /* re-enable the gasket */
472 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
473
474 /* wait until MII gasket is ready */
475 int max_loops = 10;
476 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
477 if (--max_loops <= 0) {
478 printf("WAIT for MII Gasket ready timed out\n");
479 break;
480 }
481 }
482 #endif
483
484 #ifdef CONFIG_PHYLIB
485 {
486 /* Start up the PHY */
487 int ret = phy_startup(fec->phydev);
488
489 if (ret) {
490 printf("Could not initialize PHY %s\n",
491 fec->phydev->dev->name);
492 return ret;
493 }
494 speed = fec->phydev->speed;
495 }
496 #elif CONFIG_FEC_FIXED_SPEED
497 speed = CONFIG_FEC_FIXED_SPEED;
498 #else
499 miiphy_wait_aneg(edev);
500 speed = miiphy_speed(edev->name, fec->phy_id);
501 miiphy_duplex(edev->name, fec->phy_id);
502 #endif
503
504 #ifdef FEC_QUIRK_ENET_MAC
505 {
506 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
507 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
508 if (speed == _1000BASET)
509 ecr |= FEC_ECNTRL_SPEED;
510 else if (speed != _100BASET)
511 rcr |= FEC_RCNTRL_RMII_10T;
512 writel(ecr, &fec->eth->ecntrl);
513 writel(rcr, &fec->eth->r_cntrl);
514 }
515 #endif
516 debug("%s:Speed=%i\n", __func__, speed);
517
518 /* Enable SmartDMA receive task */
519 fec_rx_task_enable(fec);
520
521 udelay(100000);
522 return 0;
523 }
524
525 #ifdef CONFIG_DM_ETH
fecmxc_init(struct udevice * dev)526 static int fecmxc_init(struct udevice *dev)
527 #else
528 static int fec_init(struct eth_device *dev, bd_t *bd)
529 #endif
530 {
531 #ifdef CONFIG_DM_ETH
532 struct fec_priv *fec = dev_get_priv(dev);
533 #else
534 struct fec_priv *fec = (struct fec_priv *)dev->priv;
535 #endif
536 u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
537 u8 *i;
538 ulong addr;
539
540 /* Initialize MAC address */
541 #ifdef CONFIG_DM_ETH
542 fecmxc_set_hwaddr(dev);
543 #else
544 fec_set_hwaddr(dev);
545 #endif
546
547 /* Setup transmit descriptors, there are two in total. */
548 fec_tbd_init(fec);
549
550 /* Setup receive descriptors. */
551 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
552
553 fec_reg_setup(fec);
554
555 if (fec->xcv_type != SEVENWIRE)
556 fec_mii_setspeed(fec->bus->priv);
557
558 /* Set Opcode/Pause Duration Register */
559 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
560 writel(0x2, &fec->eth->x_wmrk);
561
562 /* Set multicast address filter */
563 writel(0x00000000, &fec->eth->gaddr1);
564 writel(0x00000000, &fec->eth->gaddr2);
565
566 /* Do not access reserved register */
567 if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {
568 /* clear MIB RAM */
569 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
570 writel(0, i);
571
572 /* FIFO receive start register */
573 writel(0x520, &fec->eth->r_fstart);
574 }
575
576 /* size and address of each buffer */
577 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
578
579 addr = (ulong)fec->tbd_base;
580 writel((uint32_t)addr, &fec->eth->etdsr);
581
582 addr = (ulong)fec->rbd_base;
583 writel((uint32_t)addr, &fec->eth->erdsr);
584
585 #ifndef CONFIG_PHYLIB
586 if (fec->xcv_type != SEVENWIRE)
587 miiphy_restart_aneg(dev);
588 #endif
589 fec_open(dev);
590 return 0;
591 }
592
593 /**
594 * Halt the FEC engine
595 * @param[in] dev Our device to handle
596 */
597 #ifdef CONFIG_DM_ETH
fecmxc_halt(struct udevice * dev)598 static void fecmxc_halt(struct udevice *dev)
599 #else
600 static void fec_halt(struct eth_device *dev)
601 #endif
602 {
603 #ifdef CONFIG_DM_ETH
604 struct fec_priv *fec = dev_get_priv(dev);
605 #else
606 struct fec_priv *fec = (struct fec_priv *)dev->priv;
607 #endif
608 int counter = 0xffff;
609
610 /* issue graceful stop command to the FEC transmitter if necessary */
611 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
612 &fec->eth->x_cntrl);
613
614 debug("eth_halt: wait for stop regs\n");
615 /* wait for graceful stop to register */
616 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
617 udelay(1);
618
619 /* Disable SmartDMA tasks */
620 fec_tx_task_disable(fec);
621 fec_rx_task_disable(fec);
622
623 /*
624 * Disable the Ethernet Controller
625 * Note: this will also reset the BD index counter!
626 */
627 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
628 &fec->eth->ecntrl);
629 fec->rbd_index = 0;
630 fec->tbd_index = 0;
631 debug("eth_halt: done\n");
632 }
633
634 /**
635 * Transmit one frame
636 * @param[in] dev Our ethernet device to handle
637 * @param[in] packet Pointer to the data to be transmitted
638 * @param[in] length Data count in bytes
639 * @return 0 on success
640 */
641 #ifdef CONFIG_DM_ETH
fecmxc_send(struct udevice * dev,void * packet,int length)642 static int fecmxc_send(struct udevice *dev, void *packet, int length)
643 #else
644 static int fec_send(struct eth_device *dev, void *packet, int length)
645 #endif
646 {
647 unsigned int status;
648 u32 size;
649 ulong addr, end;
650 int timeout = FEC_XFER_TIMEOUT;
651 int ret = 0;
652
653 /*
654 * This routine transmits one frame. This routine only accepts
655 * 6-byte Ethernet addresses.
656 */
657 #ifdef CONFIG_DM_ETH
658 struct fec_priv *fec = dev_get_priv(dev);
659 #else
660 struct fec_priv *fec = (struct fec_priv *)dev->priv;
661 #endif
662
663 /*
664 * Check for valid length of data.
665 */
666 if ((length > 1500) || (length <= 0)) {
667 printf("Payload (%d) too large\n", length);
668 return -1;
669 }
670
671 /*
672 * Setup the transmit buffer. We are always using the first buffer for
673 * transmission, the second will be empty and only used to stop the DMA
674 * engine. We also flush the packet to RAM here to avoid cache trouble.
675 */
676 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
677 swap_packet((uint32_t *)packet, length);
678 #endif
679
680 addr = (ulong)packet;
681 end = roundup(addr + length, ARCH_DMA_MINALIGN);
682 addr &= ~(ARCH_DMA_MINALIGN - 1);
683 flush_dcache_range(addr, end);
684
685 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
686 writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
687
688 /*
689 * update BD's status now
690 * This block:
691 * - is always the last in a chain (means no chain)
692 * - should transmitt the CRC
693 * - might be the last BD in the list, so the address counter should
694 * wrap (-> keep the WRAP flag)
695 */
696 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
697 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
698 writew(status, &fec->tbd_base[fec->tbd_index].status);
699
700 /*
701 * Flush data cache. This code flushes both TX descriptors to RAM.
702 * After this code, the descriptors will be safely in RAM and we
703 * can start DMA.
704 */
705 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
706 addr = (ulong)fec->tbd_base;
707 flush_dcache_range(addr, addr + size);
708
709 /*
710 * Below we read the DMA descriptor's last four bytes back from the
711 * DRAM. This is important in order to make sure that all WRITE
712 * operations on the bus that were triggered by previous cache FLUSH
713 * have completed.
714 *
715 * Otherwise, on MX28, it is possible to observe a corruption of the
716 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
717 * for the bus structure of MX28. The scenario is as follows:
718 *
719 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
720 * to DRAM due to flush_dcache_range()
721 * 2) ARM core writes the FEC registers via AHB_ARB2
722 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
723 *
724 * Note that 2) does sometimes finish before 1) due to reordering of
725 * WRITE accesses on the AHB bus, therefore triggering 3) before the
726 * DMA descriptor is fully written into DRAM. This results in occasional
727 * corruption of the DMA descriptor.
728 */
729 readl(addr + size - 4);
730
731 /* Enable SmartDMA transmit task */
732 fec_tx_task_enable(fec);
733
734 /*
735 * Wait until frame is sent. On each turn of the wait cycle, we must
736 * invalidate data cache to see what's really in RAM. Also, we need
737 * barrier here.
738 */
739 while (--timeout) {
740 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
741 break;
742 }
743
744 if (!timeout) {
745 ret = -EINVAL;
746 goto out;
747 }
748
749 /*
750 * The TDAR bit is cleared when the descriptors are all out from TX
751 * but on mx6solox we noticed that the READY bit is still not cleared
752 * right after TDAR.
753 * These are two distinct signals, and in IC simulation, we found that
754 * TDAR always gets cleared prior than the READY bit of last BD becomes
755 * cleared.
756 * In mx6solox, we use a later version of FEC IP. It looks like that
757 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
758 * version.
759 *
760 * Fix this by polling the READY bit of BD after the TDAR polling,
761 * which covers the mx6solox case and does not harm the other SoCs.
762 */
763 timeout = FEC_XFER_TIMEOUT;
764 while (--timeout) {
765 invalidate_dcache_range(addr, addr + size);
766 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
767 FEC_TBD_READY))
768 break;
769 }
770
771 if (!timeout)
772 ret = -EINVAL;
773
774 out:
775 debug("fec_send: status 0x%x index %d ret %i\n",
776 readw(&fec->tbd_base[fec->tbd_index].status),
777 fec->tbd_index, ret);
778 /* for next transmission use the other buffer */
779 if (fec->tbd_index)
780 fec->tbd_index = 0;
781 else
782 fec->tbd_index = 1;
783
784 return ret;
785 }
786
787 /**
788 * Pull one frame from the card
789 * @param[in] dev Our ethernet device to handle
790 * @return Length of packet read
791 */
792 #ifdef CONFIG_DM_ETH
fecmxc_recv(struct udevice * dev,int flags,uchar ** packetp)793 static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
794 #else
795 static int fec_recv(struct eth_device *dev)
796 #endif
797 {
798 #ifdef CONFIG_DM_ETH
799 struct fec_priv *fec = dev_get_priv(dev);
800 #else
801 struct fec_priv *fec = (struct fec_priv *)dev->priv;
802 #endif
803 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
804 unsigned long ievent;
805 int frame_length, len = 0;
806 uint16_t bd_status;
807 ulong addr, size, end;
808 int i;
809
810 #ifdef CONFIG_DM_ETH
811 *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
812 if (*packetp == 0) {
813 printf("%s: error allocating packetp\n", __func__);
814 return -ENOMEM;
815 }
816 #else
817 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
818 #endif
819
820 /* Check if any critical events have happened */
821 ievent = readl(&fec->eth->ievent);
822 writel(ievent, &fec->eth->ievent);
823 debug("fec_recv: ievent 0x%lx\n", ievent);
824 if (ievent & FEC_IEVENT_BABR) {
825 #ifdef CONFIG_DM_ETH
826 fecmxc_halt(dev);
827 fecmxc_init(dev);
828 #else
829 fec_halt(dev);
830 fec_init(dev, fec->bd);
831 #endif
832 printf("some error: 0x%08lx\n", ievent);
833 return 0;
834 }
835 if (ievent & FEC_IEVENT_HBERR) {
836 /* Heartbeat error */
837 writel(0x00000001 | readl(&fec->eth->x_cntrl),
838 &fec->eth->x_cntrl);
839 }
840 if (ievent & FEC_IEVENT_GRA) {
841 /* Graceful stop complete */
842 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
843 #ifdef CONFIG_DM_ETH
844 fecmxc_halt(dev);
845 #else
846 fec_halt(dev);
847 #endif
848 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
849 &fec->eth->x_cntrl);
850 #ifdef CONFIG_DM_ETH
851 fecmxc_init(dev);
852 #else
853 fec_init(dev, fec->bd);
854 #endif
855 }
856 }
857
858 /*
859 * Read the buffer status. Before the status can be read, the data cache
860 * must be invalidated, because the data in RAM might have been changed
861 * by DMA. The descriptors are properly aligned to cachelines so there's
862 * no need to worry they'd overlap.
863 *
864 * WARNING: By invalidating the descriptor here, we also invalidate
865 * the descriptors surrounding this one. Therefore we can NOT change the
866 * contents of this descriptor nor the surrounding ones. The problem is
867 * that in order to mark the descriptor as processed, we need to change
868 * the descriptor. The solution is to mark the whole cache line when all
869 * descriptors in the cache line are processed.
870 */
871 addr = (ulong)rbd;
872 addr &= ~(ARCH_DMA_MINALIGN - 1);
873 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
874 invalidate_dcache_range(addr, addr + size);
875
876 bd_status = readw(&rbd->status);
877 debug("fec_recv: status 0x%x\n", bd_status);
878
879 if (!(bd_status & FEC_RBD_EMPTY)) {
880 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
881 ((readw(&rbd->data_length) - 4) > 14)) {
882 /* Get buffer address and size */
883 addr = readl(&rbd->data_pointer);
884 frame_length = readw(&rbd->data_length) - 4;
885 /* Invalidate data cache over the buffer */
886 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
887 addr &= ~(ARCH_DMA_MINALIGN - 1);
888 invalidate_dcache_range(addr, end);
889
890 /* Fill the buffer and pass it to upper layers */
891 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
892 swap_packet((uint32_t *)addr, frame_length);
893 #endif
894
895 #ifdef CONFIG_DM_ETH
896 memcpy(*packetp, (char *)addr, frame_length);
897 #else
898 memcpy(buff, (char *)addr, frame_length);
899 net_process_received_packet(buff, frame_length);
900 #endif
901 len = frame_length;
902 } else {
903 if (bd_status & FEC_RBD_ERR)
904 debug("error frame: 0x%08lx 0x%08x\n",
905 addr, bd_status);
906 }
907
908 /*
909 * Free the current buffer, restart the engine and move forward
910 * to the next buffer. Here we check if the whole cacheline of
911 * descriptors was already processed and if so, we mark it free
912 * as whole.
913 */
914 size = RXDESC_PER_CACHELINE - 1;
915 if ((fec->rbd_index & size) == size) {
916 i = fec->rbd_index - size;
917 addr = (ulong)&fec->rbd_base[i];
918 for (; i <= fec->rbd_index ; i++) {
919 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
920 &fec->rbd_base[i]);
921 }
922 flush_dcache_range(addr,
923 addr + ARCH_DMA_MINALIGN);
924 }
925
926 fec_rx_task_enable(fec);
927 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
928 }
929 debug("fec_recv: stop\n");
930
931 return len;
932 }
933
fec_set_dev_name(char * dest,int dev_id)934 static void fec_set_dev_name(char *dest, int dev_id)
935 {
936 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
937 }
938
fec_alloc_descs(struct fec_priv * fec)939 static int fec_alloc_descs(struct fec_priv *fec)
940 {
941 unsigned int size;
942 int i;
943 uint8_t *data;
944 ulong addr;
945
946 /* Allocate TX descriptors. */
947 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
948 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
949 if (!fec->tbd_base)
950 goto err_tx;
951
952 /* Allocate RX descriptors. */
953 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
954 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
955 if (!fec->rbd_base)
956 goto err_rx;
957
958 memset(fec->rbd_base, 0, size);
959
960 /* Allocate RX buffers. */
961
962 /* Maximum RX buffer size. */
963 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
964 for (i = 0; i < FEC_RBD_NUM; i++) {
965 data = memalign(FEC_DMA_RX_MINALIGN, size);
966 if (!data) {
967 printf("%s: error allocating rxbuf %d\n", __func__, i);
968 goto err_ring;
969 }
970
971 memset(data, 0, size);
972
973 addr = (ulong)data;
974 fec->rbd_base[i].data_pointer = (uint32_t)addr;
975 fec->rbd_base[i].status = FEC_RBD_EMPTY;
976 fec->rbd_base[i].data_length = 0;
977 /* Flush the buffer to memory. */
978 flush_dcache_range(addr, addr + size);
979 }
980
981 /* Mark the last RBD to close the ring. */
982 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
983
984 fec->rbd_index = 0;
985 fec->tbd_index = 0;
986
987 return 0;
988
989 err_ring:
990 for (; i >= 0; i--) {
991 addr = fec->rbd_base[i].data_pointer;
992 free((void *)addr);
993 }
994 free(fec->rbd_base);
995 err_rx:
996 free(fec->tbd_base);
997 err_tx:
998 return -ENOMEM;
999 }
1000
fec_free_descs(struct fec_priv * fec)1001 static void fec_free_descs(struct fec_priv *fec)
1002 {
1003 int i;
1004 ulong addr;
1005
1006 for (i = 0; i < FEC_RBD_NUM; i++) {
1007 addr = fec->rbd_base[i].data_pointer;
1008 free((void *)addr);
1009 }
1010 free(fec->rbd_base);
1011 free(fec->tbd_base);
1012 }
1013
fec_get_miibus(ulong base_addr,int dev_id)1014 struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
1015 {
1016 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1017 struct mii_dev *bus;
1018 int ret;
1019
1020 bus = mdio_alloc();
1021 if (!bus) {
1022 printf("mdio_alloc failed\n");
1023 return NULL;
1024 }
1025 bus->read = fec_phy_read;
1026 bus->write = fec_phy_write;
1027 bus->priv = eth;
1028 fec_set_dev_name(bus->name, dev_id);
1029
1030 ret = mdio_register(bus);
1031 if (ret) {
1032 printf("mdio_register failed\n");
1033 free(bus);
1034 return NULL;
1035 }
1036 fec_mii_setspeed(eth);
1037 return bus;
1038 }
1039
1040 #ifndef CONFIG_DM_ETH
1041 #ifdef CONFIG_PHYLIB
fec_probe(bd_t * bd,int dev_id,uint32_t base_addr,struct mii_dev * bus,struct phy_device * phydev)1042 int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1043 struct mii_dev *bus, struct phy_device *phydev)
1044 #else
1045 static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1046 struct mii_dev *bus, int phy_id)
1047 #endif
1048 {
1049 struct eth_device *edev;
1050 struct fec_priv *fec;
1051 unsigned char ethaddr[6];
1052 char mac[16];
1053 uint32_t start;
1054 int ret = 0;
1055
1056 /* create and fill edev struct */
1057 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
1058 if (!edev) {
1059 puts("fec_mxc: not enough malloc memory for eth_device\n");
1060 ret = -ENOMEM;
1061 goto err1;
1062 }
1063
1064 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
1065 if (!fec) {
1066 puts("fec_mxc: not enough malloc memory for fec_priv\n");
1067 ret = -ENOMEM;
1068 goto err2;
1069 }
1070
1071 memset(edev, 0, sizeof(*edev));
1072 memset(fec, 0, sizeof(*fec));
1073
1074 ret = fec_alloc_descs(fec);
1075 if (ret)
1076 goto err3;
1077
1078 edev->priv = fec;
1079 edev->init = fec_init;
1080 edev->send = fec_send;
1081 edev->recv = fec_recv;
1082 edev->halt = fec_halt;
1083 edev->write_hwaddr = fec_set_hwaddr;
1084
1085 fec->eth = (struct ethernet_regs *)(ulong)base_addr;
1086 fec->bd = bd;
1087
1088 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
1089
1090 /* Reset chip. */
1091 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
1092 start = get_timer(0);
1093 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1094 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1095 printf("FEC MXC: Timeout resetting chip\n");
1096 goto err4;
1097 }
1098 udelay(10);
1099 }
1100
1101 fec_reg_setup(fec);
1102 fec_set_dev_name(edev->name, dev_id);
1103 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
1104 fec->bus = bus;
1105 fec_mii_setspeed(bus->priv);
1106 #ifdef CONFIG_PHYLIB
1107 fec->phydev = phydev;
1108 phy_connect_dev(phydev, edev);
1109 /* Configure phy */
1110 phy_config(phydev);
1111 #else
1112 fec->phy_id = phy_id;
1113 #endif
1114 eth_register(edev);
1115 /* only support one eth device, the index number pointed by dev_id */
1116 edev->index = fec->dev_id;
1117
1118 if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
1119 debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
1120 memcpy(edev->enetaddr, ethaddr, 6);
1121 if (fec->dev_id)
1122 sprintf(mac, "eth%daddr", fec->dev_id);
1123 else
1124 strcpy(mac, "ethaddr");
1125 if (!env_get(mac))
1126 eth_env_set_enetaddr(mac, ethaddr);
1127 }
1128 return ret;
1129 err4:
1130 fec_free_descs(fec);
1131 err3:
1132 free(fec);
1133 err2:
1134 free(edev);
1135 err1:
1136 return ret;
1137 }
1138
fecmxc_initialize_multi(bd_t * bd,int dev_id,int phy_id,uint32_t addr)1139 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1140 {
1141 uint32_t base_mii;
1142 struct mii_dev *bus = NULL;
1143 #ifdef CONFIG_PHYLIB
1144 struct phy_device *phydev = NULL;
1145 #endif
1146 int ret;
1147
1148 #ifdef CONFIG_FEC_MXC_MDIO_BASE
1149 /*
1150 * The i.MX28 has two ethernet interfaces, but they are not equal.
1151 * Only the first one can access the MDIO bus.
1152 */
1153 base_mii = CONFIG_FEC_MXC_MDIO_BASE;
1154 #else
1155 base_mii = addr;
1156 #endif
1157 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1158 bus = fec_get_miibus(base_mii, dev_id);
1159 if (!bus)
1160 return -ENOMEM;
1161 #ifdef CONFIG_PHYLIB
1162 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1163 if (!phydev) {
1164 mdio_unregister(bus);
1165 free(bus);
1166 return -ENOMEM;
1167 }
1168 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1169 #else
1170 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1171 #endif
1172 if (ret) {
1173 #ifdef CONFIG_PHYLIB
1174 free(phydev);
1175 #endif
1176 mdio_unregister(bus);
1177 free(bus);
1178 }
1179 return ret;
1180 }
1181
1182 #ifdef CONFIG_FEC_MXC_PHYADDR
fecmxc_initialize(bd_t * bd)1183 int fecmxc_initialize(bd_t *bd)
1184 {
1185 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1186 IMX_FEC_BASE);
1187 }
1188 #endif
1189
1190 #ifndef CONFIG_PHYLIB
fecmxc_register_mii_postcall(struct eth_device * dev,int (* cb)(int))1191 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1192 {
1193 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1194 fec->mii_postcall = cb;
1195 return 0;
1196 }
1197 #endif
1198
1199 #else
1200
fecmxc_read_rom_hwaddr(struct udevice * dev)1201 static int fecmxc_read_rom_hwaddr(struct udevice *dev)
1202 {
1203 struct fec_priv *priv = dev_get_priv(dev);
1204 struct eth_pdata *pdata = dev_get_platdata(dev);
1205
1206 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
1207 }
1208
fecmxc_free_pkt(struct udevice * dev,uchar * packet,int length)1209 static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
1210 {
1211 if (packet)
1212 free(packet);
1213
1214 return 0;
1215 }
1216
1217 static const struct eth_ops fecmxc_ops = {
1218 .start = fecmxc_init,
1219 .send = fecmxc_send,
1220 .recv = fecmxc_recv,
1221 .free_pkt = fecmxc_free_pkt,
1222 .stop = fecmxc_halt,
1223 .write_hwaddr = fecmxc_set_hwaddr,
1224 .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
1225 };
1226
fec_phy_init(struct fec_priv * priv,struct udevice * dev)1227 static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1228 {
1229 struct phy_device *phydev;
1230 int mask = 0xffffffff;
1231
1232 #ifdef CONFIG_FEC_MXC_PHYADDR
1233 mask = 1 << CONFIG_FEC_MXC_PHYADDR;
1234 #endif
1235
1236 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
1237 if (!phydev)
1238 return -ENODEV;
1239
1240 phy_connect_dev(phydev, dev);
1241
1242 priv->phydev = phydev;
1243 phy_config(phydev);
1244
1245 return 0;
1246 }
1247
fecmxc_probe(struct udevice * dev)1248 static int fecmxc_probe(struct udevice *dev)
1249 {
1250 struct eth_pdata *pdata = dev_get_platdata(dev);
1251 struct fec_priv *priv = dev_get_priv(dev);
1252 struct mii_dev *bus = NULL;
1253 uint32_t start;
1254 int ret;
1255
1256 ret = fec_alloc_descs(priv);
1257 if (ret)
1258 return ret;
1259
1260 /* Reset chip. */
1261 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
1262 &priv->eth->ecntrl);
1263 start = get_timer(0);
1264 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1265 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1266 printf("FEC MXC: Timeout reseting chip\n");
1267 goto err_timeout;
1268 }
1269 udelay(10);
1270 }
1271
1272 fec_reg_setup(priv);
1273
1274 priv->dev_id = dev->seq;
1275 #ifdef CONFIG_FEC_MXC_MDIO_BASE
1276 bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
1277 #else
1278 bus = fec_get_miibus((ulong)priv->eth, dev->seq);
1279 #endif
1280 if (!bus) {
1281 ret = -ENOMEM;
1282 goto err_mii;
1283 }
1284
1285 priv->bus = bus;
1286 priv->xcv_type = CONFIG_FEC_XCV_TYPE;
1287 priv->interface = pdata->phy_interface;
1288 ret = fec_phy_init(priv, dev);
1289 if (ret)
1290 goto err_phy;
1291
1292 return 0;
1293
1294 err_phy:
1295 mdio_unregister(bus);
1296 free(bus);
1297 err_mii:
1298 err_timeout:
1299 fec_free_descs(priv);
1300 return ret;
1301 }
1302
fecmxc_remove(struct udevice * dev)1303 static int fecmxc_remove(struct udevice *dev)
1304 {
1305 struct fec_priv *priv = dev_get_priv(dev);
1306
1307 free(priv->phydev);
1308 fec_free_descs(priv);
1309 mdio_unregister(priv->bus);
1310 mdio_free(priv->bus);
1311
1312 return 0;
1313 }
1314
fecmxc_ofdata_to_platdata(struct udevice * dev)1315 static int fecmxc_ofdata_to_platdata(struct udevice *dev)
1316 {
1317 struct eth_pdata *pdata = dev_get_platdata(dev);
1318 struct fec_priv *priv = dev_get_priv(dev);
1319 const char *phy_mode;
1320
1321 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
1322 priv->eth = (struct ethernet_regs *)pdata->iobase;
1323
1324 pdata->phy_interface = -1;
1325 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1326 NULL);
1327 if (phy_mode)
1328 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1329 if (pdata->phy_interface == -1) {
1330 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1331 return -EINVAL;
1332 }
1333
1334 /* TODO
1335 * Need to get the reset-gpio and related properties from DT
1336 * and implemet the enet reset code on .probe call
1337 */
1338
1339 return 0;
1340 }
1341
1342 static const struct udevice_id fecmxc_ids[] = {
1343 { .compatible = "fsl,imx6q-fec" },
1344 { .compatible = "fsl,imx6sl-fec" },
1345 { .compatible = "fsl,imx6sx-fec" },
1346 { .compatible = "fsl,imx6ul-fec" },
1347 { .compatible = "fsl,imx53-fec" },
1348 { }
1349 };
1350
1351 U_BOOT_DRIVER(fecmxc_gem) = {
1352 .name = "fecmxc",
1353 .id = UCLASS_ETH,
1354 .of_match = fecmxc_ids,
1355 .ofdata_to_platdata = fecmxc_ofdata_to_platdata,
1356 .probe = fecmxc_probe,
1357 .remove = fecmxc_remove,
1358 .ops = &fecmxc_ops,
1359 .priv_auto_alloc_size = sizeof(struct fec_priv),
1360 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1361 };
1362 #endif
1363