/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/ |
D | fneg.s | 10 fneg z31.h, p7/m, z31.h label 16 fneg z31.s, p7/m, z31.s label 22 fneg z31.d, p7/m, z31.d label 38 fneg z4.d, p7/m, z31.d label 50 fneg z4.d, p7/m, z31.d label
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D | fneg-diagnostics.s | 6 fneg z31.h, p8/m, z31.h label 15 fneg z31.b, p7/m, z31.b label 20 fneg z31.h, p7/m, z31.s label
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/external/compiler-rt/lib/builtins/ |
D | negsf2.c | 17 ARM_EABI_FNALIAS(fneg, negsf2) in ARM_EABI_FNALIAS() argument
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
D | basic-a64-instructions.s | 1839 fneg d4, d5 define
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D | arm64-fp-encoding.s | 108 fneg d1, d2 define
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/external/llvm/test/MC/AArch64/ |
D | basic-a64-instructions.s | 1856 fneg d4, d5 define
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D | arm64-fp-encoding.s | 108 fneg d1, d2 define
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/external/vixl/test/aarch64/ |
D | test-trace-aarch64.cc | 544 __ fneg(d15, d0); in GenerateTestSequenceFP() local 545 __ fneg(s14, s15); in GenerateTestSequenceFP() local 2684 __ fneg(v1.V2D(), v25.V2D()); in GenerateTestSequenceNEONFP() local 2685 __ fneg(v14.V2S(), v31.V2S()); in GenerateTestSequenceNEONFP() local 2686 __ fneg(v5.V4S(), v4.V4S()); in GenerateTestSequenceNEONFP() local
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D | test-assembler-aarch64.cc | 12403 TEST(fneg) { in TEST() argument
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/external/v8/src/ppc/ |
D | assembler-ppc.cc | 1889 void Assembler::fneg(const DoubleRegister frt, const DoubleRegister frb, in fneg() function in v8::internal::Assembler
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/external/v8/src/arm64/ |
D | simulator-logic-arm64.cc | 3492 LogicVRegister Simulator::fneg(VectorFormat vform, LogicVRegister dst, in fneg() function in v8::internal::Simulator 3503 LogicVRegister Simulator::fneg(VectorFormat vform, LogicVRegister dst, in fneg() function in v8::internal::Simulator
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/external/vixl/src/aarch64/ |
D | logic-aarch64.cc | 4430 LogicVRegister Simulator::fneg(VectorFormat vform, in fneg() function in vixl::aarch64::Simulator 4443 LogicVRegister Simulator::fneg(VectorFormat vform, in fneg() function in vixl::aarch64::Simulator
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