1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010
4 * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com.
5 *
6 * (C) Copyright 2012
7 * Amit Virdi, ST Microelectronics, amit.virdi@st.com.
8 */
9
10 #include <common.h>
11 #include <nand.h>
12 #include <asm/io.h>
13 #include <linux/bitops.h>
14 #include <linux/err.h>
15 #include <linux/mtd/nand_ecc.h>
16 #include <linux/mtd/fsmc_nand.h>
17 #include <asm/arch/hardware.h>
18
19 static u32 fsmc_version;
20 static struct fsmc_regs *const fsmc_regs_p = (struct fsmc_regs *)
21 CONFIG_SYS_FSMC_BASE;
22
23 /*
24 * ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of
25 * data. ECC4 can correct up to 8 bits in 512 bytes of data while ECC1 can
26 * correct 1 bit in 512 bytes
27 */
28
29 static struct nand_ecclayout fsmc_ecc4_lp_layout = {
30 .eccbytes = 104,
31 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
32 9, 10, 11, 12, 13, 14,
33 18, 19, 20, 21, 22, 23, 24,
34 25, 26, 27, 28, 29, 30,
35 34, 35, 36, 37, 38, 39, 40,
36 41, 42, 43, 44, 45, 46,
37 50, 51, 52, 53, 54, 55, 56,
38 57, 58, 59, 60, 61, 62,
39 66, 67, 68, 69, 70, 71, 72,
40 73, 74, 75, 76, 77, 78,
41 82, 83, 84, 85, 86, 87, 88,
42 89, 90, 91, 92, 93, 94,
43 98, 99, 100, 101, 102, 103, 104,
44 105, 106, 107, 108, 109, 110,
45 114, 115, 116, 117, 118, 119, 120,
46 121, 122, 123, 124, 125, 126
47 },
48 .oobfree = {
49 {.offset = 15, .length = 3},
50 {.offset = 31, .length = 3},
51 {.offset = 47, .length = 3},
52 {.offset = 63, .length = 3},
53 {.offset = 79, .length = 3},
54 {.offset = 95, .length = 3},
55 {.offset = 111, .length = 3},
56 {.offset = 127, .length = 1}
57 }
58 };
59
60 /*
61 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
62 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
63 * bytes are free for use.
64 */
65 static struct nand_ecclayout fsmc_ecc4_224_layout = {
66 .eccbytes = 104,
67 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
68 9, 10, 11, 12, 13, 14,
69 18, 19, 20, 21, 22, 23, 24,
70 25, 26, 27, 28, 29, 30,
71 34, 35, 36, 37, 38, 39, 40,
72 41, 42, 43, 44, 45, 46,
73 50, 51, 52, 53, 54, 55, 56,
74 57, 58, 59, 60, 61, 62,
75 66, 67, 68, 69, 70, 71, 72,
76 73, 74, 75, 76, 77, 78,
77 82, 83, 84, 85, 86, 87, 88,
78 89, 90, 91, 92, 93, 94,
79 98, 99, 100, 101, 102, 103, 104,
80 105, 106, 107, 108, 109, 110,
81 114, 115, 116, 117, 118, 119, 120,
82 121, 122, 123, 124, 125, 126
83 },
84 .oobfree = {
85 {.offset = 15, .length = 3},
86 {.offset = 31, .length = 3},
87 {.offset = 47, .length = 3},
88 {.offset = 63, .length = 3},
89 {.offset = 79, .length = 3},
90 {.offset = 95, .length = 3},
91 {.offset = 111, .length = 3},
92 {.offset = 127, .length = 97}
93 }
94 };
95
96 /*
97 * ECC placement definitions in oobfree type format
98 * There are 13 bytes of ecc for every 512 byte block and it has to be read
99 * consecutively and immediately after the 512 byte data block for hardware to
100 * generate the error bit offsets in 512 byte data
101 * Managing the ecc bytes in the following way makes it easier for software to
102 * read ecc bytes consecutive to data bytes. This way is similar to
103 * oobfree structure maintained already in u-boot nand driver
104 */
105 static struct fsmc_eccplace fsmc_eccpl_lp = {
106 .eccplace = {
107 {.offset = 2, .length = 13},
108 {.offset = 18, .length = 13},
109 {.offset = 34, .length = 13},
110 {.offset = 50, .length = 13},
111 {.offset = 66, .length = 13},
112 {.offset = 82, .length = 13},
113 {.offset = 98, .length = 13},
114 {.offset = 114, .length = 13}
115 }
116 };
117
118 static struct nand_ecclayout fsmc_ecc4_sp_layout = {
119 .eccbytes = 13,
120 .eccpos = { 0, 1, 2, 3, 6, 7, 8,
121 9, 10, 11, 12, 13, 14
122 },
123 .oobfree = {
124 {.offset = 15, .length = 1},
125 }
126 };
127
128 static struct fsmc_eccplace fsmc_eccpl_sp = {
129 .eccplace = {
130 {.offset = 0, .length = 4},
131 {.offset = 6, .length = 9}
132 }
133 };
134
135 static struct nand_ecclayout fsmc_ecc1_layout = {
136 .eccbytes = 24,
137 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
138 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
139 .oobfree = {
140 {.offset = 8, .length = 8},
141 {.offset = 24, .length = 8},
142 {.offset = 40, .length = 8},
143 {.offset = 56, .length = 8},
144 {.offset = 72, .length = 8},
145 {.offset = 88, .length = 8},
146 {.offset = 104, .length = 8},
147 {.offset = 120, .length = 8}
148 }
149 };
150
151 /* Count the number of 0's in buff upto a max of max_bits */
count_written_bits(uint8_t * buff,int size,int max_bits)152 static int count_written_bits(uint8_t *buff, int size, int max_bits)
153 {
154 int k, written_bits = 0;
155
156 for (k = 0; k < size; k++) {
157 written_bits += hweight8(~buff[k]);
158 if (written_bits > max_bits)
159 break;
160 }
161
162 return written_bits;
163 }
164
fsmc_nand_hwcontrol(struct mtd_info * mtd,int cmd,uint ctrl)165 static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
166 {
167 struct nand_chip *this = mtd_to_nand(mtd);
168 ulong IO_ADDR_W;
169
170 if (ctrl & NAND_CTRL_CHANGE) {
171 IO_ADDR_W = (ulong)this->IO_ADDR_W;
172
173 IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE);
174 if (ctrl & NAND_CLE)
175 IO_ADDR_W |= CONFIG_SYS_NAND_CLE;
176 if (ctrl & NAND_ALE)
177 IO_ADDR_W |= CONFIG_SYS_NAND_ALE;
178
179 if (ctrl & NAND_NCE) {
180 writel(readl(&fsmc_regs_p->pc) |
181 FSMC_ENABLE, &fsmc_regs_p->pc);
182 } else {
183 writel(readl(&fsmc_regs_p->pc) &
184 ~FSMC_ENABLE, &fsmc_regs_p->pc);
185 }
186 this->IO_ADDR_W = (void *)IO_ADDR_W;
187 }
188
189 if (cmd != NAND_CMD_NONE)
190 writeb(cmd, this->IO_ADDR_W);
191 }
192
fsmc_bch8_correct_data(struct mtd_info * mtd,u_char * dat,u_char * read_ecc,u_char * calc_ecc)193 static int fsmc_bch8_correct_data(struct mtd_info *mtd, u_char *dat,
194 u_char *read_ecc, u_char *calc_ecc)
195 {
196 /* The calculated ecc is actually the correction index in data */
197 u32 err_idx[8];
198 u32 num_err, i;
199 u32 ecc1, ecc2, ecc3, ecc4;
200
201 num_err = (readl(&fsmc_regs_p->sts) >> 10) & 0xF;
202
203 if (likely(num_err == 0))
204 return 0;
205
206 if (unlikely(num_err > 8)) {
207 /*
208 * This is a temporary erase check. A newly erased page read
209 * would result in an ecc error because the oob data is also
210 * erased to FF and the calculated ecc for an FF data is not
211 * FF..FF.
212 * This is a workaround to skip performing correction in case
213 * data is FF..FF
214 *
215 * Logic:
216 * For every page, each bit written as 0 is counted until these
217 * number of bits are greater than 8 (the maximum correction
218 * capability of FSMC for each 512 + 13 bytes)
219 */
220
221 int bits_ecc = count_written_bits(read_ecc, 13, 8);
222 int bits_data = count_written_bits(dat, 512, 8);
223
224 if ((bits_ecc + bits_data) <= 8) {
225 if (bits_data)
226 memset(dat, 0xff, 512);
227 return bits_data + bits_ecc;
228 }
229
230 return -EBADMSG;
231 }
232
233 ecc1 = readl(&fsmc_regs_p->ecc1);
234 ecc2 = readl(&fsmc_regs_p->ecc2);
235 ecc3 = readl(&fsmc_regs_p->ecc3);
236 ecc4 = readl(&fsmc_regs_p->sts);
237
238 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
239 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
240 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
241 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
242 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
243 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
244 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
245 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
246
247 i = 0;
248 while (i < num_err) {
249 err_idx[i] ^= 3;
250
251 if (err_idx[i] < 512 * 8)
252 __change_bit(err_idx[i], dat);
253
254 i++;
255 }
256
257 return num_err;
258 }
259
fsmc_read_hwecc(struct mtd_info * mtd,const u_char * data,u_char * ecc)260 static int fsmc_read_hwecc(struct mtd_info *mtd,
261 const u_char *data, u_char *ecc)
262 {
263 u_int ecc_tmp;
264 int timeout = CONFIG_SYS_HZ;
265 ulong start;
266
267 switch (fsmc_version) {
268 case FSMC_VER8:
269 start = get_timer(0);
270 while (get_timer(start) < timeout) {
271 /*
272 * Busy waiting for ecc computation
273 * to finish for 512 bytes
274 */
275 if (readl(&fsmc_regs_p->sts) & FSMC_CODE_RDY)
276 break;
277 }
278
279 ecc_tmp = readl(&fsmc_regs_p->ecc1);
280 ecc[0] = (u_char) (ecc_tmp >> 0);
281 ecc[1] = (u_char) (ecc_tmp >> 8);
282 ecc[2] = (u_char) (ecc_tmp >> 16);
283 ecc[3] = (u_char) (ecc_tmp >> 24);
284
285 ecc_tmp = readl(&fsmc_regs_p->ecc2);
286 ecc[4] = (u_char) (ecc_tmp >> 0);
287 ecc[5] = (u_char) (ecc_tmp >> 8);
288 ecc[6] = (u_char) (ecc_tmp >> 16);
289 ecc[7] = (u_char) (ecc_tmp >> 24);
290
291 ecc_tmp = readl(&fsmc_regs_p->ecc3);
292 ecc[8] = (u_char) (ecc_tmp >> 0);
293 ecc[9] = (u_char) (ecc_tmp >> 8);
294 ecc[10] = (u_char) (ecc_tmp >> 16);
295 ecc[11] = (u_char) (ecc_tmp >> 24);
296
297 ecc_tmp = readl(&fsmc_regs_p->sts);
298 ecc[12] = (u_char) (ecc_tmp >> 16);
299 break;
300
301 default:
302 ecc_tmp = readl(&fsmc_regs_p->ecc1);
303 ecc[0] = (u_char) (ecc_tmp >> 0);
304 ecc[1] = (u_char) (ecc_tmp >> 8);
305 ecc[2] = (u_char) (ecc_tmp >> 16);
306 break;
307 }
308
309 return 0;
310 }
311
fsmc_enable_hwecc(struct mtd_info * mtd,int mode)312 void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
313 {
314 writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCPLEN_256,
315 &fsmc_regs_p->pc);
316 writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCEN,
317 &fsmc_regs_p->pc);
318 writel(readl(&fsmc_regs_p->pc) | FSMC_ECCEN,
319 &fsmc_regs_p->pc);
320 }
321
322 /*
323 * fsmc_read_page_hwecc
324 * @mtd: mtd info structure
325 * @chip: nand chip info structure
326 * @buf: buffer to store read data
327 * @oob_required: caller expects OOB data read to chip->oob_poi
328 * @page: page number to read
329 *
330 * This routine is needed for fsmc verison 8 as reading from NAND chip has to be
331 * performed in a strict sequence as follows:
332 * data(512 byte) -> ecc(13 byte)
333 * After this read, fsmc hardware generates and reports error data bits(upto a
334 * max of 8 bits)
335 */
fsmc_read_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)336 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
337 uint8_t *buf, int oob_required, int page)
338 {
339 struct fsmc_eccplace *fsmc_eccpl;
340 int i, j, s, stat, eccsize = chip->ecc.size;
341 int eccbytes = chip->ecc.bytes;
342 int eccsteps = chip->ecc.steps;
343 uint8_t *p = buf;
344 uint8_t *ecc_calc = chip->buffers->ecccalc;
345 uint8_t *ecc_code = chip->buffers->ecccode;
346 int off, len, group = 0;
347 uint8_t oob[13] __attribute__ ((aligned (2)));
348
349 /* Differentiate between small and large page ecc place definitions */
350 if (mtd->writesize == 512)
351 fsmc_eccpl = &fsmc_eccpl_sp;
352 else
353 fsmc_eccpl = &fsmc_eccpl_lp;
354
355 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
356
357 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
358 chip->ecc.hwctl(mtd, NAND_ECC_READ);
359 chip->read_buf(mtd, p, eccsize);
360
361 for (j = 0; j < eccbytes;) {
362 off = fsmc_eccpl->eccplace[group].offset;
363 len = fsmc_eccpl->eccplace[group].length;
364 group++;
365
366 /*
367 * length is intentionally kept a higher multiple of 2
368 * to read at least 13 bytes even in case of 16 bit NAND
369 * devices
370 */
371 if (chip->options & NAND_BUSWIDTH_16)
372 len = roundup(len, 2);
373 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
374 chip->read_buf(mtd, oob + j, len);
375 j += len;
376 }
377
378 memcpy(&ecc_code[i], oob, 13);
379 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
380
381 stat = chip->ecc.correct(mtd, p, &ecc_code[i],
382 &ecc_calc[i]);
383 if (stat < 0)
384 mtd->ecc_stats.failed++;
385 else
386 mtd->ecc_stats.corrected += stat;
387 }
388
389 return 0;
390 }
391
392 #ifndef CONFIG_SPL_BUILD
393 /*
394 * fsmc_nand_switch_ecc - switch the ECC operation between different engines
395 *
396 * @eccstrength - the number of bits that could be corrected
397 * (1 - HW, 4 - SW BCH4)
398 */
fsmc_nand_switch_ecc(uint32_t eccstrength)399 int fsmc_nand_switch_ecc(uint32_t eccstrength)
400 {
401 struct nand_chip *nand;
402 struct mtd_info *mtd;
403 int err;
404
405 /*
406 * This functions is only called on SPEAr600 platforms, supporting
407 * 1 bit HW ECC. The BCH8 HW ECC (FSMC_VER8) from the ST-Ericsson
408 * Nomadik SoC is currently supporting this fsmc_nand_switch_ecc()
409 * function, as it doesn't need to switch to a different ECC layout.
410 */
411 mtd = get_nand_dev_by_index(nand_curr_device);
412 nand = mtd_to_nand(mtd);
413
414 /* Setup the ecc configurations again */
415 if (eccstrength == 1) {
416 nand->ecc.mode = NAND_ECC_HW;
417 nand->ecc.bytes = 3;
418 nand->ecc.strength = 1;
419 nand->ecc.layout = &fsmc_ecc1_layout;
420 nand->ecc.calculate = fsmc_read_hwecc;
421 nand->ecc.correct = nand_correct_data;
422 } else if (eccstrength == 4) {
423 /*
424 * .calculate .correct and .bytes will be set in
425 * nand_scan_tail()
426 */
427 nand->ecc.mode = NAND_ECC_SOFT_BCH;
428 nand->ecc.strength = 4;
429 nand->ecc.layout = NULL;
430 } else {
431 printf("Error: ECC strength %d not supported!\n", eccstrength);
432 }
433
434 /* Update NAND handling after ECC mode switch */
435 err = nand_scan_tail(mtd);
436
437 return err;
438 }
439 #endif /* CONFIG_SPL_BUILD */
440
fsmc_nand_init(struct nand_chip * nand)441 int fsmc_nand_init(struct nand_chip *nand)
442 {
443 static int chip_nr;
444 struct mtd_info *mtd;
445 u32 peripid2 = readl(&fsmc_regs_p->peripid2);
446
447 fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) &
448 FSMC_REVISION_MSK;
449
450 writel(readl(&fsmc_regs_p->ctrl) | FSMC_WP, &fsmc_regs_p->ctrl);
451
452 #if defined(CONFIG_SYS_FSMC_NAND_16BIT)
453 writel(FSMC_DEVWID_16 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,
454 &fsmc_regs_p->pc);
455 #elif defined(CONFIG_SYS_FSMC_NAND_8BIT)
456 writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,
457 &fsmc_regs_p->pc);
458 #else
459 #error Please define CONFIG_SYS_FSMC_NAND_16BIT or CONFIG_SYS_FSMC_NAND_8BIT
460 #endif
461 writel(readl(&fsmc_regs_p->pc) | FSMC_TCLR_1 | FSMC_TAR_1,
462 &fsmc_regs_p->pc);
463 writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
464 &fsmc_regs_p->comm);
465 writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
466 &fsmc_regs_p->attrib);
467
468 nand->options = 0;
469 #if defined(CONFIG_SYS_FSMC_NAND_16BIT)
470 nand->options |= NAND_BUSWIDTH_16;
471 #endif
472 nand->ecc.mode = NAND_ECC_HW;
473 nand->ecc.size = 512;
474 nand->ecc.calculate = fsmc_read_hwecc;
475 nand->ecc.hwctl = fsmc_enable_hwecc;
476 nand->cmd_ctrl = fsmc_nand_hwcontrol;
477 nand->IO_ADDR_R = nand->IO_ADDR_W =
478 (void __iomem *)CONFIG_SYS_NAND_BASE;
479 nand->badblockbits = 7;
480
481 mtd = nand_to_mtd(nand);
482
483 switch (fsmc_version) {
484 case FSMC_VER8:
485 nand->ecc.bytes = 13;
486 nand->ecc.strength = 8;
487 nand->ecc.correct = fsmc_bch8_correct_data;
488 nand->ecc.read_page = fsmc_read_page_hwecc;
489 if (mtd->writesize == 512)
490 nand->ecc.layout = &fsmc_ecc4_sp_layout;
491 else {
492 if (mtd->oobsize == 224)
493 nand->ecc.layout = &fsmc_ecc4_224_layout;
494 else
495 nand->ecc.layout = &fsmc_ecc4_lp_layout;
496 }
497
498 break;
499 default:
500 nand->ecc.bytes = 3;
501 nand->ecc.strength = 1;
502 nand->ecc.layout = &fsmc_ecc1_layout;
503 nand->ecc.correct = nand_correct_data;
504 break;
505 }
506
507 /* Detect NAND chips */
508 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL))
509 return -ENXIO;
510
511 if (nand_scan_tail(mtd))
512 return -ENXIO;
513
514 if (nand_register(chip_nr++, mtd))
515 return -ENXIO;
516
517 return 0;
518 }
519