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1 //===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines structures to encapsulate information gleaned from the
11 // target register and register class definitions.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "CodeGenRegisters.h"
16 #include "CodeGenTarget.h"
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/IntEqClasses.h"
21 #include "llvm/ADT/SetVector.h"
22 #include "llvm/ADT/SmallPtrSet.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Twine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/TableGen/Error.h"
32 #include "llvm/TableGen/Record.h"
33 #include <algorithm>
34 #include <cassert>
35 #include <cstdint>
36 #include <iterator>
37 #include <map>
38 #include <queue>
39 #include <set>
40 #include <string>
41 #include <tuple>
42 #include <utility>
43 #include <vector>
44 
45 using namespace llvm;
46 
47 #define DEBUG_TYPE "regalloc-emitter"
48 
49 //===----------------------------------------------------------------------===//
50 //                             CodeGenSubRegIndex
51 //===----------------------------------------------------------------------===//
52 
CodeGenSubRegIndex(Record * R,unsigned Enum)53 CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum)
54   : TheDef(R), EnumValue(Enum), AllSuperRegsCovered(true), Artificial(true) {
55   Name = R->getName();
56   if (R->getValue("Namespace"))
57     Namespace = R->getValueAsString("Namespace");
58   Size = R->getValueAsInt("Size");
59   Offset = R->getValueAsInt("Offset");
60 }
61 
CodeGenSubRegIndex(StringRef N,StringRef Nspace,unsigned Enum)62 CodeGenSubRegIndex::CodeGenSubRegIndex(StringRef N, StringRef Nspace,
63                                        unsigned Enum)
64   : TheDef(nullptr), Name(N), Namespace(Nspace), Size(-1), Offset(-1),
65     EnumValue(Enum), AllSuperRegsCovered(true), Artificial(true) {
66 }
67 
getQualifiedName() const68 std::string CodeGenSubRegIndex::getQualifiedName() const {
69   std::string N = getNamespace();
70   if (!N.empty())
71     N += "::";
72   N += getName();
73   return N;
74 }
75 
updateComponents(CodeGenRegBank & RegBank)76 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
77   if (!TheDef)
78     return;
79 
80   std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf");
81   if (!Comps.empty()) {
82     if (Comps.size() != 2)
83       PrintFatalError(TheDef->getLoc(),
84                       "ComposedOf must have exactly two entries");
85     CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]);
86     CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]);
87     CodeGenSubRegIndex *X = A->addComposite(B, this);
88     if (X)
89       PrintFatalError(TheDef->getLoc(), "Ambiguous ComposedOf entries");
90   }
91 
92   std::vector<Record*> Parts =
93     TheDef->getValueAsListOfDefs("CoveringSubRegIndices");
94   if (!Parts.empty()) {
95     if (Parts.size() < 2)
96       PrintFatalError(TheDef->getLoc(),
97                       "CoveredBySubRegs must have two or more entries");
98     SmallVector<CodeGenSubRegIndex*, 8> IdxParts;
99     for (Record *Part : Parts)
100       IdxParts.push_back(RegBank.getSubRegIdx(Part));
101     setConcatenationOf(IdxParts);
102   }
103 }
104 
computeLaneMask() const105 LaneBitmask CodeGenSubRegIndex::computeLaneMask() const {
106   // Already computed?
107   if (LaneMask.any())
108     return LaneMask;
109 
110   // Recursion guard, shouldn't be required.
111   LaneMask = LaneBitmask::getAll();
112 
113   // The lane mask is simply the union of all sub-indices.
114   LaneBitmask M;
115   for (const auto &C : Composed)
116     M |= C.second->computeLaneMask();
117   assert(M.any() && "Missing lane mask, sub-register cycle?");
118   LaneMask = M;
119   return LaneMask;
120 }
121 
setConcatenationOf(ArrayRef<CodeGenSubRegIndex * > Parts)122 void CodeGenSubRegIndex::setConcatenationOf(
123     ArrayRef<CodeGenSubRegIndex*> Parts) {
124   if (ConcatenationOf.empty())
125     ConcatenationOf.assign(Parts.begin(), Parts.end());
126   else
127     assert(std::equal(Parts.begin(), Parts.end(),
128                       ConcatenationOf.begin()) && "parts consistent");
129 }
130 
computeConcatTransitiveClosure()131 void CodeGenSubRegIndex::computeConcatTransitiveClosure() {
132   for (SmallVectorImpl<CodeGenSubRegIndex*>::iterator
133        I = ConcatenationOf.begin(); I != ConcatenationOf.end(); /*empty*/) {
134     CodeGenSubRegIndex *SubIdx = *I;
135     SubIdx->computeConcatTransitiveClosure();
136 #ifndef NDEBUG
137     for (CodeGenSubRegIndex *SRI : SubIdx->ConcatenationOf)
138       assert(SRI->ConcatenationOf.empty() && "No transitive closure?");
139 #endif
140 
141     if (SubIdx->ConcatenationOf.empty()) {
142       ++I;
143     } else {
144       I = ConcatenationOf.erase(I);
145       I = ConcatenationOf.insert(I, SubIdx->ConcatenationOf.begin(),
146                                  SubIdx->ConcatenationOf.end());
147       I += SubIdx->ConcatenationOf.size();
148     }
149   }
150 }
151 
152 //===----------------------------------------------------------------------===//
153 //                              CodeGenRegister
154 //===----------------------------------------------------------------------===//
155 
CodeGenRegister(Record * R,unsigned Enum)156 CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
157   : TheDef(R),
158     EnumValue(Enum),
159     CostPerUse(R->getValueAsInt("CostPerUse")),
160     CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")),
161     HasDisjunctSubRegs(false),
162     SubRegsComplete(false),
163     SuperRegsComplete(false),
164     TopoSig(~0u) {
165   Artificial = R->getValueAsBit("isArtificial");
166 }
167 
buildObjectGraph(CodeGenRegBank & RegBank)168 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
169   std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices");
170   std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
171 
172   if (SRIs.size() != SRs.size())
173     PrintFatalError(TheDef->getLoc(),
174                     "SubRegs and SubRegIndices must have the same size");
175 
176   for (unsigned i = 0, e = SRIs.size(); i != e; ++i) {
177     ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i]));
178     ExplicitSubRegs.push_back(RegBank.getReg(SRs[i]));
179   }
180 
181   // Also compute leading super-registers. Each register has a list of
182   // covered-by-subregs super-registers where it appears as the first explicit
183   // sub-register.
184   //
185   // This is used by computeSecondarySubRegs() to find candidates.
186   if (CoveredBySubRegs && !ExplicitSubRegs.empty())
187     ExplicitSubRegs.front()->LeadingSuperRegs.push_back(this);
188 
189   // Add ad hoc alias links. This is a symmetric relationship between two
190   // registers, so build a symmetric graph by adding links in both ends.
191   std::vector<Record*> Aliases = TheDef->getValueAsListOfDefs("Aliases");
192   for (Record *Alias : Aliases) {
193     CodeGenRegister *Reg = RegBank.getReg(Alias);
194     ExplicitAliases.push_back(Reg);
195     Reg->ExplicitAliases.push_back(this);
196   }
197 }
198 
getName() const199 const StringRef CodeGenRegister::getName() const {
200   assert(TheDef && "no def");
201   return TheDef->getName();
202 }
203 
204 namespace {
205 
206 // Iterate over all register units in a set of registers.
207 class RegUnitIterator {
208   CodeGenRegister::Vec::const_iterator RegI, RegE;
209   CodeGenRegister::RegUnitList::iterator UnitI, UnitE;
210 
211 public:
RegUnitIterator(const CodeGenRegister::Vec & Regs)212   RegUnitIterator(const CodeGenRegister::Vec &Regs):
213     RegI(Regs.begin()), RegE(Regs.end()) {
214 
215     if (RegI != RegE) {
216       UnitI = (*RegI)->getRegUnits().begin();
217       UnitE = (*RegI)->getRegUnits().end();
218       advance();
219     }
220   }
221 
isValid() const222   bool isValid() const { return UnitI != UnitE; }
223 
operator *() const224   unsigned operator* () const { assert(isValid()); return *UnitI; }
225 
getReg() const226   const CodeGenRegister *getReg() const { assert(isValid()); return *RegI; }
227 
228   /// Preincrement.  Move to the next unit.
operator ++()229   void operator++() {
230     assert(isValid() && "Cannot advance beyond the last operand");
231     ++UnitI;
232     advance();
233   }
234 
235 protected:
advance()236   void advance() {
237     while (UnitI == UnitE) {
238       if (++RegI == RegE)
239         break;
240       UnitI = (*RegI)->getRegUnits().begin();
241       UnitE = (*RegI)->getRegUnits().end();
242     }
243   }
244 };
245 
246 } // end anonymous namespace
247 
248 // Return true of this unit appears in RegUnits.
hasRegUnit(CodeGenRegister::RegUnitList & RegUnits,unsigned Unit)249 static bool hasRegUnit(CodeGenRegister::RegUnitList &RegUnits, unsigned Unit) {
250   return RegUnits.test(Unit);
251 }
252 
253 // Inherit register units from subregisters.
254 // Return true if the RegUnits changed.
inheritRegUnits(CodeGenRegBank & RegBank)255 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) {
256   bool changed = false;
257   for (const auto &SubReg : SubRegs) {
258     CodeGenRegister *SR = SubReg.second;
259     // Merge the subregister's units into this register's RegUnits.
260     changed |= (RegUnits |= SR->RegUnits);
261   }
262 
263   return changed;
264 }
265 
266 const CodeGenRegister::SubRegMap &
computeSubRegs(CodeGenRegBank & RegBank)267 CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
268   // Only compute this map once.
269   if (SubRegsComplete)
270     return SubRegs;
271   SubRegsComplete = true;
272 
273   HasDisjunctSubRegs = ExplicitSubRegs.size() > 1;
274 
275   // First insert the explicit subregs and make sure they are fully indexed.
276   for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
277     CodeGenRegister *SR = ExplicitSubRegs[i];
278     CodeGenSubRegIndex *Idx = ExplicitSubRegIndices[i];
279     if (!SR->Artificial)
280       Idx->Artificial = false;
281     if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
282       PrintFatalError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() +
283                       " appears twice in Register " + getName());
284     // Map explicit sub-registers first, so the names take precedence.
285     // The inherited sub-registers are mapped below.
286     SubReg2Idx.insert(std::make_pair(SR, Idx));
287   }
288 
289   // Keep track of inherited subregs and how they can be reached.
290   SmallPtrSet<CodeGenRegister*, 8> Orphans;
291 
292   // Clone inherited subregs and place duplicate entries in Orphans.
293   // Here the order is important - earlier subregs take precedence.
294   for (CodeGenRegister *ESR : ExplicitSubRegs) {
295     const SubRegMap &Map = ESR->computeSubRegs(RegBank);
296     HasDisjunctSubRegs |= ESR->HasDisjunctSubRegs;
297 
298     for (const auto &SR : Map) {
299       if (!SubRegs.insert(SR).second)
300         Orphans.insert(SR.second);
301     }
302   }
303 
304   // Expand any composed subreg indices.
305   // If dsub_2 has ComposedOf = [qsub_1, dsub_0], and this register has a
306   // qsub_1 subreg, add a dsub_2 subreg.  Keep growing Indices and process
307   // expanded subreg indices recursively.
308   SmallVector<CodeGenSubRegIndex*, 8> Indices = ExplicitSubRegIndices;
309   for (unsigned i = 0; i != Indices.size(); ++i) {
310     CodeGenSubRegIndex *Idx = Indices[i];
311     const CodeGenSubRegIndex::CompMap &Comps = Idx->getComposites();
312     CodeGenRegister *SR = SubRegs[Idx];
313     const SubRegMap &Map = SR->computeSubRegs(RegBank);
314 
315     // Look at the possible compositions of Idx.
316     // They may not all be supported by SR.
317     for (CodeGenSubRegIndex::CompMap::const_iterator I = Comps.begin(),
318            E = Comps.end(); I != E; ++I) {
319       SubRegMap::const_iterator SRI = Map.find(I->first);
320       if (SRI == Map.end())
321         continue; // Idx + I->first doesn't exist in SR.
322       // Add I->second as a name for the subreg SRI->second, assuming it is
323       // orphaned, and the name isn't already used for something else.
324       if (SubRegs.count(I->second) || !Orphans.erase(SRI->second))
325         continue;
326       // We found a new name for the orphaned sub-register.
327       SubRegs.insert(std::make_pair(I->second, SRI->second));
328       Indices.push_back(I->second);
329     }
330   }
331 
332   // Now Orphans contains the inherited subregisters without a direct index.
333   // Create inferred indexes for all missing entries.
334   // Work backwards in the Indices vector in order to compose subregs bottom-up.
335   // Consider this subreg sequence:
336   //
337   //   qsub_1 -> dsub_0 -> ssub_0
338   //
339   // The qsub_1 -> dsub_0 composition becomes dsub_2, so the ssub_0 register
340   // can be reached in two different ways:
341   //
342   //   qsub_1 -> ssub_0
343   //   dsub_2 -> ssub_0
344   //
345   // We pick the latter composition because another register may have [dsub_0,
346   // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg.  The
347   // dsub_2 -> ssub_0 composition can be shared.
348   while (!Indices.empty() && !Orphans.empty()) {
349     CodeGenSubRegIndex *Idx = Indices.pop_back_val();
350     CodeGenRegister *SR = SubRegs[Idx];
351     const SubRegMap &Map = SR->computeSubRegs(RegBank);
352     for (const auto &SubReg : Map)
353       if (Orphans.erase(SubReg.second))
354         SubRegs[RegBank.getCompositeSubRegIndex(Idx, SubReg.first)] = SubReg.second;
355   }
356 
357   // Compute the inverse SubReg -> Idx map.
358   for (const auto &SubReg : SubRegs) {
359     if (SubReg.second == this) {
360       ArrayRef<SMLoc> Loc;
361       if (TheDef)
362         Loc = TheDef->getLoc();
363       PrintFatalError(Loc, "Register " + getName() +
364                       " has itself as a sub-register");
365     }
366 
367     // Compute AllSuperRegsCovered.
368     if (!CoveredBySubRegs)
369       SubReg.first->AllSuperRegsCovered = false;
370 
371     // Ensure that every sub-register has a unique name.
372     DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins =
373       SubReg2Idx.insert(std::make_pair(SubReg.second, SubReg.first)).first;
374     if (Ins->second == SubReg.first)
375       continue;
376     // Trouble: Two different names for SubReg.second.
377     ArrayRef<SMLoc> Loc;
378     if (TheDef)
379       Loc = TheDef->getLoc();
380     PrintFatalError(Loc, "Sub-register can't have two names: " +
381                   SubReg.second->getName() + " available as " +
382                   SubReg.first->getName() + " and " + Ins->second->getName());
383   }
384 
385   // Derive possible names for sub-register concatenations from any explicit
386   // sub-registers. By doing this before computeSecondarySubRegs(), we ensure
387   // that getConcatSubRegIndex() won't invent any concatenated indices that the
388   // user already specified.
389   for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
390     CodeGenRegister *SR = ExplicitSubRegs[i];
391     if (!SR->CoveredBySubRegs || SR->ExplicitSubRegs.size() <= 1 ||
392         SR->Artificial)
393       continue;
394 
395     // SR is composed of multiple sub-regs. Find their names in this register.
396     SmallVector<CodeGenSubRegIndex*, 8> Parts;
397     for (unsigned j = 0, e = SR->ExplicitSubRegs.size(); j != e; ++j) {
398       CodeGenSubRegIndex &I = *SR->ExplicitSubRegIndices[j];
399       if (!I.Artificial)
400         Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j]));
401     }
402 
403     // Offer this as an existing spelling for the concatenation of Parts.
404     CodeGenSubRegIndex &Idx = *ExplicitSubRegIndices[i];
405     Idx.setConcatenationOf(Parts);
406   }
407 
408   // Initialize RegUnitList. Because getSubRegs is called recursively, this
409   // processes the register hierarchy in postorder.
410   //
411   // Inherit all sub-register units. It is good enough to look at the explicit
412   // sub-registers, the other registers won't contribute any more units.
413   for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
414     CodeGenRegister *SR = ExplicitSubRegs[i];
415     RegUnits |= SR->RegUnits;
416   }
417 
418   // Absent any ad hoc aliasing, we create one register unit per leaf register.
419   // These units correspond to the maximal cliques in the register overlap
420   // graph which is optimal.
421   //
422   // When there is ad hoc aliasing, we simply create one unit per edge in the
423   // undirected ad hoc aliasing graph. Technically, we could do better by
424   // identifying maximal cliques in the ad hoc graph, but cliques larger than 2
425   // are extremely rare anyway (I've never seen one), so we don't bother with
426   // the added complexity.
427   for (unsigned i = 0, e = ExplicitAliases.size(); i != e; ++i) {
428     CodeGenRegister *AR = ExplicitAliases[i];
429     // Only visit each edge once.
430     if (AR->SubRegsComplete)
431       continue;
432     // Create a RegUnit representing this alias edge, and add it to both
433     // registers.
434     unsigned Unit = RegBank.newRegUnit(this, AR);
435     RegUnits.set(Unit);
436     AR->RegUnits.set(Unit);
437   }
438 
439   // Finally, create units for leaf registers without ad hoc aliases. Note that
440   // a leaf register with ad hoc aliases doesn't get its own unit - it isn't
441   // necessary. This means the aliasing leaf registers can share a single unit.
442   if (RegUnits.empty())
443     RegUnits.set(RegBank.newRegUnit(this));
444 
445   // We have now computed the native register units. More may be adopted later
446   // for balancing purposes.
447   NativeRegUnits = RegUnits;
448 
449   return SubRegs;
450 }
451 
452 // In a register that is covered by its sub-registers, try to find redundant
453 // sub-registers. For example:
454 //
455 //   QQ0 = {Q0, Q1}
456 //   Q0 = {D0, D1}
457 //   Q1 = {D2, D3}
458 //
459 // We can infer that D1_D2 is also a sub-register, even if it wasn't named in
460 // the register definition.
461 //
462 // The explicitly specified registers form a tree. This function discovers
463 // sub-register relationships that would force a DAG.
464 //
computeSecondarySubRegs(CodeGenRegBank & RegBank)465 void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
466   SmallVector<SubRegMap::value_type, 8> NewSubRegs;
467 
468   std::queue<std::pair<CodeGenSubRegIndex*,CodeGenRegister*>> SubRegQueue;
469   for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : SubRegs)
470     SubRegQueue.push(P);
471 
472   // Look at the leading super-registers of each sub-register. Those are the
473   // candidates for new sub-registers, assuming they are fully contained in
474   // this register.
475   while (!SubRegQueue.empty()) {
476     CodeGenSubRegIndex *SubRegIdx;
477     const CodeGenRegister *SubReg;
478     std::tie(SubRegIdx, SubReg) = SubRegQueue.front();
479     SubRegQueue.pop();
480 
481     const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs;
482     for (unsigned i = 0, e = Leads.size(); i != e; ++i) {
483       CodeGenRegister *Cand = const_cast<CodeGenRegister*>(Leads[i]);
484       // Already got this sub-register?
485       if (Cand == this || getSubRegIndex(Cand))
486         continue;
487       // Check if each component of Cand is already a sub-register.
488       assert(!Cand->ExplicitSubRegs.empty() &&
489              "Super-register has no sub-registers");
490       if (Cand->ExplicitSubRegs.size() == 1)
491         continue;
492       SmallVector<CodeGenSubRegIndex*, 8> Parts;
493       // We know that the first component is (SubRegIdx,SubReg). However we
494       // may still need to split it into smaller subregister parts.
495       assert(Cand->ExplicitSubRegs[0] == SubReg && "LeadingSuperRegs correct");
496       assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct");
497       for (CodeGenRegister *SubReg : Cand->ExplicitSubRegs) {
498         if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) {
499           if (SubRegIdx->ConcatenationOf.empty()) {
500             Parts.push_back(SubRegIdx);
501           } else
502             for (CodeGenSubRegIndex *SubIdx : SubRegIdx->ConcatenationOf)
503               Parts.push_back(SubIdx);
504         } else {
505           // Sub-register doesn't exist.
506           Parts.clear();
507           break;
508         }
509       }
510       // There is nothing to do if some Cand sub-register is not part of this
511       // register.
512       if (Parts.empty())
513         continue;
514 
515       // Each part of Cand is a sub-register of this. Make the full Cand also
516       // a sub-register with a concatenated sub-register index.
517       CodeGenSubRegIndex *Concat = RegBank.getConcatSubRegIndex(Parts);
518       std::pair<CodeGenSubRegIndex*,CodeGenRegister*> NewSubReg =
519           std::make_pair(Concat, Cand);
520 
521       if (!SubRegs.insert(NewSubReg).second)
522         continue;
523 
524       // We inserted a new subregister.
525       NewSubRegs.push_back(NewSubReg);
526       SubRegQueue.push(NewSubReg);
527       SubReg2Idx.insert(std::make_pair(Cand, Concat));
528     }
529   }
530 
531   // Create sub-register index composition maps for the synthesized indices.
532   for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) {
533     CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first;
534     CodeGenRegister *NewSubReg = NewSubRegs[i].second;
535     for (SubRegMap::const_iterator SI = NewSubReg->SubRegs.begin(),
536            SE = NewSubReg->SubRegs.end(); SI != SE; ++SI) {
537       CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second);
538       if (!SubIdx)
539         PrintFatalError(TheDef->getLoc(), "No SubRegIndex for " +
540                         SI->second->getName() + " in " + getName());
541       NewIdx->addComposite(SI->first, SubIdx);
542     }
543   }
544 }
545 
computeSuperRegs(CodeGenRegBank & RegBank)546 void CodeGenRegister::computeSuperRegs(CodeGenRegBank &RegBank) {
547   // Only visit each register once.
548   if (SuperRegsComplete)
549     return;
550   SuperRegsComplete = true;
551 
552   // Make sure all sub-registers have been visited first, so the super-reg
553   // lists will be topologically ordered.
554   for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
555        I != E; ++I)
556     I->second->computeSuperRegs(RegBank);
557 
558   // Now add this as a super-register on all sub-registers.
559   // Also compute the TopoSigId in post-order.
560   TopoSigId Id;
561   for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
562        I != E; ++I) {
563     // Topological signature computed from SubIdx, TopoId(SubReg).
564     // Loops and idempotent indices have TopoSig = ~0u.
565     Id.push_back(I->first->EnumValue);
566     Id.push_back(I->second->TopoSig);
567 
568     // Don't add duplicate entries.
569     if (!I->second->SuperRegs.empty() && I->second->SuperRegs.back() == this)
570       continue;
571     I->second->SuperRegs.push_back(this);
572   }
573   TopoSig = RegBank.getTopoSig(Id);
574 }
575 
576 void
addSubRegsPreOrder(SetVector<const CodeGenRegister * > & OSet,CodeGenRegBank & RegBank) const577 CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
578                                     CodeGenRegBank &RegBank) const {
579   assert(SubRegsComplete && "Must precompute sub-registers");
580   for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
581     CodeGenRegister *SR = ExplicitSubRegs[i];
582     if (OSet.insert(SR))
583       SR->addSubRegsPreOrder(OSet, RegBank);
584   }
585   // Add any secondary sub-registers that weren't part of the explicit tree.
586   for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
587        I != E; ++I)
588     OSet.insert(I->second);
589 }
590 
591 // Get the sum of this register's unit weights.
getWeight(const CodeGenRegBank & RegBank) const592 unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const {
593   unsigned Weight = 0;
594   for (RegUnitList::iterator I = RegUnits.begin(), E = RegUnits.end();
595        I != E; ++I) {
596     Weight += RegBank.getRegUnit(*I).Weight;
597   }
598   return Weight;
599 }
600 
601 //===----------------------------------------------------------------------===//
602 //                               RegisterTuples
603 //===----------------------------------------------------------------------===//
604 
605 // A RegisterTuples def is used to generate pseudo-registers from lists of
606 // sub-registers. We provide a SetTheory expander class that returns the new
607 // registers.
608 namespace {
609 
610 struct TupleExpander : SetTheory::Expander {
611   // Reference to SynthDefs in the containing CodeGenRegBank, to keep track of
612   // the synthesized definitions for their lifetime.
613   std::vector<std::unique_ptr<Record>> &SynthDefs;
614 
TupleExpander__anonebe1174b0211::TupleExpander615   TupleExpander(std::vector<std::unique_ptr<Record>> &SynthDefs)
616       : SynthDefs(SynthDefs) {}
617 
expand__anonebe1174b0211::TupleExpander618   void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) override {
619     std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
620     unsigned Dim = Indices.size();
621     ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
622     if (Dim != SubRegs->size())
623       PrintFatalError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
624     if (Dim < 2)
625       PrintFatalError(Def->getLoc(),
626                       "Tuples must have at least 2 sub-registers");
627 
628     // Evaluate the sub-register lists to be zipped.
629     unsigned Length = ~0u;
630     SmallVector<SetTheory::RecSet, 4> Lists(Dim);
631     for (unsigned i = 0; i != Dim; ++i) {
632       ST.evaluate(SubRegs->getElement(i), Lists[i], Def->getLoc());
633       Length = std::min(Length, unsigned(Lists[i].size()));
634     }
635 
636     if (Length == 0)
637       return;
638 
639     // Precompute some types.
640     Record *RegisterCl = Def->getRecords().getClass("Register");
641     RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl);
642     StringInit *BlankName = StringInit::get("");
643 
644     // Zip them up.
645     for (unsigned n = 0; n != Length; ++n) {
646       std::string Name;
647       Record *Proto = Lists[0][n];
648       std::vector<Init*> Tuple;
649       unsigned CostPerUse = 0;
650       for (unsigned i = 0; i != Dim; ++i) {
651         Record *Reg = Lists[i][n];
652         if (i) Name += '_';
653         Name += Reg->getName();
654         Tuple.push_back(DefInit::get(Reg));
655         CostPerUse = std::max(CostPerUse,
656                               unsigned(Reg->getValueAsInt("CostPerUse")));
657       }
658 
659       // Create a new Record representing the synthesized register. This record
660       // is only for consumption by CodeGenRegister, it is not added to the
661       // RecordKeeper.
662       SynthDefs.emplace_back(
663           llvm::make_unique<Record>(Name, Def->getLoc(), Def->getRecords()));
664       Record *NewReg = SynthDefs.back().get();
665       Elts.insert(NewReg);
666 
667       // Copy Proto super-classes.
668       ArrayRef<std::pair<Record *, SMRange>> Supers = Proto->getSuperClasses();
669       for (const auto &SuperPair : Supers)
670         NewReg->addSuperClass(SuperPair.first, SuperPair.second);
671 
672       // Copy Proto fields.
673       for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) {
674         RecordVal RV = Proto->getValues()[i];
675 
676         // Skip existing fields, like NAME.
677         if (NewReg->getValue(RV.getNameInit()))
678           continue;
679 
680         StringRef Field = RV.getName();
681 
682         // Replace the sub-register list with Tuple.
683         if (Field == "SubRegs")
684           RV.setValue(ListInit::get(Tuple, RegisterRecTy));
685 
686         // Provide a blank AsmName. MC hacks are required anyway.
687         if (Field == "AsmName")
688           RV.setValue(BlankName);
689 
690         // CostPerUse is aggregated from all Tuple members.
691         if (Field == "CostPerUse")
692           RV.setValue(IntInit::get(CostPerUse));
693 
694         // Composite registers are always covered by sub-registers.
695         if (Field == "CoveredBySubRegs")
696           RV.setValue(BitInit::get(true));
697 
698         // Copy fields from the RegisterTuples def.
699         if (Field == "SubRegIndices" ||
700             Field == "CompositeIndices") {
701           NewReg->addValue(*Def->getValue(Field));
702           continue;
703         }
704 
705         // Some fields get their default uninitialized value.
706         if (Field == "DwarfNumbers" ||
707             Field == "DwarfAlias" ||
708             Field == "Aliases") {
709           if (const RecordVal *DefRV = RegisterCl->getValue(Field))
710             NewReg->addValue(*DefRV);
711           continue;
712         }
713 
714         // Everything else is copied from Proto.
715         NewReg->addValue(RV);
716       }
717     }
718   }
719 };
720 
721 } // end anonymous namespace
722 
723 //===----------------------------------------------------------------------===//
724 //                            CodeGenRegisterClass
725 //===----------------------------------------------------------------------===//
726 
sortAndUniqueRegisters(CodeGenRegister::Vec & M)727 static void sortAndUniqueRegisters(CodeGenRegister::Vec &M) {
728   llvm::sort(M.begin(), M.end(), deref<llvm::less>());
729   M.erase(std::unique(M.begin(), M.end(), deref<llvm::equal>()), M.end());
730 }
731 
CodeGenRegisterClass(CodeGenRegBank & RegBank,Record * R)732 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
733   : TheDef(R),
734     Name(R->getName()),
735     TopoSigs(RegBank.getNumTopoSigs()),
736     EnumValue(-1) {
737 
738   std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
739   for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
740     Record *Type = TypeList[i];
741     if (!Type->isSubClassOf("ValueType"))
742       PrintFatalError("RegTypes list member '" + Type->getName() +
743         "' does not derive from the ValueType class!");
744     VTs.push_back(getValueTypeByHwMode(Type, RegBank.getHwModes()));
745   }
746   assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
747 
748   // Allocation order 0 is the full set. AltOrders provides others.
749   const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
750   ListInit *AltOrders = R->getValueAsListInit("AltOrders");
751   Orders.resize(1 + AltOrders->size());
752 
753   // Default allocation order always contains all registers.
754   Artificial = true;
755   for (unsigned i = 0, e = Elements->size(); i != e; ++i) {
756     Orders[0].push_back((*Elements)[i]);
757     const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]);
758     Members.push_back(Reg);
759     Artificial &= Reg->Artificial;
760     TopoSigs.set(Reg->getTopoSig());
761   }
762   sortAndUniqueRegisters(Members);
763 
764   // Alternative allocation orders may be subsets.
765   SetTheory::RecSet Order;
766   for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) {
767     RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc());
768     Orders[1 + i].append(Order.begin(), Order.end());
769     // Verify that all altorder members are regclass members.
770     while (!Order.empty()) {
771       CodeGenRegister *Reg = RegBank.getReg(Order.back());
772       Order.pop_back();
773       if (!contains(Reg))
774         PrintFatalError(R->getLoc(), " AltOrder register " + Reg->getName() +
775                       " is not a class member");
776     }
777   }
778 
779   Namespace = R->getValueAsString("Namespace");
780 
781   if (const RecordVal *RV = R->getValue("RegInfos"))
782     if (DefInit *DI = dyn_cast_or_null<DefInit>(RV->getValue()))
783       RSI = RegSizeInfoByHwMode(DI->getDef(), RegBank.getHwModes());
784   unsigned Size = R->getValueAsInt("Size");
785   assert((RSI.hasDefault() || Size != 0 || VTs[0].isSimple()) &&
786          "Impossible to determine register size");
787   if (!RSI.hasDefault()) {
788     RegSizeInfo RI;
789     RI.RegSize = RI.SpillSize = Size ? Size
790                                      : VTs[0].getSimple().getSizeInBits();
791     RI.SpillAlignment = R->getValueAsInt("Alignment");
792     RSI.Map.insert({DefaultMode, RI});
793   }
794 
795   CopyCost = R->getValueAsInt("CopyCost");
796   Allocatable = R->getValueAsBit("isAllocatable");
797   AltOrderSelect = R->getValueAsString("AltOrderSelect");
798   int AllocationPriority = R->getValueAsInt("AllocationPriority");
799   if (AllocationPriority < 0 || AllocationPriority > 63)
800     PrintFatalError(R->getLoc(), "AllocationPriority out of range [0,63]");
801   this->AllocationPriority = AllocationPriority;
802 }
803 
804 // Create an inferred register class that was missing from the .td files.
805 // Most properties will be inherited from the closest super-class after the
806 // class structure has been computed.
CodeGenRegisterClass(CodeGenRegBank & RegBank,StringRef Name,Key Props)807 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
808                                            StringRef Name, Key Props)
809   : Members(*Props.Members),
810     TheDef(nullptr),
811     Name(Name),
812     TopoSigs(RegBank.getNumTopoSigs()),
813     EnumValue(-1),
814     RSI(Props.RSI),
815     CopyCost(0),
816     Allocatable(true),
817     AllocationPriority(0) {
818   Artificial = true;
819   for (const auto R : Members) {
820     TopoSigs.set(R->getTopoSig());
821     Artificial &= R->Artificial;
822   }
823 }
824 
825 // Compute inherited propertied for a synthesized register class.
inheritProperties(CodeGenRegBank & RegBank)826 void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
827   assert(!getDef() && "Only synthesized classes can inherit properties");
828   assert(!SuperClasses.empty() && "Synthesized class without super class");
829 
830   // The last super-class is the smallest one.
831   CodeGenRegisterClass &Super = *SuperClasses.back();
832 
833   // Most properties are copied directly.
834   // Exceptions are members, size, and alignment
835   Namespace = Super.Namespace;
836   VTs = Super.VTs;
837   CopyCost = Super.CopyCost;
838   Allocatable = Super.Allocatable;
839   AltOrderSelect = Super.AltOrderSelect;
840   AllocationPriority = Super.AllocationPriority;
841 
842   // Copy all allocation orders, filter out foreign registers from the larger
843   // super-class.
844   Orders.resize(Super.Orders.size());
845   for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i)
846     for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j)
847       if (contains(RegBank.getReg(Super.Orders[i][j])))
848         Orders[i].push_back(Super.Orders[i][j]);
849 }
850 
contains(const CodeGenRegister * Reg) const851 bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
852   return std::binary_search(Members.begin(), Members.end(), Reg,
853                             deref<llvm::less>());
854 }
855 
856 namespace llvm {
857 
operator <<(raw_ostream & OS,const CodeGenRegisterClass::Key & K)858   raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) {
859     OS << "{ " << K.RSI;
860     for (const auto R : *K.Members)
861       OS << ", " << R->getName();
862     return OS << " }";
863   }
864 
865 } // end namespace llvm
866 
867 // This is a simple lexicographical order that can be used to search for sets.
868 // It is not the same as the topological order provided by TopoOrderRC.
869 bool CodeGenRegisterClass::Key::
operator <(const CodeGenRegisterClass::Key & B) const870 operator<(const CodeGenRegisterClass::Key &B) const {
871   assert(Members && B.Members);
872   return std::tie(*Members, RSI) < std::tie(*B.Members, B.RSI);
873 }
874 
875 // Returns true if RC is a strict subclass.
876 // RC is a sub-class of this class if it is a valid replacement for any
877 // instruction operand where a register of this classis required. It must
878 // satisfy these conditions:
879 //
880 // 1. All RC registers are also in this.
881 // 2. The RC spill size must not be smaller than our spill size.
882 // 3. RC spill alignment must be compatible with ours.
883 //
testSubClass(const CodeGenRegisterClass * A,const CodeGenRegisterClass * B)884 static bool testSubClass(const CodeGenRegisterClass *A,
885                          const CodeGenRegisterClass *B) {
886   return A->RSI.isSubClassOf(B->RSI) &&
887          std::includes(A->getMembers().begin(), A->getMembers().end(),
888                        B->getMembers().begin(), B->getMembers().end(),
889                        deref<llvm::less>());
890 }
891 
892 /// Sorting predicate for register classes.  This provides a topological
893 /// ordering that arranges all register classes before their sub-classes.
894 ///
895 /// Register classes with the same registers, spill size, and alignment form a
896 /// clique.  They will be ordered alphabetically.
897 ///
TopoOrderRC(const CodeGenRegisterClass & PA,const CodeGenRegisterClass & PB)898 static bool TopoOrderRC(const CodeGenRegisterClass &PA,
899                         const CodeGenRegisterClass &PB) {
900   auto *A = &PA;
901   auto *B = &PB;
902   if (A == B)
903     return false;
904 
905   if (A->RSI < B->RSI)
906     return true;
907   if (A->RSI != B->RSI)
908     return false;
909 
910   // Order by descending set size.  Note that the classes' allocation order may
911   // not have been computed yet.  The Members set is always vaild.
912   if (A->getMembers().size() > B->getMembers().size())
913     return true;
914   if (A->getMembers().size() < B->getMembers().size())
915     return false;
916 
917   // Finally order by name as a tie breaker.
918   return StringRef(A->getName()) < B->getName();
919 }
920 
getQualifiedName() const921 std::string CodeGenRegisterClass::getQualifiedName() const {
922   if (Namespace.empty())
923     return getName();
924   else
925     return (Namespace + "::" + getName()).str();
926 }
927 
928 // Compute sub-classes of all register classes.
929 // Assume the classes are ordered topologically.
computeSubClasses(CodeGenRegBank & RegBank)930 void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
931   auto &RegClasses = RegBank.getRegClasses();
932 
933   // Visit backwards so sub-classes are seen first.
934   for (auto I = RegClasses.rbegin(), E = RegClasses.rend(); I != E; ++I) {
935     CodeGenRegisterClass &RC = *I;
936     RC.SubClasses.resize(RegClasses.size());
937     RC.SubClasses.set(RC.EnumValue);
938     if (RC.Artificial)
939       continue;
940 
941     // Normally, all subclasses have IDs >= rci, unless RC is part of a clique.
942     for (auto I2 = I.base(), E2 = RegClasses.end(); I2 != E2; ++I2) {
943       CodeGenRegisterClass &SubRC = *I2;
944       if (RC.SubClasses.test(SubRC.EnumValue))
945         continue;
946       if (!testSubClass(&RC, &SubRC))
947         continue;
948       // SubRC is a sub-class. Grap all its sub-classes so we won't have to
949       // check them again.
950       RC.SubClasses |= SubRC.SubClasses;
951     }
952 
953     // Sweep up missed clique members.  They will be immediately preceding RC.
954     for (auto I2 = std::next(I); I2 != E && testSubClass(&RC, &*I2); ++I2)
955       RC.SubClasses.set(I2->EnumValue);
956   }
957 
958   // Compute the SuperClasses lists from the SubClasses vectors.
959   for (auto &RC : RegClasses) {
960     const BitVector &SC = RC.getSubClasses();
961     auto I = RegClasses.begin();
962     for (int s = 0, next_s = SC.find_first(); next_s != -1;
963          next_s = SC.find_next(s)) {
964       std::advance(I, next_s - s);
965       s = next_s;
966       if (&*I == &RC)
967         continue;
968       I->SuperClasses.push_back(&RC);
969     }
970   }
971 
972   // With the class hierarchy in place, let synthesized register classes inherit
973   // properties from their closest super-class. The iteration order here can
974   // propagate properties down multiple levels.
975   for (auto &RC : RegClasses)
976     if (!RC.getDef())
977       RC.inheritProperties(RegBank);
978 }
979 
980 Optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>>
getMatchingSubClassWithSubRegs(CodeGenRegBank & RegBank,const CodeGenSubRegIndex * SubIdx) const981 CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
982     CodeGenRegBank &RegBank, const CodeGenSubRegIndex *SubIdx) const {
983   auto SizeOrder = [](const CodeGenRegisterClass *A,
984                       const CodeGenRegisterClass *B) {
985     return A->getMembers().size() > B->getMembers().size();
986   };
987 
988   auto &RegClasses = RegBank.getRegClasses();
989 
990   // Find all the subclasses of this one that fully support the sub-register
991   // index and order them by size. BiggestSuperRC should always be first.
992   CodeGenRegisterClass *BiggestSuperRegRC = getSubClassWithSubReg(SubIdx);
993   if (!BiggestSuperRegRC)
994     return None;
995   BitVector SuperRegRCsBV = BiggestSuperRegRC->getSubClasses();
996   std::vector<CodeGenRegisterClass *> SuperRegRCs;
997   for (auto &RC : RegClasses)
998     if (SuperRegRCsBV[RC.EnumValue])
999       SuperRegRCs.emplace_back(&RC);
1000   llvm::sort(SuperRegRCs.begin(), SuperRegRCs.end(), SizeOrder);
1001   assert(SuperRegRCs.front() == BiggestSuperRegRC && "Biggest class wasn't first");
1002 
1003   // Find all the subreg classes and order them by size too.
1004   std::vector<std::pair<CodeGenRegisterClass *, BitVector>> SuperRegClasses;
1005   for (auto &RC: RegClasses) {
1006     BitVector SuperRegClassesBV(RegClasses.size());
1007     RC.getSuperRegClasses(SubIdx, SuperRegClassesBV);
1008     if (SuperRegClassesBV.any())
1009       SuperRegClasses.push_back(std::make_pair(&RC, SuperRegClassesBV));
1010   }
1011   llvm::sort(SuperRegClasses.begin(), SuperRegClasses.end(),
1012              [&](const std::pair<CodeGenRegisterClass *, BitVector> &A,
1013                  const std::pair<CodeGenRegisterClass *, BitVector> &B) {
1014                return SizeOrder(A.first, B.first);
1015              });
1016 
1017   // Find the biggest subclass and subreg class such that R:subidx is in the
1018   // subreg class for all R in subclass.
1019   //
1020   // For example:
1021   // All registers in X86's GR64 have a sub_32bit subregister but no class
1022   // exists that contains all the 32-bit subregisters because GR64 contains RIP
1023   // but GR32 does not contain EIP. Instead, we constrain SuperRegRC to
1024   // GR32_with_sub_8bit (which is identical to GR32_with_sub_32bit) and then,
1025   // having excluded RIP, we are able to find a SubRegRC (GR32).
1026   CodeGenRegisterClass *ChosenSuperRegClass = nullptr;
1027   CodeGenRegisterClass *SubRegRC = nullptr;
1028   for (auto *SuperRegRC : SuperRegRCs) {
1029     for (const auto &SuperRegClassPair : SuperRegClasses) {
1030       const BitVector &SuperRegClassBV = SuperRegClassPair.second;
1031       if (SuperRegClassBV[SuperRegRC->EnumValue]) {
1032         SubRegRC = SuperRegClassPair.first;
1033         ChosenSuperRegClass = SuperRegRC;
1034 
1035         // If SubRegRC is bigger than SuperRegRC then there are members of
1036         // SubRegRC that don't have super registers via SubIdx. Keep looking to
1037         // find a better fit and fall back on this one if there isn't one.
1038         //
1039         // This is intended to prevent X86 from making odd choices such as
1040         // picking LOW32_ADDR_ACCESS_RBP instead of GR32 in the example above.
1041         // LOW32_ADDR_ACCESS_RBP is a valid choice but contains registers that
1042         // aren't subregisters of SuperRegRC whereas GR32 has a direct 1:1
1043         // mapping.
1044         if (SuperRegRC->getMembers().size() >= SubRegRC->getMembers().size())
1045           return std::make_pair(ChosenSuperRegClass, SubRegRC);
1046       }
1047     }
1048 
1049     // If we found a fit but it wasn't quite ideal because SubRegRC had excess
1050     // registers, then we're done.
1051     if (ChosenSuperRegClass)
1052       return std::make_pair(ChosenSuperRegClass, SubRegRC);
1053   }
1054 
1055   return None;
1056 }
1057 
getSuperRegClasses(const CodeGenSubRegIndex * SubIdx,BitVector & Out) const1058 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
1059                                               BitVector &Out) const {
1060   auto FindI = SuperRegClasses.find(SubIdx);
1061   if (FindI == SuperRegClasses.end())
1062     return;
1063   for (CodeGenRegisterClass *RC : FindI->second)
1064     Out.set(RC->EnumValue);
1065 }
1066 
1067 // Populate a unique sorted list of units from a register set.
buildRegUnitSet(const CodeGenRegBank & RegBank,std::vector<unsigned> & RegUnits) const1068 void CodeGenRegisterClass::buildRegUnitSet(const CodeGenRegBank &RegBank,
1069   std::vector<unsigned> &RegUnits) const {
1070   std::vector<unsigned> TmpUnits;
1071   for (RegUnitIterator UnitI(Members); UnitI.isValid(); ++UnitI) {
1072     const RegUnit &RU = RegBank.getRegUnit(*UnitI);
1073     if (!RU.Artificial)
1074       TmpUnits.push_back(*UnitI);
1075   }
1076   llvm::sort(TmpUnits.begin(), TmpUnits.end());
1077   std::unique_copy(TmpUnits.begin(), TmpUnits.end(),
1078                    std::back_inserter(RegUnits));
1079 }
1080 
1081 //===----------------------------------------------------------------------===//
1082 //                               CodeGenRegBank
1083 //===----------------------------------------------------------------------===//
1084 
CodeGenRegBank(RecordKeeper & Records,const CodeGenHwModes & Modes)1085 CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
1086                                const CodeGenHwModes &Modes) : CGH(Modes) {
1087   // Configure register Sets to understand register classes and tuples.
1088   Sets.addFieldExpander("RegisterClass", "MemberList");
1089   Sets.addFieldExpander("CalleeSavedRegs", "SaveList");
1090   Sets.addExpander("RegisterTuples",
1091                    llvm::make_unique<TupleExpander>(SynthDefs));
1092 
1093   // Read in the user-defined (named) sub-register indices.
1094   // More indices will be synthesized later.
1095   std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex");
1096   llvm::sort(SRIs.begin(), SRIs.end(), LessRecord());
1097   for (unsigned i = 0, e = SRIs.size(); i != e; ++i)
1098     getSubRegIdx(SRIs[i]);
1099   // Build composite maps from ComposedOf fields.
1100   for (auto &Idx : SubRegIndices)
1101     Idx.updateComponents(*this);
1102 
1103   // Read in the register definitions.
1104   std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
1105   llvm::sort(Regs.begin(), Regs.end(), LessRecordRegister());
1106   // Assign the enumeration values.
1107   for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1108     getReg(Regs[i]);
1109 
1110   // Expand tuples and number the new registers.
1111   std::vector<Record*> Tups =
1112     Records.getAllDerivedDefinitions("RegisterTuples");
1113 
1114   for (Record *R : Tups) {
1115     std::vector<Record *> TupRegs = *Sets.expand(R);
1116     llvm::sort(TupRegs.begin(), TupRegs.end(), LessRecordRegister());
1117     for (Record *RC : TupRegs)
1118       getReg(RC);
1119   }
1120 
1121   // Now all the registers are known. Build the object graph of explicit
1122   // register-register references.
1123   for (auto &Reg : Registers)
1124     Reg.buildObjectGraph(*this);
1125 
1126   // Compute register name map.
1127   for (auto &Reg : Registers)
1128     // FIXME: This could just be RegistersByName[name] = register, except that
1129     // causes some failures in MIPS - perhaps they have duplicate register name
1130     // entries? (or maybe there's a reason for it - I don't know much about this
1131     // code, just drive-by refactoring)
1132     RegistersByName.insert(
1133         std::make_pair(Reg.TheDef->getValueAsString("AsmName"), &Reg));
1134 
1135   // Precompute all sub-register maps.
1136   // This will create Composite entries for all inferred sub-register indices.
1137   for (auto &Reg : Registers)
1138     Reg.computeSubRegs(*this);
1139 
1140   // Compute transitive closure of subregister index ConcatenationOf vectors
1141   // and initialize ConcatIdx map.
1142   for (CodeGenSubRegIndex &SRI : SubRegIndices) {
1143     SRI.computeConcatTransitiveClosure();
1144     if (!SRI.ConcatenationOf.empty())
1145       ConcatIdx.insert(std::make_pair(
1146           SmallVector<CodeGenSubRegIndex*,8>(SRI.ConcatenationOf.begin(),
1147                                              SRI.ConcatenationOf.end()), &SRI));
1148   }
1149 
1150   // Infer even more sub-registers by combining leading super-registers.
1151   for (auto &Reg : Registers)
1152     if (Reg.CoveredBySubRegs)
1153       Reg.computeSecondarySubRegs(*this);
1154 
1155   // After the sub-register graph is complete, compute the topologically
1156   // ordered SuperRegs list.
1157   for (auto &Reg : Registers)
1158     Reg.computeSuperRegs(*this);
1159 
1160   // For each pair of Reg:SR, if both are non-artificial, mark the
1161   // corresponding sub-register index as non-artificial.
1162   for (auto &Reg : Registers) {
1163     if (Reg.Artificial)
1164       continue;
1165     for (auto P : Reg.getSubRegs()) {
1166       const CodeGenRegister *SR = P.second;
1167       if (!SR->Artificial)
1168         P.first->Artificial = false;
1169     }
1170   }
1171 
1172   // Native register units are associated with a leaf register. They've all been
1173   // discovered now.
1174   NumNativeRegUnits = RegUnits.size();
1175 
1176   // Read in register class definitions.
1177   std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
1178   if (RCs.empty())
1179     PrintFatalError("No 'RegisterClass' subclasses defined!");
1180 
1181   // Allocate user-defined register classes.
1182   for (auto *R : RCs) {
1183     RegClasses.emplace_back(*this, R);
1184     CodeGenRegisterClass &RC = RegClasses.back();
1185     if (!RC.Artificial)
1186       addToMaps(&RC);
1187   }
1188 
1189   // Infer missing classes to create a full algebra.
1190   computeInferredRegisterClasses();
1191 
1192   // Order register classes topologically and assign enum values.
1193   RegClasses.sort(TopoOrderRC);
1194   unsigned i = 0;
1195   for (auto &RC : RegClasses)
1196     RC.EnumValue = i++;
1197   CodeGenRegisterClass::computeSubClasses(*this);
1198 }
1199 
1200 // Create a synthetic CodeGenSubRegIndex without a corresponding Record.
1201 CodeGenSubRegIndex*
createSubRegIndex(StringRef Name,StringRef Namespace)1202 CodeGenRegBank::createSubRegIndex(StringRef Name, StringRef Namespace) {
1203   SubRegIndices.emplace_back(Name, Namespace, SubRegIndices.size() + 1);
1204   return &SubRegIndices.back();
1205 }
1206 
getSubRegIdx(Record * Def)1207 CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) {
1208   CodeGenSubRegIndex *&Idx = Def2SubRegIdx[Def];
1209   if (Idx)
1210     return Idx;
1211   SubRegIndices.emplace_back(Def, SubRegIndices.size() + 1);
1212   Idx = &SubRegIndices.back();
1213   return Idx;
1214 }
1215 
getReg(Record * Def)1216 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
1217   CodeGenRegister *&Reg = Def2Reg[Def];
1218   if (Reg)
1219     return Reg;
1220   Registers.emplace_back(Def, Registers.size() + 1);
1221   Reg = &Registers.back();
1222   return Reg;
1223 }
1224 
addToMaps(CodeGenRegisterClass * RC)1225 void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) {
1226   if (Record *Def = RC->getDef())
1227     Def2RC.insert(std::make_pair(Def, RC));
1228 
1229   // Duplicate classes are rejected by insert().
1230   // That's OK, we only care about the properties handled by CGRC::Key.
1231   CodeGenRegisterClass::Key K(*RC);
1232   Key2RC.insert(std::make_pair(K, RC));
1233 }
1234 
1235 // Create a synthetic sub-class if it is missing.
1236 CodeGenRegisterClass*
getOrCreateSubClass(const CodeGenRegisterClass * RC,const CodeGenRegister::Vec * Members,StringRef Name)1237 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC,
1238                                     const CodeGenRegister::Vec *Members,
1239                                     StringRef Name) {
1240   // Synthetic sub-class has the same size and alignment as RC.
1241   CodeGenRegisterClass::Key K(Members, RC->RSI);
1242   RCKeyMap::const_iterator FoundI = Key2RC.find(K);
1243   if (FoundI != Key2RC.end())
1244     return FoundI->second;
1245 
1246   // Sub-class doesn't exist, create a new one.
1247   RegClasses.emplace_back(*this, Name, K);
1248   addToMaps(&RegClasses.back());
1249   return &RegClasses.back();
1250 }
1251 
getRegClass(Record * Def)1252 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
1253   if (CodeGenRegisterClass *RC = Def2RC[Def])
1254     return RC;
1255 
1256   PrintFatalError(Def->getLoc(), "Not a known RegisterClass!");
1257 }
1258 
1259 CodeGenSubRegIndex*
getCompositeSubRegIndex(CodeGenSubRegIndex * A,CodeGenSubRegIndex * B)1260 CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A,
1261                                         CodeGenSubRegIndex *B) {
1262   // Look for an existing entry.
1263   CodeGenSubRegIndex *Comp = A->compose(B);
1264   if (Comp)
1265     return Comp;
1266 
1267   // None exists, synthesize one.
1268   std::string Name = A->getName() + "_then_" + B->getName();
1269   Comp = createSubRegIndex(Name, A->getNamespace());
1270   A->addComposite(B, Comp);
1271   return Comp;
1272 }
1273 
1274 CodeGenSubRegIndex *CodeGenRegBank::
getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *,8> & Parts)1275 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts) {
1276   assert(Parts.size() > 1 && "Need two parts to concatenate");
1277 #ifndef NDEBUG
1278   for (CodeGenSubRegIndex *Idx : Parts) {
1279     assert(Idx->ConcatenationOf.empty() && "No transitive closure?");
1280   }
1281 #endif
1282 
1283   // Look for an existing entry.
1284   CodeGenSubRegIndex *&Idx = ConcatIdx[Parts];
1285   if (Idx)
1286     return Idx;
1287 
1288   // None exists, synthesize one.
1289   std::string Name = Parts.front()->getName();
1290   // Determine whether all parts are contiguous.
1291   bool isContinuous = true;
1292   unsigned Size = Parts.front()->Size;
1293   unsigned LastOffset = Parts.front()->Offset;
1294   unsigned LastSize = Parts.front()->Size;
1295   for (unsigned i = 1, e = Parts.size(); i != e; ++i) {
1296     Name += '_';
1297     Name += Parts[i]->getName();
1298     Size += Parts[i]->Size;
1299     if (Parts[i]->Offset != (LastOffset + LastSize))
1300       isContinuous = false;
1301     LastOffset = Parts[i]->Offset;
1302     LastSize = Parts[i]->Size;
1303   }
1304   Idx = createSubRegIndex(Name, Parts.front()->getNamespace());
1305   Idx->Size = Size;
1306   Idx->Offset = isContinuous ? Parts.front()->Offset : -1;
1307   Idx->ConcatenationOf.assign(Parts.begin(), Parts.end());
1308   return Idx;
1309 }
1310 
computeComposites()1311 void CodeGenRegBank::computeComposites() {
1312   // Keep track of TopoSigs visited. We only need to visit each TopoSig once,
1313   // and many registers will share TopoSigs on regular architectures.
1314   BitVector TopoSigs(getNumTopoSigs());
1315 
1316   for (const auto &Reg1 : Registers) {
1317     // Skip identical subreg structures already processed.
1318     if (TopoSigs.test(Reg1.getTopoSig()))
1319       continue;
1320     TopoSigs.set(Reg1.getTopoSig());
1321 
1322     const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs();
1323     for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
1324          e1 = SRM1.end(); i1 != e1; ++i1) {
1325       CodeGenSubRegIndex *Idx1 = i1->first;
1326       CodeGenRegister *Reg2 = i1->second;
1327       // Ignore identity compositions.
1328       if (&Reg1 == Reg2)
1329         continue;
1330       const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
1331       // Try composing Idx1 with another SubRegIndex.
1332       for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
1333            e2 = SRM2.end(); i2 != e2; ++i2) {
1334         CodeGenSubRegIndex *Idx2 = i2->first;
1335         CodeGenRegister *Reg3 = i2->second;
1336         // Ignore identity compositions.
1337         if (Reg2 == Reg3)
1338           continue;
1339         // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
1340         CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg3);
1341         assert(Idx3 && "Sub-register doesn't have an index");
1342 
1343         // Conflicting composition? Emit a warning but allow it.
1344         if (CodeGenSubRegIndex *Prev = Idx1->addComposite(Idx2, Idx3))
1345           PrintWarning(Twine("SubRegIndex ") + Idx1->getQualifiedName() +
1346                        " and " + Idx2->getQualifiedName() +
1347                        " compose ambiguously as " + Prev->getQualifiedName() +
1348                        " or " + Idx3->getQualifiedName());
1349       }
1350     }
1351   }
1352 }
1353 
1354 // Compute lane masks. This is similar to register units, but at the
1355 // sub-register index level. Each bit in the lane mask is like a register unit
1356 // class, and two lane masks will have a bit in common if two sub-register
1357 // indices overlap in some register.
1358 //
1359 // Conservatively share a lane mask bit if two sub-register indices overlap in
1360 // some registers, but not in others. That shouldn't happen a lot.
computeSubRegLaneMasks()1361 void CodeGenRegBank::computeSubRegLaneMasks() {
1362   // First assign individual bits to all the leaf indices.
1363   unsigned Bit = 0;
1364   // Determine mask of lanes that cover their registers.
1365   CoveringLanes = LaneBitmask::getAll();
1366   for (auto &Idx : SubRegIndices) {
1367     if (Idx.getComposites().empty()) {
1368       if (Bit > LaneBitmask::BitWidth) {
1369         PrintFatalError(
1370           Twine("Ran out of lanemask bits to represent subregister ")
1371           + Idx.getName());
1372       }
1373       Idx.LaneMask = LaneBitmask::getLane(Bit);
1374       ++Bit;
1375     } else {
1376       Idx.LaneMask = LaneBitmask::getNone();
1377     }
1378   }
1379 
1380   // Compute transformation sequences for composeSubRegIndexLaneMask. The idea
1381   // here is that for each possible target subregister we look at the leafs
1382   // in the subregister graph that compose for this target and create
1383   // transformation sequences for the lanemasks. Each step in the sequence
1384   // consists of a bitmask and a bitrotate operation. As the rotation amounts
1385   // are usually the same for many subregisters we can easily combine the steps
1386   // by combining the masks.
1387   for (const auto &Idx : SubRegIndices) {
1388     const auto &Composites = Idx.getComposites();
1389     auto &LaneTransforms = Idx.CompositionLaneMaskTransform;
1390 
1391     if (Composites.empty()) {
1392       // Moving from a class with no subregisters we just had a single lane:
1393       // The subregister must be a leaf subregister and only occupies 1 bit.
1394       // Move the bit from the class without subregisters into that position.
1395       unsigned DstBit = Idx.LaneMask.getHighestLane();
1396       assert(Idx.LaneMask == LaneBitmask::getLane(DstBit) &&
1397              "Must be a leaf subregister");
1398       MaskRolPair MaskRol = { LaneBitmask::getLane(0), (uint8_t)DstBit };
1399       LaneTransforms.push_back(MaskRol);
1400     } else {
1401       // Go through all leaf subregisters and find the ones that compose with
1402       // Idx. These make out all possible valid bits in the lane mask we want to
1403       // transform. Looking only at the leafs ensure that only a single bit in
1404       // the mask is set.
1405       unsigned NextBit = 0;
1406       for (auto &Idx2 : SubRegIndices) {
1407         // Skip non-leaf subregisters.
1408         if (!Idx2.getComposites().empty())
1409           continue;
1410         // Replicate the behaviour from the lane mask generation loop above.
1411         unsigned SrcBit = NextBit;
1412         LaneBitmask SrcMask = LaneBitmask::getLane(SrcBit);
1413         if (NextBit < LaneBitmask::BitWidth-1)
1414           ++NextBit;
1415         assert(Idx2.LaneMask == SrcMask);
1416 
1417         // Get the composed subregister if there is any.
1418         auto C = Composites.find(&Idx2);
1419         if (C == Composites.end())
1420           continue;
1421         const CodeGenSubRegIndex *Composite = C->second;
1422         // The Composed subreg should be a leaf subreg too
1423         assert(Composite->getComposites().empty());
1424 
1425         // Create Mask+Rotate operation and merge with existing ops if possible.
1426         unsigned DstBit = Composite->LaneMask.getHighestLane();
1427         int Shift = DstBit - SrcBit;
1428         uint8_t RotateLeft = Shift >= 0 ? (uint8_t)Shift
1429                                         : LaneBitmask::BitWidth + Shift;
1430         for (auto &I : LaneTransforms) {
1431           if (I.RotateLeft == RotateLeft) {
1432             I.Mask |= SrcMask;
1433             SrcMask = LaneBitmask::getNone();
1434           }
1435         }
1436         if (SrcMask.any()) {
1437           MaskRolPair MaskRol = { SrcMask, RotateLeft };
1438           LaneTransforms.push_back(MaskRol);
1439         }
1440       }
1441     }
1442 
1443     // Optimize if the transformation consists of one step only: Set mask to
1444     // 0xffffffff (including some irrelevant invalid bits) so that it should
1445     // merge with more entries later while compressing the table.
1446     if (LaneTransforms.size() == 1)
1447       LaneTransforms[0].Mask = LaneBitmask::getAll();
1448 
1449     // Further compression optimization: For invalid compositions resulting
1450     // in a sequence with 0 entries we can just pick any other. Choose
1451     // Mask 0xffffffff with Rotation 0.
1452     if (LaneTransforms.size() == 0) {
1453       MaskRolPair P = { LaneBitmask::getAll(), 0 };
1454       LaneTransforms.push_back(P);
1455     }
1456   }
1457 
1458   // FIXME: What if ad-hoc aliasing introduces overlaps that aren't represented
1459   // by the sub-register graph? This doesn't occur in any known targets.
1460 
1461   // Inherit lanes from composites.
1462   for (const auto &Idx : SubRegIndices) {
1463     LaneBitmask Mask = Idx.computeLaneMask();
1464     // If some super-registers without CoveredBySubRegs use this index, we can
1465     // no longer assume that the lanes are covering their registers.
1466     if (!Idx.AllSuperRegsCovered)
1467       CoveringLanes &= ~Mask;
1468   }
1469 
1470   // Compute lane mask combinations for register classes.
1471   for (auto &RegClass : RegClasses) {
1472     LaneBitmask LaneMask;
1473     for (const auto &SubRegIndex : SubRegIndices) {
1474       if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr)
1475         continue;
1476       LaneMask |= SubRegIndex.LaneMask;
1477     }
1478 
1479     // For classes without any subregisters set LaneMask to 1 instead of 0.
1480     // This makes it easier for client code to handle classes uniformly.
1481     if (LaneMask.none())
1482       LaneMask = LaneBitmask::getLane(0);
1483 
1484     RegClass.LaneMask = LaneMask;
1485   }
1486 }
1487 
1488 namespace {
1489 
1490 // UberRegSet is a helper class for computeRegUnitWeights. Each UberRegSet is
1491 // the transitive closure of the union of overlapping register
1492 // classes. Together, the UberRegSets form a partition of the registers. If we
1493 // consider overlapping register classes to be connected, then each UberRegSet
1494 // is a set of connected components.
1495 //
1496 // An UberRegSet will likely be a horizontal slice of register names of
1497 // the same width. Nontrivial subregisters should then be in a separate
1498 // UberRegSet. But this property isn't required for valid computation of
1499 // register unit weights.
1500 //
1501 // A Weight field caches the max per-register unit weight in each UberRegSet.
1502 //
1503 // A set of SingularDeterminants flags single units of some register in this set
1504 // for which the unit weight equals the set weight. These units should not have
1505 // their weight increased.
1506 struct UberRegSet {
1507   CodeGenRegister::Vec Regs;
1508   unsigned Weight = 0;
1509   CodeGenRegister::RegUnitList SingularDeterminants;
1510 
1511   UberRegSet() = default;
1512 };
1513 
1514 } // end anonymous namespace
1515 
1516 // Partition registers into UberRegSets, where each set is the transitive
1517 // closure of the union of overlapping register classes.
1518 //
1519 // UberRegSets[0] is a special non-allocatable set.
computeUberSets(std::vector<UberRegSet> & UberSets,std::vector<UberRegSet * > & RegSets,CodeGenRegBank & RegBank)1520 static void computeUberSets(std::vector<UberRegSet> &UberSets,
1521                             std::vector<UberRegSet*> &RegSets,
1522                             CodeGenRegBank &RegBank) {
1523   const auto &Registers = RegBank.getRegisters();
1524 
1525   // The Register EnumValue is one greater than its index into Registers.
1526   assert(Registers.size() == Registers.back().EnumValue &&
1527          "register enum value mismatch");
1528 
1529   // For simplicitly make the SetID the same as EnumValue.
1530   IntEqClasses UberSetIDs(Registers.size()+1);
1531   std::set<unsigned> AllocatableRegs;
1532   for (auto &RegClass : RegBank.getRegClasses()) {
1533     if (!RegClass.Allocatable)
1534       continue;
1535 
1536     const CodeGenRegister::Vec &Regs = RegClass.getMembers();
1537     if (Regs.empty())
1538       continue;
1539 
1540     unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue);
1541     assert(USetID && "register number 0 is invalid");
1542 
1543     AllocatableRegs.insert((*Regs.begin())->EnumValue);
1544     for (auto I = std::next(Regs.begin()), E = Regs.end(); I != E; ++I) {
1545       AllocatableRegs.insert((*I)->EnumValue);
1546       UberSetIDs.join(USetID, (*I)->EnumValue);
1547     }
1548   }
1549   // Combine non-allocatable regs.
1550   for (const auto &Reg : Registers) {
1551     unsigned RegNum = Reg.EnumValue;
1552     if (AllocatableRegs.count(RegNum))
1553       continue;
1554 
1555     UberSetIDs.join(0, RegNum);
1556   }
1557   UberSetIDs.compress();
1558 
1559   // Make the first UberSet a special unallocatable set.
1560   unsigned ZeroID = UberSetIDs[0];
1561 
1562   // Insert Registers into the UberSets formed by union-find.
1563   // Do not resize after this.
1564   UberSets.resize(UberSetIDs.getNumClasses());
1565   unsigned i = 0;
1566   for (const CodeGenRegister &Reg : Registers) {
1567     unsigned USetID = UberSetIDs[Reg.EnumValue];
1568     if (!USetID)
1569       USetID = ZeroID;
1570     else if (USetID == ZeroID)
1571       USetID = 0;
1572 
1573     UberRegSet *USet = &UberSets[USetID];
1574     USet->Regs.push_back(&Reg);
1575     sortAndUniqueRegisters(USet->Regs);
1576     RegSets[i++] = USet;
1577   }
1578 }
1579 
1580 // Recompute each UberSet weight after changing unit weights.
computeUberWeights(std::vector<UberRegSet> & UberSets,CodeGenRegBank & RegBank)1581 static void computeUberWeights(std::vector<UberRegSet> &UberSets,
1582                                CodeGenRegBank &RegBank) {
1583   // Skip the first unallocatable set.
1584   for (std::vector<UberRegSet>::iterator I = std::next(UberSets.begin()),
1585          E = UberSets.end(); I != E; ++I) {
1586 
1587     // Initialize all unit weights in this set, and remember the max units/reg.
1588     const CodeGenRegister *Reg = nullptr;
1589     unsigned MaxWeight = 0, Weight = 0;
1590     for (RegUnitIterator UnitI(I->Regs); UnitI.isValid(); ++UnitI) {
1591       if (Reg != UnitI.getReg()) {
1592         if (Weight > MaxWeight)
1593           MaxWeight = Weight;
1594         Reg = UnitI.getReg();
1595         Weight = 0;
1596       }
1597       if (!RegBank.getRegUnit(*UnitI).Artificial) {
1598         unsigned UWeight = RegBank.getRegUnit(*UnitI).Weight;
1599         if (!UWeight) {
1600           UWeight = 1;
1601           RegBank.increaseRegUnitWeight(*UnitI, UWeight);
1602         }
1603         Weight += UWeight;
1604       }
1605     }
1606     if (Weight > MaxWeight)
1607       MaxWeight = Weight;
1608     if (I->Weight != MaxWeight) {
1609       LLVM_DEBUG(dbgs() << "UberSet " << I - UberSets.begin() << " Weight "
1610                         << MaxWeight;
1611                  for (auto &Unit
1612                       : I->Regs) dbgs()
1613                  << " " << Unit->getName();
1614                  dbgs() << "\n");
1615       // Update the set weight.
1616       I->Weight = MaxWeight;
1617     }
1618 
1619     // Find singular determinants.
1620     for (const auto R : I->Regs) {
1621       if (R->getRegUnits().count() == 1 && R->getWeight(RegBank) == I->Weight) {
1622         I->SingularDeterminants |= R->getRegUnits();
1623       }
1624     }
1625   }
1626 }
1627 
1628 // normalizeWeight is a computeRegUnitWeights helper that adjusts the weight of
1629 // a register and its subregisters so that they have the same weight as their
1630 // UberSet. Self-recursion processes the subregister tree in postorder so
1631 // subregisters are normalized first.
1632 //
1633 // Side effects:
1634 // - creates new adopted register units
1635 // - causes superregisters to inherit adopted units
1636 // - increases the weight of "singular" units
1637 // - induces recomputation of UberWeights.
normalizeWeight(CodeGenRegister * Reg,std::vector<UberRegSet> & UberSets,std::vector<UberRegSet * > & RegSets,BitVector & NormalRegs,CodeGenRegister::RegUnitList & NormalUnits,CodeGenRegBank & RegBank)1638 static bool normalizeWeight(CodeGenRegister *Reg,
1639                             std::vector<UberRegSet> &UberSets,
1640                             std::vector<UberRegSet*> &RegSets,
1641                             BitVector &NormalRegs,
1642                             CodeGenRegister::RegUnitList &NormalUnits,
1643                             CodeGenRegBank &RegBank) {
1644   NormalRegs.resize(std::max(Reg->EnumValue + 1, NormalRegs.size()));
1645   if (NormalRegs.test(Reg->EnumValue))
1646     return false;
1647   NormalRegs.set(Reg->EnumValue);
1648 
1649   bool Changed = false;
1650   const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
1651   for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(),
1652          SRE = SRM.end(); SRI != SRE; ++SRI) {
1653     if (SRI->second == Reg)
1654       continue; // self-cycles happen
1655 
1656     Changed |= normalizeWeight(SRI->second, UberSets, RegSets,
1657                                NormalRegs, NormalUnits, RegBank);
1658   }
1659   // Postorder register normalization.
1660 
1661   // Inherit register units newly adopted by subregisters.
1662   if (Reg->inheritRegUnits(RegBank))
1663     computeUberWeights(UberSets, RegBank);
1664 
1665   // Check if this register is too skinny for its UberRegSet.
1666   UberRegSet *UberSet = RegSets[RegBank.getRegIndex(Reg)];
1667 
1668   unsigned RegWeight = Reg->getWeight(RegBank);
1669   if (UberSet->Weight > RegWeight) {
1670     // A register unit's weight can be adjusted only if it is the singular unit
1671     // for this register, has not been used to normalize a subregister's set,
1672     // and has not already been used to singularly determine this UberRegSet.
1673     unsigned AdjustUnit = *Reg->getRegUnits().begin();
1674     if (Reg->getRegUnits().count() != 1
1675         || hasRegUnit(NormalUnits, AdjustUnit)
1676         || hasRegUnit(UberSet->SingularDeterminants, AdjustUnit)) {
1677       // We don't have an adjustable unit, so adopt a new one.
1678       AdjustUnit = RegBank.newRegUnit(UberSet->Weight - RegWeight);
1679       Reg->adoptRegUnit(AdjustUnit);
1680       // Adopting a unit does not immediately require recomputing set weights.
1681     }
1682     else {
1683       // Adjust the existing single unit.
1684       if (!RegBank.getRegUnit(AdjustUnit).Artificial)
1685         RegBank.increaseRegUnitWeight(AdjustUnit, UberSet->Weight - RegWeight);
1686       // The unit may be shared among sets and registers within this set.
1687       computeUberWeights(UberSets, RegBank);
1688     }
1689     Changed = true;
1690   }
1691 
1692   // Mark these units normalized so superregisters can't change their weights.
1693   NormalUnits |= Reg->getRegUnits();
1694 
1695   return Changed;
1696 }
1697 
1698 // Compute a weight for each register unit created during getSubRegs.
1699 //
1700 // The goal is that two registers in the same class will have the same weight,
1701 // where each register's weight is defined as sum of its units' weights.
computeRegUnitWeights()1702 void CodeGenRegBank::computeRegUnitWeights() {
1703   std::vector<UberRegSet> UberSets;
1704   std::vector<UberRegSet*> RegSets(Registers.size());
1705   computeUberSets(UberSets, RegSets, *this);
1706   // UberSets and RegSets are now immutable.
1707 
1708   computeUberWeights(UberSets, *this);
1709 
1710   // Iterate over each Register, normalizing the unit weights until reaching
1711   // a fix point.
1712   unsigned NumIters = 0;
1713   for (bool Changed = true; Changed; ++NumIters) {
1714     assert(NumIters <= NumNativeRegUnits && "Runaway register unit weights");
1715     Changed = false;
1716     for (auto &Reg : Registers) {
1717       CodeGenRegister::RegUnitList NormalUnits;
1718       BitVector NormalRegs;
1719       Changed |= normalizeWeight(&Reg, UberSets, RegSets, NormalRegs,
1720                                  NormalUnits, *this);
1721     }
1722   }
1723 }
1724 
1725 // Find a set in UniqueSets with the same elements as Set.
1726 // Return an iterator into UniqueSets.
1727 static std::vector<RegUnitSet>::const_iterator
findRegUnitSet(const std::vector<RegUnitSet> & UniqueSets,const RegUnitSet & Set)1728 findRegUnitSet(const std::vector<RegUnitSet> &UniqueSets,
1729                const RegUnitSet &Set) {
1730   std::vector<RegUnitSet>::const_iterator
1731     I = UniqueSets.begin(), E = UniqueSets.end();
1732   for(;I != E; ++I) {
1733     if (I->Units == Set.Units)
1734       break;
1735   }
1736   return I;
1737 }
1738 
1739 // Return true if the RUSubSet is a subset of RUSuperSet.
isRegUnitSubSet(const std::vector<unsigned> & RUSubSet,const std::vector<unsigned> & RUSuperSet)1740 static bool isRegUnitSubSet(const std::vector<unsigned> &RUSubSet,
1741                             const std::vector<unsigned> &RUSuperSet) {
1742   return std::includes(RUSuperSet.begin(), RUSuperSet.end(),
1743                        RUSubSet.begin(), RUSubSet.end());
1744 }
1745 
1746 /// Iteratively prune unit sets. Prune subsets that are close to the superset,
1747 /// but with one or two registers removed. We occasionally have registers like
1748 /// APSR and PC thrown in with the general registers. We also see many
1749 /// special-purpose register subsets, such as tail-call and Thumb
1750 /// encodings. Generating all possible overlapping sets is combinatorial and
1751 /// overkill for modeling pressure. Ideally we could fix this statically in
1752 /// tablegen by (1) having the target define register classes that only include
1753 /// the allocatable registers and marking other classes as non-allocatable and
1754 /// (2) having a way to mark special purpose classes as "don't-care" classes for
1755 /// the purpose of pressure.  However, we make an attempt to handle targets that
1756 /// are not nicely defined by merging nearly identical register unit sets
1757 /// statically. This generates smaller tables. Then, dynamically, we adjust the
1758 /// set limit by filtering the reserved registers.
1759 ///
1760 /// Merge sets only if the units have the same weight. For example, on ARM,
1761 /// Q-tuples with ssub index 0 include all S regs but also include D16+. We
1762 /// should not expand the S set to include D regs.
pruneUnitSets()1763 void CodeGenRegBank::pruneUnitSets() {
1764   assert(RegClassUnitSets.empty() && "this invalidates RegClassUnitSets");
1765 
1766   // Form an equivalence class of UnitSets with no significant difference.
1767   std::vector<unsigned> SuperSetIDs;
1768   for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size();
1769        SubIdx != EndIdx; ++SubIdx) {
1770     const RegUnitSet &SubSet = RegUnitSets[SubIdx];
1771     unsigned SuperIdx = 0;
1772     for (; SuperIdx != EndIdx; ++SuperIdx) {
1773       if (SuperIdx == SubIdx)
1774         continue;
1775 
1776       unsigned UnitWeight = RegUnits[SubSet.Units[0]].Weight;
1777       const RegUnitSet &SuperSet = RegUnitSets[SuperIdx];
1778       if (isRegUnitSubSet(SubSet.Units, SuperSet.Units)
1779           && (SubSet.Units.size() + 3 > SuperSet.Units.size())
1780           && UnitWeight == RegUnits[SuperSet.Units[0]].Weight
1781           && UnitWeight == RegUnits[SuperSet.Units.back()].Weight) {
1782         LLVM_DEBUG(dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdx
1783                           << "\n");
1784         // We can pick any of the set names for the merged set. Go for the
1785         // shortest one to avoid picking the name of one of the classes that are
1786         // artificially created by tablegen. So "FPR128_lo" instead of
1787         // "QQQQ_with_qsub3_in_FPR128_lo".
1788         if (RegUnitSets[SubIdx].Name.size() < RegUnitSets[SuperIdx].Name.size())
1789           RegUnitSets[SuperIdx].Name = RegUnitSets[SubIdx].Name;
1790         break;
1791       }
1792     }
1793     if (SuperIdx == EndIdx)
1794       SuperSetIDs.push_back(SubIdx);
1795   }
1796   // Populate PrunedUnitSets with each equivalence class's superset.
1797   std::vector<RegUnitSet> PrunedUnitSets(SuperSetIDs.size());
1798   for (unsigned i = 0, e = SuperSetIDs.size(); i != e; ++i) {
1799     unsigned SuperIdx = SuperSetIDs[i];
1800     PrunedUnitSets[i].Name = RegUnitSets[SuperIdx].Name;
1801     PrunedUnitSets[i].Units.swap(RegUnitSets[SuperIdx].Units);
1802   }
1803   RegUnitSets.swap(PrunedUnitSets);
1804 }
1805 
1806 // Create a RegUnitSet for each RegClass that contains all units in the class
1807 // including adopted units that are necessary to model register pressure. Then
1808 // iteratively compute RegUnitSets such that the union of any two overlapping
1809 // RegUnitSets is repreresented.
1810 //
1811 // RegisterInfoEmitter will map each RegClass to its RegUnitClass and any
1812 // RegUnitSet that is a superset of that RegUnitClass.
computeRegUnitSets()1813 void CodeGenRegBank::computeRegUnitSets() {
1814   assert(RegUnitSets.empty() && "dirty RegUnitSets");
1815 
1816   // Compute a unique RegUnitSet for each RegClass.
1817   auto &RegClasses = getRegClasses();
1818   for (auto &RC : RegClasses) {
1819     if (!RC.Allocatable || RC.Artificial)
1820       continue;
1821 
1822     // Speculatively grow the RegUnitSets to hold the new set.
1823     RegUnitSets.resize(RegUnitSets.size() + 1);
1824     RegUnitSets.back().Name = RC.getName();
1825 
1826     // Compute a sorted list of units in this class.
1827     RC.buildRegUnitSet(*this, RegUnitSets.back().Units);
1828 
1829     // Find an existing RegUnitSet.
1830     std::vector<RegUnitSet>::const_iterator SetI =
1831       findRegUnitSet(RegUnitSets, RegUnitSets.back());
1832     if (SetI != std::prev(RegUnitSets.end()))
1833       RegUnitSets.pop_back();
1834   }
1835 
1836   LLVM_DEBUG(dbgs() << "\nBefore pruning:\n"; for (unsigned USIdx = 0,
1837                                                    USEnd = RegUnitSets.size();
1838                                                    USIdx < USEnd; ++USIdx) {
1839     dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name << ":";
1840     for (auto &U : RegUnitSets[USIdx].Units)
1841       printRegUnitName(U);
1842     dbgs() << "\n";
1843   });
1844 
1845   // Iteratively prune unit sets.
1846   pruneUnitSets();
1847 
1848   LLVM_DEBUG(dbgs() << "\nBefore union:\n"; for (unsigned USIdx = 0,
1849                                                  USEnd = RegUnitSets.size();
1850                                                  USIdx < USEnd; ++USIdx) {
1851     dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name << ":";
1852     for (auto &U : RegUnitSets[USIdx].Units)
1853       printRegUnitName(U);
1854     dbgs() << "\n";
1855   } dbgs() << "\nUnion sets:\n");
1856 
1857   // Iterate over all unit sets, including new ones added by this loop.
1858   unsigned NumRegUnitSubSets = RegUnitSets.size();
1859   for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) {
1860     // In theory, this is combinatorial. In practice, it needs to be bounded
1861     // by a small number of sets for regpressure to be efficient.
1862     // If the assert is hit, we need to implement pruning.
1863     assert(Idx < (2*NumRegUnitSubSets) && "runaway unit set inference");
1864 
1865     // Compare new sets with all original classes.
1866     for (unsigned SearchIdx = (Idx >= NumRegUnitSubSets) ? 0 : Idx+1;
1867          SearchIdx != EndIdx; ++SearchIdx) {
1868       std::set<unsigned> Intersection;
1869       std::set_intersection(RegUnitSets[Idx].Units.begin(),
1870                             RegUnitSets[Idx].Units.end(),
1871                             RegUnitSets[SearchIdx].Units.begin(),
1872                             RegUnitSets[SearchIdx].Units.end(),
1873                             std::inserter(Intersection, Intersection.begin()));
1874       if (Intersection.empty())
1875         continue;
1876 
1877       // Speculatively grow the RegUnitSets to hold the new set.
1878       RegUnitSets.resize(RegUnitSets.size() + 1);
1879       RegUnitSets.back().Name =
1880         RegUnitSets[Idx].Name + "+" + RegUnitSets[SearchIdx].Name;
1881 
1882       std::set_union(RegUnitSets[Idx].Units.begin(),
1883                      RegUnitSets[Idx].Units.end(),
1884                      RegUnitSets[SearchIdx].Units.begin(),
1885                      RegUnitSets[SearchIdx].Units.end(),
1886                      std::inserter(RegUnitSets.back().Units,
1887                                    RegUnitSets.back().Units.begin()));
1888 
1889       // Find an existing RegUnitSet, or add the union to the unique sets.
1890       std::vector<RegUnitSet>::const_iterator SetI =
1891         findRegUnitSet(RegUnitSets, RegUnitSets.back());
1892       if (SetI != std::prev(RegUnitSets.end()))
1893         RegUnitSets.pop_back();
1894       else {
1895         LLVM_DEBUG(dbgs() << "UnitSet " << RegUnitSets.size() - 1 << " "
1896                           << RegUnitSets.back().Name << ":";
1897                    for (auto &U
1898                         : RegUnitSets.back().Units) printRegUnitName(U);
1899                    dbgs() << "\n";);
1900       }
1901     }
1902   }
1903 
1904   // Iteratively prune unit sets after inferring supersets.
1905   pruneUnitSets();
1906 
1907   LLVM_DEBUG(
1908       dbgs() << "\n"; for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
1909                            USIdx < USEnd; ++USIdx) {
1910         dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name << ":";
1911         for (auto &U : RegUnitSets[USIdx].Units)
1912           printRegUnitName(U);
1913         dbgs() << "\n";
1914       });
1915 
1916   // For each register class, list the UnitSets that are supersets.
1917   RegClassUnitSets.resize(RegClasses.size());
1918   int RCIdx = -1;
1919   for (auto &RC : RegClasses) {
1920     ++RCIdx;
1921     if (!RC.Allocatable)
1922       continue;
1923 
1924     // Recompute the sorted list of units in this class.
1925     std::vector<unsigned> RCRegUnits;
1926     RC.buildRegUnitSet(*this, RCRegUnits);
1927 
1928     // Don't increase pressure for unallocatable regclasses.
1929     if (RCRegUnits.empty())
1930       continue;
1931 
1932     LLVM_DEBUG(dbgs() << "RC " << RC.getName() << " Units: \n";
1933                for (auto U
1934                     : RCRegUnits) printRegUnitName(U);
1935                dbgs() << "\n  UnitSetIDs:");
1936 
1937     // Find all supersets.
1938     for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
1939          USIdx != USEnd; ++USIdx) {
1940       if (isRegUnitSubSet(RCRegUnits, RegUnitSets[USIdx].Units)) {
1941         LLVM_DEBUG(dbgs() << " " << USIdx);
1942         RegClassUnitSets[RCIdx].push_back(USIdx);
1943       }
1944     }
1945     LLVM_DEBUG(dbgs() << "\n");
1946     assert(!RegClassUnitSets[RCIdx].empty() && "missing unit set for regclass");
1947   }
1948 
1949   // For each register unit, ensure that we have the list of UnitSets that
1950   // contain the unit. Normally, this matches an existing list of UnitSets for a
1951   // register class. If not, we create a new entry in RegClassUnitSets as a
1952   // "fake" register class.
1953   for (unsigned UnitIdx = 0, UnitEnd = NumNativeRegUnits;
1954        UnitIdx < UnitEnd; ++UnitIdx) {
1955     std::vector<unsigned> RUSets;
1956     for (unsigned i = 0, e = RegUnitSets.size(); i != e; ++i) {
1957       RegUnitSet &RUSet = RegUnitSets[i];
1958       if (!is_contained(RUSet.Units, UnitIdx))
1959         continue;
1960       RUSets.push_back(i);
1961     }
1962     unsigned RCUnitSetsIdx = 0;
1963     for (unsigned e = RegClassUnitSets.size();
1964          RCUnitSetsIdx != e; ++RCUnitSetsIdx) {
1965       if (RegClassUnitSets[RCUnitSetsIdx] == RUSets) {
1966         break;
1967       }
1968     }
1969     RegUnits[UnitIdx].RegClassUnitSetsIdx = RCUnitSetsIdx;
1970     if (RCUnitSetsIdx == RegClassUnitSets.size()) {
1971       // Create a new list of UnitSets as a "fake" register class.
1972       RegClassUnitSets.resize(RCUnitSetsIdx + 1);
1973       RegClassUnitSets[RCUnitSetsIdx].swap(RUSets);
1974     }
1975   }
1976 }
1977 
computeRegUnitLaneMasks()1978 void CodeGenRegBank::computeRegUnitLaneMasks() {
1979   for (auto &Register : Registers) {
1980     // Create an initial lane mask for all register units.
1981     const auto &RegUnits = Register.getRegUnits();
1982     CodeGenRegister::RegUnitLaneMaskList
1983         RegUnitLaneMasks(RegUnits.count(), LaneBitmask::getNone());
1984     // Iterate through SubRegisters.
1985     typedef CodeGenRegister::SubRegMap SubRegMap;
1986     const SubRegMap &SubRegs = Register.getSubRegs();
1987     for (SubRegMap::const_iterator S = SubRegs.begin(),
1988          SE = SubRegs.end(); S != SE; ++S) {
1989       CodeGenRegister *SubReg = S->second;
1990       // Ignore non-leaf subregisters, their lane masks are fully covered by
1991       // the leaf subregisters anyway.
1992       if (!SubReg->getSubRegs().empty())
1993         continue;
1994       CodeGenSubRegIndex *SubRegIndex = S->first;
1995       const CodeGenRegister *SubRegister = S->second;
1996       LaneBitmask LaneMask = SubRegIndex->LaneMask;
1997       // Distribute LaneMask to Register Units touched.
1998       for (unsigned SUI : SubRegister->getRegUnits()) {
1999         bool Found = false;
2000         unsigned u = 0;
2001         for (unsigned RU : RegUnits) {
2002           if (SUI == RU) {
2003             RegUnitLaneMasks[u] |= LaneMask;
2004             assert(!Found);
2005             Found = true;
2006           }
2007           ++u;
2008         }
2009         (void)Found;
2010         assert(Found);
2011       }
2012     }
2013     Register.setRegUnitLaneMasks(RegUnitLaneMasks);
2014   }
2015 }
2016 
computeDerivedInfo()2017 void CodeGenRegBank::computeDerivedInfo() {
2018   computeComposites();
2019   computeSubRegLaneMasks();
2020 
2021   // Compute a weight for each register unit created during getSubRegs.
2022   // This may create adopted register units (with unit # >= NumNativeRegUnits).
2023   computeRegUnitWeights();
2024 
2025   // Compute a unique set of RegUnitSets. One for each RegClass and inferred
2026   // supersets for the union of overlapping sets.
2027   computeRegUnitSets();
2028 
2029   computeRegUnitLaneMasks();
2030 
2031   // Compute register class HasDisjunctSubRegs/CoveredBySubRegs flag.
2032   for (CodeGenRegisterClass &RC : RegClasses) {
2033     RC.HasDisjunctSubRegs = false;
2034     RC.CoveredBySubRegs = true;
2035     for (const CodeGenRegister *Reg : RC.getMembers()) {
2036       RC.HasDisjunctSubRegs |= Reg->HasDisjunctSubRegs;
2037       RC.CoveredBySubRegs &= Reg->CoveredBySubRegs;
2038     }
2039   }
2040 
2041   // Get the weight of each set.
2042   for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx)
2043     RegUnitSets[Idx].Weight = getRegUnitSetWeight(RegUnitSets[Idx].Units);
2044 
2045   // Find the order of each set.
2046   RegUnitSetOrder.reserve(RegUnitSets.size());
2047   for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx)
2048     RegUnitSetOrder.push_back(Idx);
2049 
2050   std::stable_sort(RegUnitSetOrder.begin(), RegUnitSetOrder.end(),
2051                    [this](unsigned ID1, unsigned ID2) {
2052     return getRegPressureSet(ID1).Units.size() <
2053            getRegPressureSet(ID2).Units.size();
2054   });
2055   for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) {
2056     RegUnitSets[RegUnitSetOrder[Idx]].Order = Idx;
2057   }
2058 }
2059 
2060 //
2061 // Synthesize missing register class intersections.
2062 //
2063 // Make sure that sub-classes of RC exists such that getCommonSubClass(RC, X)
2064 // returns a maximal register class for all X.
2065 //
inferCommonSubClass(CodeGenRegisterClass * RC)2066 void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
2067   assert(!RegClasses.empty());
2068   // Stash the iterator to the last element so that this loop doesn't visit
2069   // elements added by the getOrCreateSubClass call within it.
2070   for (auto I = RegClasses.begin(), E = std::prev(RegClasses.end());
2071        I != std::next(E); ++I) {
2072     CodeGenRegisterClass *RC1 = RC;
2073     CodeGenRegisterClass *RC2 = &*I;
2074     if (RC1 == RC2)
2075       continue;
2076 
2077     // Compute the set intersection of RC1 and RC2.
2078     const CodeGenRegister::Vec &Memb1 = RC1->getMembers();
2079     const CodeGenRegister::Vec &Memb2 = RC2->getMembers();
2080     CodeGenRegister::Vec Intersection;
2081     std::set_intersection(
2082         Memb1.begin(), Memb1.end(), Memb2.begin(), Memb2.end(),
2083         std::inserter(Intersection, Intersection.begin()), deref<llvm::less>());
2084 
2085     // Skip disjoint class pairs.
2086     if (Intersection.empty())
2087       continue;
2088 
2089     // If RC1 and RC2 have different spill sizes or alignments, use the
2090     // stricter one for sub-classing.  If they are equal, prefer RC1.
2091     if (RC2->RSI.hasStricterSpillThan(RC1->RSI))
2092       std::swap(RC1, RC2);
2093 
2094     getOrCreateSubClass(RC1, &Intersection,
2095                         RC1->getName() + "_and_" + RC2->getName());
2096   }
2097 }
2098 
2099 //
2100 // Synthesize missing sub-classes for getSubClassWithSubReg().
2101 //
2102 // Make sure that the set of registers in RC with a given SubIdx sub-register
2103 // form a register class.  Update RC->SubClassWithSubReg.
2104 //
inferSubClassWithSubReg(CodeGenRegisterClass * RC)2105 void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
2106   // Map SubRegIndex to set of registers in RC supporting that SubRegIndex.
2107   typedef std::map<const CodeGenSubRegIndex *, CodeGenRegister::Vec,
2108                    deref<llvm::less>> SubReg2SetMap;
2109 
2110   // Compute the set of registers supporting each SubRegIndex.
2111   SubReg2SetMap SRSets;
2112   for (const auto R : RC->getMembers()) {
2113     if (R->Artificial)
2114       continue;
2115     const CodeGenRegister::SubRegMap &SRM = R->getSubRegs();
2116     for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
2117          E = SRM.end(); I != E; ++I) {
2118       if (!I->first->Artificial)
2119         SRSets[I->first].push_back(R);
2120     }
2121   }
2122 
2123   for (auto I : SRSets)
2124     sortAndUniqueRegisters(I.second);
2125 
2126   // Find matching classes for all SRSets entries.  Iterate in SubRegIndex
2127   // numerical order to visit synthetic indices last.
2128   for (const auto &SubIdx : SubRegIndices) {
2129     if (SubIdx.Artificial)
2130       continue;
2131     SubReg2SetMap::const_iterator I = SRSets.find(&SubIdx);
2132     // Unsupported SubRegIndex. Skip it.
2133     if (I == SRSets.end())
2134       continue;
2135     // In most cases, all RC registers support the SubRegIndex.
2136     if (I->second.size() == RC->getMembers().size()) {
2137       RC->setSubClassWithSubReg(&SubIdx, RC);
2138       continue;
2139     }
2140     // This is a real subset.  See if we have a matching class.
2141     CodeGenRegisterClass *SubRC =
2142       getOrCreateSubClass(RC, &I->second,
2143                           RC->getName() + "_with_" + I->first->getName());
2144     RC->setSubClassWithSubReg(&SubIdx, SubRC);
2145   }
2146 }
2147 
2148 //
2149 // Synthesize missing sub-classes of RC for getMatchingSuperRegClass().
2150 //
2151 // Create sub-classes of RC such that getMatchingSuperRegClass(RC, SubIdx, X)
2152 // has a maximal result for any SubIdx and any X >= FirstSubRegRC.
2153 //
2154 
inferMatchingSuperRegClass(CodeGenRegisterClass * RC,std::list<CodeGenRegisterClass>::iterator FirstSubRegRC)2155 void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
2156                                                 std::list<CodeGenRegisterClass>::iterator FirstSubRegRC) {
2157   SmallVector<std::pair<const CodeGenRegister*,
2158                         const CodeGenRegister*>, 16> SSPairs;
2159   BitVector TopoSigs(getNumTopoSigs());
2160 
2161   // Iterate in SubRegIndex numerical order to visit synthetic indices last.
2162   for (auto &SubIdx : SubRegIndices) {
2163     // Skip indexes that aren't fully supported by RC's registers. This was
2164     // computed by inferSubClassWithSubReg() above which should have been
2165     // called first.
2166     if (RC->getSubClassWithSubReg(&SubIdx) != RC)
2167       continue;
2168 
2169     // Build list of (Super, Sub) pairs for this SubIdx.
2170     SSPairs.clear();
2171     TopoSigs.reset();
2172     for (const auto Super : RC->getMembers()) {
2173       const CodeGenRegister *Sub = Super->getSubRegs().find(&SubIdx)->second;
2174       assert(Sub && "Missing sub-register");
2175       SSPairs.push_back(std::make_pair(Super, Sub));
2176       TopoSigs.set(Sub->getTopoSig());
2177     }
2178 
2179     // Iterate over sub-register class candidates.  Ignore classes created by
2180     // this loop. They will never be useful.
2181     // Store an iterator to the last element (not end) so that this loop doesn't
2182     // visit newly inserted elements.
2183     assert(!RegClasses.empty());
2184     for (auto I = FirstSubRegRC, E = std::prev(RegClasses.end());
2185          I != std::next(E); ++I) {
2186       CodeGenRegisterClass &SubRC = *I;
2187       if (SubRC.Artificial)
2188         continue;
2189       // Topological shortcut: SubRC members have the wrong shape.
2190       if (!TopoSigs.anyCommon(SubRC.getTopoSigs()))
2191         continue;
2192       // Compute the subset of RC that maps into SubRC.
2193       CodeGenRegister::Vec SubSetVec;
2194       for (unsigned i = 0, e = SSPairs.size(); i != e; ++i)
2195         if (SubRC.contains(SSPairs[i].second))
2196           SubSetVec.push_back(SSPairs[i].first);
2197 
2198       if (SubSetVec.empty())
2199         continue;
2200 
2201       // RC injects completely into SubRC.
2202       sortAndUniqueRegisters(SubSetVec);
2203       if (SubSetVec.size() == SSPairs.size()) {
2204         SubRC.addSuperRegClass(&SubIdx, RC);
2205         continue;
2206       }
2207 
2208       // Only a subset of RC maps into SubRC. Make sure it is represented by a
2209       // class.
2210       getOrCreateSubClass(RC, &SubSetVec, RC->getName() + "_with_" +
2211                                           SubIdx.getName() + "_in_" +
2212                                           SubRC.getName());
2213     }
2214   }
2215 }
2216 
2217 //
2218 // Infer missing register classes.
2219 //
computeInferredRegisterClasses()2220 void CodeGenRegBank::computeInferredRegisterClasses() {
2221   assert(!RegClasses.empty());
2222   // When this function is called, the register classes have not been sorted
2223   // and assigned EnumValues yet.  That means getSubClasses(),
2224   // getSuperClasses(), and hasSubClass() functions are defunct.
2225 
2226   // Use one-before-the-end so it doesn't move forward when new elements are
2227   // added.
2228   auto FirstNewRC = std::prev(RegClasses.end());
2229 
2230   // Visit all register classes, including the ones being added by the loop.
2231   // Watch out for iterator invalidation here.
2232   for (auto I = RegClasses.begin(), E = RegClasses.end(); I != E; ++I) {
2233     CodeGenRegisterClass *RC = &*I;
2234     if (RC->Artificial)
2235       continue;
2236 
2237     // Synthesize answers for getSubClassWithSubReg().
2238     inferSubClassWithSubReg(RC);
2239 
2240     // Synthesize answers for getCommonSubClass().
2241     inferCommonSubClass(RC);
2242 
2243     // Synthesize answers for getMatchingSuperRegClass().
2244     inferMatchingSuperRegClass(RC);
2245 
2246     // New register classes are created while this loop is running, and we need
2247     // to visit all of them.  I  particular, inferMatchingSuperRegClass needs
2248     // to match old super-register classes with sub-register classes created
2249     // after inferMatchingSuperRegClass was called.  At this point,
2250     // inferMatchingSuperRegClass has checked SuperRC = [0..rci] with SubRC =
2251     // [0..FirstNewRC).  We need to cover SubRC = [FirstNewRC..rci].
2252     if (I == FirstNewRC) {
2253       auto NextNewRC = std::prev(RegClasses.end());
2254       for (auto I2 = RegClasses.begin(), E2 = std::next(FirstNewRC); I2 != E2;
2255            ++I2)
2256         inferMatchingSuperRegClass(&*I2, E2);
2257       FirstNewRC = NextNewRC;
2258     }
2259   }
2260 }
2261 
2262 /// getRegisterClassForRegister - Find the register class that contains the
2263 /// specified physical register.  If the register is not in a register class,
2264 /// return null. If the register is in multiple classes, and the classes have a
2265 /// superset-subset relationship and the same set of types, return the
2266 /// superclass.  Otherwise return null.
2267 const CodeGenRegisterClass*
getRegClassForRegister(Record * R)2268 CodeGenRegBank::getRegClassForRegister(Record *R) {
2269   const CodeGenRegister *Reg = getReg(R);
2270   const CodeGenRegisterClass *FoundRC = nullptr;
2271   for (const auto &RC : getRegClasses()) {
2272     if (!RC.contains(Reg))
2273       continue;
2274 
2275     // If this is the first class that contains the register,
2276     // make a note of it and go on to the next class.
2277     if (!FoundRC) {
2278       FoundRC = &RC;
2279       continue;
2280     }
2281 
2282     // If a register's classes have different types, return null.
2283     if (RC.getValueTypes() != FoundRC->getValueTypes())
2284       return nullptr;
2285 
2286     // Check to see if the previously found class that contains
2287     // the register is a subclass of the current class. If so,
2288     // prefer the superclass.
2289     if (RC.hasSubClass(FoundRC)) {
2290       FoundRC = &RC;
2291       continue;
2292     }
2293 
2294     // Check to see if the previously found class that contains
2295     // the register is a superclass of the current class. If so,
2296     // prefer the superclass.
2297     if (FoundRC->hasSubClass(&RC))
2298       continue;
2299 
2300     // Multiple classes, and neither is a superclass of the other.
2301     // Return null.
2302     return nullptr;
2303   }
2304   return FoundRC;
2305 }
2306 
computeCoveredRegisters(ArrayRef<Record * > Regs)2307 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
2308   SetVector<const CodeGenRegister*> Set;
2309 
2310   // First add Regs with all sub-registers.
2311   for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2312     CodeGenRegister *Reg = getReg(Regs[i]);
2313     if (Set.insert(Reg))
2314       // Reg is new, add all sub-registers.
2315       // The pre-ordering is not important here.
2316       Reg->addSubRegsPreOrder(Set, *this);
2317   }
2318 
2319   // Second, find all super-registers that are completely covered by the set.
2320   for (unsigned i = 0; i != Set.size(); ++i) {
2321     const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs();
2322     for (unsigned j = 0, e = SR.size(); j != e; ++j) {
2323       const CodeGenRegister *Super = SR[j];
2324       if (!Super->CoveredBySubRegs || Set.count(Super))
2325         continue;
2326       // This new super-register is covered by its sub-registers.
2327       bool AllSubsInSet = true;
2328       const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs();
2329       for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
2330              E = SRM.end(); I != E; ++I)
2331         if (!Set.count(I->second)) {
2332           AllSubsInSet = false;
2333           break;
2334         }
2335       // All sub-registers in Set, add Super as well.
2336       // We will visit Super later to recheck its super-registers.
2337       if (AllSubsInSet)
2338         Set.insert(Super);
2339     }
2340   }
2341 
2342   // Convert to BitVector.
2343   BitVector BV(Registers.size() + 1);
2344   for (unsigned i = 0, e = Set.size(); i != e; ++i)
2345     BV.set(Set[i]->EnumValue);
2346   return BV;
2347 }
2348 
printRegUnitName(unsigned Unit) const2349 void CodeGenRegBank::printRegUnitName(unsigned Unit) const {
2350   if (Unit < NumNativeRegUnits)
2351     dbgs() << ' ' << RegUnits[Unit].Roots[0]->getName();
2352   else
2353     dbgs() << " #" << Unit;
2354 }
2355