1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines wrappers for the Target class and related global 11 // functionality. This makes it easier to access the data and provides a single 12 // place that needs to check it for validity. All of these classes abort 13 // on error conditions. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef LLVM_UTILS_TABLEGEN_CODEGENTARGET_H 18 #define LLVM_UTILS_TABLEGEN_CODEGENTARGET_H 19 20 #include "CodeGenHwModes.h" 21 #include "CodeGenInstruction.h" 22 #include "CodeGenRegisters.h" 23 #include "InfoByHwMode.h" 24 #include "SDNodeProperties.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include "llvm/TableGen/Record.h" 27 #include <algorithm> 28 29 namespace llvm { 30 31 struct CodeGenRegister; 32 class CodeGenSchedModels; 33 class CodeGenTarget; 34 35 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen 36 /// record corresponds to. 37 MVT::SimpleValueType getValueType(Record *Rec); 38 39 StringRef getName(MVT::SimpleValueType T); 40 StringRef getEnumName(MVT::SimpleValueType T); 41 42 /// getQualifiedName - Return the name of the specified record, with a 43 /// namespace qualifier if the record contains one. 44 std::string getQualifiedName(const Record *R); 45 46 /// CodeGenTarget - This class corresponds to the Target class in the .td files. 47 /// 48 class CodeGenTarget { 49 RecordKeeper &Records; 50 Record *TargetRec; 51 52 mutable DenseMap<const Record*, 53 std::unique_ptr<CodeGenInstruction>> Instructions; 54 mutable std::unique_ptr<CodeGenRegBank> RegBank; 55 mutable std::vector<Record*> RegAltNameIndices; 56 mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes; 57 CodeGenHwModes CGH; 58 void ReadRegAltNameIndices() const; 59 void ReadInstructions() const; 60 void ReadLegalValueTypes() const; 61 62 mutable std::unique_ptr<CodeGenSchedModels> SchedModels; 63 64 mutable std::vector<const CodeGenInstruction*> InstrsByEnum; 65 mutable unsigned NumPseudoInstructions = 0; 66 public: 67 CodeGenTarget(RecordKeeper &Records); 68 ~CodeGenTarget(); 69 getTargetRecord()70 Record *getTargetRecord() const { return TargetRec; } 71 const StringRef getName() const; 72 73 /// getInstNamespace - Return the target-specific instruction namespace. 74 /// 75 StringRef getInstNamespace() const; 76 77 /// getInstructionSet - Return the InstructionSet object. 78 /// 79 Record *getInstructionSet() const; 80 81 /// getAllowRegisterRenaming - Return the AllowRegisterRenaming flag value for 82 /// this target. 83 /// 84 bool getAllowRegisterRenaming() const; 85 86 /// getAsmParser - Return the AssemblyParser definition for this target. 87 /// 88 Record *getAsmParser() const; 89 90 /// getAsmParserVariant - Return the AssmblyParserVariant definition for 91 /// this target. 92 /// 93 Record *getAsmParserVariant(unsigned i) const; 94 95 /// getAsmParserVariantCount - Return the AssmblyParserVariant definition 96 /// available for this target. 97 /// 98 unsigned getAsmParserVariantCount() const; 99 100 /// getAsmWriter - Return the AssemblyWriter definition for this target. 101 /// 102 Record *getAsmWriter() const; 103 104 /// getRegBank - Return the register bank description. 105 CodeGenRegBank &getRegBank() const; 106 107 /// getRegisterByName - If there is a register with the specific AsmName, 108 /// return it. 109 const CodeGenRegister *getRegisterByName(StringRef Name) const; 110 getRegAltNameIndices()111 const std::vector<Record*> &getRegAltNameIndices() const { 112 if (RegAltNameIndices.empty()) ReadRegAltNameIndices(); 113 return RegAltNameIndices; 114 } 115 getRegisterClass(Record * R)116 const CodeGenRegisterClass &getRegisterClass(Record *R) const { 117 return *getRegBank().getRegClass(R); 118 } 119 120 /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the 121 /// specified physical register. 122 std::vector<ValueTypeByHwMode> getRegisterVTs(Record *R) const; 123 getLegalValueTypes()124 ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const { 125 if (LegalValueTypes.empty()) 126 ReadLegalValueTypes(); 127 return LegalValueTypes; 128 } 129 130 CodeGenSchedModels &getSchedModels() const; 131 getHwModes()132 const CodeGenHwModes &getHwModes() const { return CGH; } 133 134 private: 135 DenseMap<const Record*, std::unique_ptr<CodeGenInstruction>> & getInstructions()136 getInstructions() const { 137 if (Instructions.empty()) ReadInstructions(); 138 return Instructions; 139 } 140 public: 141 getInstruction(const Record * InstRec)142 CodeGenInstruction &getInstruction(const Record *InstRec) const { 143 if (Instructions.empty()) ReadInstructions(); 144 auto I = Instructions.find(InstRec); 145 assert(I != Instructions.end() && "Not an instruction"); 146 return *I->second; 147 } 148 149 /// Returns the number of predefined instructions. 150 static unsigned getNumFixedInstructions(); 151 152 /// Returns the number of pseudo instructions. getNumPseudoInstructions()153 unsigned getNumPseudoInstructions() const { 154 if (InstrsByEnum.empty()) 155 ComputeInstrsByEnum(); 156 return NumPseudoInstructions; 157 } 158 159 /// Return all of the instructions defined by the target, ordered by their 160 /// enum value. 161 /// The following order of instructions is also guaranteed: 162 /// - fixed / generic instructions as declared in TargetOpcodes.def, in order; 163 /// - pseudo instructions in lexicographical order sorted by name; 164 /// - other instructions in lexicographical order sorted by name. getInstructionsByEnumValue()165 ArrayRef<const CodeGenInstruction *> getInstructionsByEnumValue() const { 166 if (InstrsByEnum.empty()) 167 ComputeInstrsByEnum(); 168 return InstrsByEnum; 169 } 170 171 typedef ArrayRef<const CodeGenInstruction *>::const_iterator inst_iterator; inst_begin()172 inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();} inst_end()173 inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); } 174 175 176 /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]? 177 /// 178 bool isLittleEndianEncoding() const; 179 180 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit 181 /// encodings, reverse the bit order of all instructions. 182 void reverseBitsForLittleEndianEncoding(); 183 184 /// guessInstructionProperties - should we just guess unset instruction 185 /// properties? 186 bool guessInstructionProperties() const; 187 188 private: 189 void ComputeInstrsByEnum() const; 190 }; 191 192 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern 193 /// tablegen class in TargetSelectionDAG.td 194 class ComplexPattern { 195 MVT::SimpleValueType Ty; 196 unsigned NumOperands; 197 std::string SelectFunc; 198 std::vector<Record*> RootNodes; 199 unsigned Properties; // Node properties 200 unsigned Complexity; 201 public: 202 ComplexPattern(Record *R); 203 getValueType()204 MVT::SimpleValueType getValueType() const { return Ty; } getNumOperands()205 unsigned getNumOperands() const { return NumOperands; } getSelectFunc()206 const std::string &getSelectFunc() const { return SelectFunc; } getRootNodes()207 const std::vector<Record*> &getRootNodes() const { 208 return RootNodes; 209 } hasProperty(enum SDNP Prop)210 bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); } getComplexity()211 unsigned getComplexity() const { return Complexity; } 212 }; 213 214 } // End llvm namespace 215 216 #endif 217