1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir_target_nvc0.h"
24
25 namespace nv50_ir {
26
getTargetNVC0(unsigned int chipset)27 Target *getTargetNVC0(unsigned int chipset)
28 {
29 return new TargetNVC0(chipset);
30 }
31
TargetNVC0(unsigned int card)32 TargetNVC0::TargetNVC0(unsigned int card) :
33 Target(card < 0x110, false, card >= 0xe4)
34 {
35 chipset = card;
36 initOpInfo();
37 }
38
39 // BULTINS / LIBRARY FUNCTIONS:
40
41 // lazyness -> will just hardcode everything for the time being
42
43 #include "lib/gf100.asm.h"
44 #include "lib/gk104.asm.h"
45 #include "lib/gk110.asm.h"
46
47 void
getBuiltinCode(const uint32_t ** code,uint32_t * size) const48 TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const
49 {
50 switch (chipset & ~0xf) {
51 case 0xe0:
52 if (chipset < NVISA_GK20A_CHIPSET) {
53 *code = (const uint32_t *)&gk104_builtin_code[0];
54 *size = sizeof(gk104_builtin_code);
55 break;
56 }
57 /* fall-through for GK20A */
58 case 0xf0:
59 case 0x100:
60 *code = (const uint32_t *)&gk110_builtin_code[0];
61 *size = sizeof(gk110_builtin_code);
62 break;
63 default:
64 *code = (const uint32_t *)&gf100_builtin_code[0];
65 *size = sizeof(gf100_builtin_code);
66 break;
67 }
68 }
69
70 uint32_t
getBuiltinOffset(int builtin) const71 TargetNVC0::getBuiltinOffset(int builtin) const
72 {
73 assert(builtin < NVC0_BUILTIN_COUNT);
74
75 switch (chipset & ~0xf) {
76 case 0xe0:
77 if (chipset < NVISA_GK20A_CHIPSET)
78 return gk104_builtin_offsets[builtin];
79 /* fall-through for GK20A */
80 case 0xf0:
81 case 0x100:
82 return gk110_builtin_offsets[builtin];
83 default:
84 return gf100_builtin_offsets[builtin];
85 }
86 }
87
88 struct opProperties
89 {
90 operation op;
91 unsigned int mNeg : 4;
92 unsigned int mAbs : 4;
93 unsigned int mNot : 4;
94 unsigned int mSat : 4;
95 unsigned int fConst : 3;
96 unsigned int fImmd : 4; // last bit indicates if full immediate is suppoted
97 };
98
99 static const struct opProperties _initProps[] =
100 {
101 // neg abs not sat c[] imm
102 { OP_ADD, 0x3, 0x3, 0x0, 0x8, 0x2, 0x2 | 0x8 },
103 { OP_SUB, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 | 0x8 },
104 { OP_MUL, 0x3, 0x0, 0x0, 0x8, 0x2, 0x2 | 0x8 },
105 { OP_MAX, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
106 { OP_MIN, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
107 { OP_MAD, 0x7, 0x0, 0x0, 0x8, 0x6, 0x2 }, // special c[] constraint
108 { OP_FMA, 0x7, 0x0, 0x0, 0x8, 0x6, 0x2 }, // keep the same as OP_MAD
109 { OP_SHLADD, 0x5, 0x0, 0x0, 0x0, 0x4, 0x6 },
110 { OP_MADSP, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
111 { OP_ABS, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
112 { OP_NEG, 0x0, 0x1, 0x0, 0x0, 0x1, 0x0 },
113 { OP_CVT, 0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
114 { OP_CEIL, 0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
115 { OP_FLOOR, 0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
116 { OP_TRUNC, 0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
117 { OP_AND, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
118 { OP_OR, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
119 { OP_XOR, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
120 { OP_SHL, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
121 { OP_SHR, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
122 { OP_SET, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
123 { OP_SLCT, 0x4, 0x0, 0x0, 0x0, 0x6, 0x2 }, // special c[] constraint
124 { OP_PREEX2, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
125 { OP_PRESIN, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
126 { OP_COS, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
127 { OP_SIN, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
128 { OP_EX2, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
129 { OP_LG2, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
130 { OP_RCP, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
131 { OP_RSQ, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
132 { OP_DFDX, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
133 { OP_DFDY, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
134 { OP_CALL, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
135 { OP_POPCNT, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 },
136 { OP_INSBF, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
137 { OP_EXTBF, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
138 { OP_BFIND, 0x0, 0x0, 0x1, 0x0, 0x1, 0x1 },
139 { OP_PERMT, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
140 { OP_SET_AND, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
141 { OP_SET_OR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
142 { OP_SET_XOR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
143 // saturate only:
144 { OP_LINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
145 { OP_PINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
146 // nve4 ops:
147 { OP_SULDB, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
148 { OP_SUSTB, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
149 { OP_SUSTP, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
150 { OP_SUCLAMP, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
151 { OP_SUBFM, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
152 { OP_SUEAU, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 }
153 };
154
initOpInfo()155 void TargetNVC0::initOpInfo()
156 {
157 unsigned int i, j;
158
159 static const uint32_t commutative[(OP_LAST + 31) / 32] =
160 {
161 // ADD, MUL, MAD, FMA, AND, OR, XOR, MAX, MIN, SET_AND, SET_OR, SET_XOR,
162 // SET, SELP, SLCT
163 0x0ce0ca00, 0x0000007e, 0x00000000, 0x00000000
164 };
165
166 static const uint32_t shortForm[(OP_LAST + 31) / 32] =
167 {
168 // ADD, MUL, MAD, FMA, AND, OR, XOR, MAX, MIN
169 0x0ce0ca00, 0x00000000, 0x00000000, 0x00000000
170 };
171
172 static const operation noDest[] =
173 {
174 OP_STORE, OP_WRSV, OP_EXPORT, OP_BRA, OP_CALL, OP_RET, OP_EXIT,
175 OP_DISCARD, OP_CONT, OP_BREAK, OP_PRECONT, OP_PREBREAK, OP_PRERET,
176 OP_JOIN, OP_JOINAT, OP_BRKPT, OP_MEMBAR, OP_EMIT, OP_RESTART,
177 OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
178 OP_SUREDB, OP_BAR
179 };
180
181 static const operation noPred[] =
182 {
183 OP_CALL, OP_PRERET, OP_QUADON, OP_QUADPOP,
184 OP_JOINAT, OP_PREBREAK, OP_PRECONT, OP_BRKPT
185 };
186
187 for (i = 0; i < DATA_FILE_COUNT; ++i)
188 nativeFileMap[i] = (DataFile)i;
189 nativeFileMap[FILE_ADDRESS] = FILE_GPR;
190
191 for (i = 0; i < OP_LAST; ++i) {
192 opInfo[i].variants = NULL;
193 opInfo[i].op = (operation)i;
194 opInfo[i].srcTypes = 1 << (int)TYPE_F32;
195 opInfo[i].dstTypes = 1 << (int)TYPE_F32;
196 opInfo[i].immdBits = 0;
197 opInfo[i].srcNr = operationSrcNr[i];
198
199 for (j = 0; j < opInfo[i].srcNr; ++j) {
200 opInfo[i].srcMods[j] = 0;
201 opInfo[i].srcFiles[j] = 1 << (int)FILE_GPR;
202 }
203 opInfo[i].dstMods = 0;
204 opInfo[i].dstFiles = 1 << (int)FILE_GPR;
205
206 opInfo[i].hasDest = 1;
207 opInfo[i].vector = (i >= OP_TEX && i <= OP_TEXCSAA);
208 opInfo[i].commutative = (commutative[i / 32] >> (i % 32)) & 1;
209 opInfo[i].pseudo = (i < OP_MOV);
210 opInfo[i].predicate = !opInfo[i].pseudo;
211 opInfo[i].flow = (i >= OP_BRA && i <= OP_JOIN);
212 opInfo[i].minEncSize = (shortForm[i / 32] & (1 << (i % 32))) ? 4 : 8;
213 }
214 for (i = 0; i < sizeof(noDest) / sizeof(noDest[0]); ++i)
215 opInfo[noDest[i]].hasDest = 0;
216 for (i = 0; i < sizeof(noPred) / sizeof(noPred[0]); ++i)
217 opInfo[noPred[i]].predicate = 0;
218
219 for (i = 0; i < sizeof(_initProps) / sizeof(_initProps[0]); ++i) {
220 const struct opProperties *prop = &_initProps[i];
221
222 for (int s = 0; s < 3; ++s) {
223 if (prop->mNeg & (1 << s))
224 opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NEG;
225 if (prop->mAbs & (1 << s))
226 opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_ABS;
227 if (prop->mNot & (1 << s))
228 opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NOT;
229 if (prop->fConst & (1 << s))
230 opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_MEMORY_CONST;
231 if (prop->fImmd & (1 << s))
232 opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_IMMEDIATE;
233 if (prop->fImmd & 8)
234 opInfo[prop->op].immdBits = 0xffffffff;
235 }
236 if (prop->mSat & 8)
237 opInfo[prop->op].dstMods = NV50_IR_MOD_SAT;
238 }
239 }
240
241 unsigned int
getFileSize(DataFile file) const242 TargetNVC0::getFileSize(DataFile file) const
243 {
244 const unsigned int gprs = (chipset >= NVISA_GK20A_CHIPSET) ? 255 : 63;
245 const unsigned int smregs = (chipset >= NVISA_GK104_CHIPSET) ? 65536 : 32768;
246 switch (file) {
247 case FILE_NULL: return 0;
248 case FILE_GPR: return MIN2(gprs, smregs / threads);
249 case FILE_PREDICATE: return 7;
250 case FILE_FLAGS: return 1;
251 case FILE_ADDRESS: return 0;
252 case FILE_IMMEDIATE: return 0;
253 case FILE_MEMORY_CONST: return 65536;
254 case FILE_SHADER_INPUT: return 0x400;
255 case FILE_SHADER_OUTPUT: return 0x400;
256 case FILE_MEMORY_BUFFER: return 0xffffffff;
257 case FILE_MEMORY_GLOBAL: return 0xffffffff;
258 case FILE_MEMORY_SHARED: return 16 << 10;
259 case FILE_MEMORY_LOCAL: return 48 << 10;
260 case FILE_SYSTEM_VALUE: return 32;
261 default:
262 assert(!"invalid file");
263 return 0;
264 }
265 }
266
267 unsigned int
getFileUnit(DataFile file) const268 TargetNVC0::getFileUnit(DataFile file) const
269 {
270 if (file == FILE_GPR || file == FILE_ADDRESS || file == FILE_SYSTEM_VALUE)
271 return 2;
272 return 0;
273 }
274
275 uint32_t
getSVAddress(DataFile shaderFile,const Symbol * sym) const276 TargetNVC0::getSVAddress(DataFile shaderFile, const Symbol *sym) const
277 {
278 const int idx = sym->reg.data.sv.index;
279 const SVSemantic sv = sym->reg.data.sv.sv;
280
281 const bool isInput = shaderFile == FILE_SHADER_INPUT;
282 const bool kepler = getChipset() >= NVISA_GK104_CHIPSET;
283
284 switch (sv) {
285 case SV_POSITION: return 0x070 + idx * 4;
286 case SV_INSTANCE_ID: return 0x2f8;
287 case SV_VERTEX_ID: return 0x2fc;
288 case SV_PRIMITIVE_ID: return isInput ? 0x060 : 0x040;
289 case SV_LAYER: return 0x064;
290 case SV_VIEWPORT_INDEX: return 0x068;
291 case SV_POINT_SIZE: return 0x06c;
292 case SV_CLIP_DISTANCE: return 0x2c0 + idx * 4;
293 case SV_POINT_COORD: return 0x2e0 + idx * 4;
294 case SV_FACE: return 0x3fc;
295 case SV_TESS_OUTER: return 0x000 + idx * 4;
296 case SV_TESS_INNER: return 0x010 + idx * 4;
297 case SV_TESS_COORD: return 0x2f0 + idx * 4;
298 case SV_NTID: return kepler ? (0x00 + idx * 4) : ~0;
299 case SV_NCTAID: return kepler ? (0x0c + idx * 4) : ~0;
300 case SV_GRIDID: return kepler ? 0x18 : ~0;
301 case SV_WORK_DIM: return 0x1c;
302 case SV_SAMPLE_INDEX: return 0;
303 case SV_SAMPLE_POS: return 0;
304 case SV_SAMPLE_MASK: return 0;
305 case SV_BASEVERTEX: return 0;
306 case SV_BASEINSTANCE: return 0;
307 case SV_DRAWID: return 0;
308 default:
309 return 0xffffffff;
310 }
311 }
312
313 bool
insnCanLoad(const Instruction * i,int s,const Instruction * ld) const314 TargetNVC0::insnCanLoad(const Instruction *i, int s,
315 const Instruction *ld) const
316 {
317 DataFile sf = ld->src(0).getFile();
318
319 // immediate 0 can be represented by GPR $r63/$r255
320 if (sf == FILE_IMMEDIATE && ld->getSrc(0)->reg.data.u64 == 0)
321 return (!i->isPseudo() &&
322 !i->asTex() &&
323 i->op != OP_EXPORT && i->op != OP_STORE);
324
325 if (s >= opInfo[i->op].srcNr)
326 return false;
327 if (!(opInfo[i->op].srcFiles[s] & (1 << (int)sf)))
328 return false;
329
330 // indirect loads can only be done by OP_LOAD/VFETCH/INTERP on nvc0
331 if (ld->src(0).isIndirect(0))
332 return false;
333 // these are implemented using shf.r and shf.l which can't load consts
334 if ((i->op == OP_SHL || i->op == OP_SHR) && typeSizeof(i->sType) == 8 &&
335 sf == FILE_MEMORY_CONST)
336 return false;
337
338 for (int k = 0; i->srcExists(k); ++k) {
339 if (i->src(k).getFile() == FILE_IMMEDIATE) {
340 if (k == 2 && i->op == OP_SUCLAMP) // special case
341 continue;
342 if (k == 1 && i->op == OP_SHLADD) // special case
343 continue;
344 if (i->getSrc(k)->reg.data.u64 != 0)
345 return false;
346 } else
347 if (i->src(k).getFile() != FILE_GPR &&
348 i->src(k).getFile() != FILE_PREDICATE &&
349 i->src(k).getFile() != FILE_FLAGS) {
350 return false;
351 }
352 }
353
354 // not all instructions support full 32 bit immediates
355 if (sf == FILE_IMMEDIATE) {
356 Storage ® = ld->getSrc(0)->asImm()->reg;
357
358 if (opInfo[i->op].immdBits != 0xffffffff || typeSizeof(i->sType) > 4) {
359 switch (i->sType) {
360 case TYPE_F64:
361 if (reg.data.u64 & 0x00000fffffffffffULL)
362 return false;
363 break;
364 case TYPE_F32:
365 if (reg.data.u32 & 0xfff)
366 return false;
367 break;
368 case TYPE_S32:
369 case TYPE_U32:
370 // with u32, 0xfffff counts as 0xffffffff as well
371 if (reg.data.s32 > 0x7ffff || reg.data.s32 < -0x80000)
372 return false;
373 break;
374 case TYPE_U8:
375 case TYPE_S8:
376 case TYPE_U16:
377 case TYPE_S16:
378 case TYPE_F16:
379 break;
380 default:
381 return false;
382 }
383 } else
384 if (i->op == OP_ADD && i->sType == TYPE_F32) {
385 // add f32 LIMM cannot saturate
386 if (i->saturate && (reg.data.u32 & 0xfff))
387 return false;
388 }
389 }
390
391 return true;
392 }
393
394 bool
insnCanLoadOffset(const Instruction * insn,int s,int offset) const395 TargetNVC0::insnCanLoadOffset(const Instruction *insn, int s, int offset) const
396 {
397 const ValueRef& ref = insn->src(s);
398 if (ref.getFile() == FILE_MEMORY_CONST &&
399 (insn->op != OP_LOAD || insn->subOp != NV50_IR_SUBOP_LDC_IS))
400 return offset >= -0x8000 && offset < 0x8000;
401 return true;
402 }
403
404 bool
isAccessSupported(DataFile file,DataType ty) const405 TargetNVC0::isAccessSupported(DataFile file, DataType ty) const
406 {
407 if (ty == TYPE_NONE)
408 return false;
409 if (file == FILE_MEMORY_CONST) {
410 if (getChipset() >= NVISA_GM107_CHIPSET)
411 return typeSizeof(ty) <= 4;
412 else
413 if (getChipset() >= NVISA_GK104_CHIPSET) // wrong encoding ?
414 return typeSizeof(ty) <= 8;
415 }
416 if (ty == TYPE_B96)
417 return false;
418 return true;
419 }
420
421 bool
isOpSupported(operation op,DataType ty) const422 TargetNVC0::isOpSupported(operation op, DataType ty) const
423 {
424 if (op == OP_SAD && ty != TYPE_S32 && ty != TYPE_U32)
425 return false;
426 if (op == OP_POW || op == OP_SQRT || op == OP_DIV || op == OP_MOD)
427 return false;
428 return true;
429 }
430
431 bool
isModSupported(const Instruction * insn,int s,Modifier mod) const432 TargetNVC0::isModSupported(const Instruction *insn, int s, Modifier mod) const
433 {
434 if (!isFloatType(insn->dType)) {
435 switch (insn->op) {
436 case OP_ABS:
437 case OP_NEG:
438 case OP_CVT:
439 case OP_CEIL:
440 case OP_FLOOR:
441 case OP_TRUNC:
442 case OP_AND:
443 case OP_OR:
444 case OP_XOR:
445 case OP_POPCNT:
446 case OP_BFIND:
447 break;
448 case OP_SET:
449 if (insn->sType != TYPE_F32)
450 return false;
451 break;
452 case OP_ADD:
453 if (mod.abs())
454 return false;
455 if (insn->src(s ? 0 : 1).mod.neg())
456 return false;
457 break;
458 case OP_SUB:
459 if (s == 0)
460 return insn->src(1).mod.neg() ? false : true;
461 break;
462 case OP_SHLADD:
463 if (s == 1)
464 return false;
465 if (insn->src(s ? 0 : 2).mod.neg())
466 return false;
467 break;
468 default:
469 return false;
470 }
471 }
472 if (s >= opInfo[insn->op].srcNr || s >= 3)
473 return false;
474 return (mod & Modifier(opInfo[insn->op].srcMods[s])) == mod;
475 }
476
477 bool
mayPredicate(const Instruction * insn,const Value * pred) const478 TargetNVC0::mayPredicate(const Instruction *insn, const Value *pred) const
479 {
480 if (insn->getPredicate())
481 return false;
482 return opInfo[insn->op].predicate;
483 }
484
485 bool
isSatSupported(const Instruction * insn) const486 TargetNVC0::isSatSupported(const Instruction *insn) const
487 {
488 if (insn->op == OP_CVT)
489 return true;
490 if (!(opInfo[insn->op].dstMods & NV50_IR_MOD_SAT))
491 return false;
492
493 if (insn->dType == TYPE_U32)
494 return (insn->op == OP_ADD) || (insn->op == OP_MAD);
495
496 // add f32 LIMM cannot saturate
497 if (insn->op == OP_ADD && insn->sType == TYPE_F32) {
498 if (insn->getSrc(1)->asImm() &&
499 insn->getSrc(1)->reg.data.u32 & 0xfff)
500 return false;
501 }
502
503 return insn->dType == TYPE_F32;
504 }
505
506 bool
isPostMultiplySupported(operation op,float f,int & e) const507 TargetNVC0::isPostMultiplySupported(operation op, float f, int& e) const
508 {
509 if (op != OP_MUL)
510 return false;
511 f = fabsf(f);
512 e = static_cast<int>(log2f(f));
513 if (e < -3 || e > 3)
514 return false;
515 return f == exp2f(static_cast<float>(e));
516 }
517
518 // TODO: better values
519 // this could be more precise, e.g. depending on the issue-to-read/write delay
520 // of the depending instruction, but it's good enough
getLatency(const Instruction * i) const521 int TargetNVC0::getLatency(const Instruction *i) const
522 {
523 if (chipset >= 0xe4) {
524 if (i->dType == TYPE_F64 || i->sType == TYPE_F64)
525 return 20;
526 switch (i->op) {
527 case OP_LINTERP:
528 case OP_PINTERP:
529 return 15;
530 case OP_LOAD:
531 if (i->src(0).getFile() == FILE_MEMORY_CONST)
532 return 9;
533 // fall through
534 case OP_VFETCH:
535 return 24;
536 default:
537 if (Target::getOpClass(i->op) == OPCLASS_TEXTURE)
538 return 17;
539 if (i->op == OP_MUL && i->dType != TYPE_F32)
540 return 15;
541 return 9;
542 }
543 } else {
544 if (i->op == OP_LOAD) {
545 if (i->cache == CACHE_CV)
546 return 700;
547 return 48;
548 }
549 return 24;
550 }
551 return 32;
552 }
553
554 // These are "inverse" throughput values, i.e. the number of cycles required
555 // to issue a specific instruction for a full warp (32 threads).
556 //
557 // Assuming we have more than 1 warp in flight, a higher issue latency results
558 // in a lower result latency since the MP will have spent more time with other
559 // warps.
560 // This also helps to determine the number of cycles between instructions in
561 // a single warp.
562 //
getThroughput(const Instruction * i) const563 int TargetNVC0::getThroughput(const Instruction *i) const
564 {
565 // TODO: better values
566 if (i->dType == TYPE_F32) {
567 switch (i->op) {
568 case OP_ADD:
569 case OP_MUL:
570 case OP_MAD:
571 case OP_FMA:
572 return 1;
573 case OP_CVT:
574 case OP_CEIL:
575 case OP_FLOOR:
576 case OP_TRUNC:
577 case OP_SET:
578 case OP_SLCT:
579 case OP_MIN:
580 case OP_MAX:
581 return 2;
582 case OP_RCP:
583 case OP_RSQ:
584 case OP_LG2:
585 case OP_SIN:
586 case OP_COS:
587 case OP_PRESIN:
588 case OP_PREEX2:
589 default:
590 return 8;
591 }
592 } else
593 if (i->dType == TYPE_U32 || i->dType == TYPE_S32) {
594 switch (i->op) {
595 case OP_ADD:
596 case OP_AND:
597 case OP_OR:
598 case OP_XOR:
599 case OP_NOT:
600 return 1;
601 case OP_MUL:
602 case OP_MAD:
603 case OP_CVT:
604 case OP_SET:
605 case OP_SLCT:
606 case OP_SHL:
607 case OP_SHR:
608 case OP_NEG:
609 case OP_ABS:
610 case OP_MIN:
611 case OP_MAX:
612 default:
613 return 2;
614 }
615 } else
616 if (i->dType == TYPE_F64) {
617 return 2;
618 } else {
619 return 1;
620 }
621 }
622
canDualIssue(const Instruction * a,const Instruction * b) const623 bool TargetNVC0::canDualIssue(const Instruction *a, const Instruction *b) const
624 {
625 const OpClass clA = operationClass[a->op];
626 const OpClass clB = operationClass[b->op];
627
628 if (getChipset() >= 0xe4) {
629 // not texturing
630 // not if the 2nd instruction isn't necessarily executed
631 if (clA == OPCLASS_TEXTURE || clA == OPCLASS_FLOW)
632 return false;
633
634 // Check that a and b don't write to the same sources, nor that b reads
635 // anything that a writes.
636 if (!a->canCommuteDefDef(b) || !a->canCommuteDefSrc(b))
637 return false;
638
639 // anything with MOV
640 if (a->op == OP_MOV || b->op == OP_MOV)
641 return true;
642 if (clA == clB) {
643 switch (clA) {
644 // there might be more
645 case OPCLASS_COMPARE:
646 if ((a->op == OP_MIN || a->op == OP_MAX) &&
647 (b->op == OP_MIN || b->op == OP_MAX))
648 break;
649 return false;
650 case OPCLASS_ARITH:
651 break;
652 default:
653 return false;
654 }
655 // only F32 arith or integer additions
656 return (a->dType == TYPE_F32 || a->op == OP_ADD ||
657 b->dType == TYPE_F32 || b->op == OP_ADD);
658 }
659 // nothing with TEXBAR
660 if (a->op == OP_TEXBAR || b->op == OP_TEXBAR)
661 return false;
662 // no loads and stores accessing the same space
663 if ((clA == OPCLASS_LOAD && clB == OPCLASS_STORE) ||
664 (clB == OPCLASS_LOAD && clA == OPCLASS_STORE))
665 if (a->src(0).getFile() == b->src(0).getFile())
666 return false;
667 // no > 32-bit ops
668 if (typeSizeof(a->dType) > 4 || typeSizeof(b->dType) > 4 ||
669 typeSizeof(a->sType) > 4 || typeSizeof(b->sType) > 4)
670 return false;
671 return true;
672 } else {
673 return false; // info not needed (yet)
674 }
675 }
676
677 } // namespace nv50_ir
678