1 #include <common.h>
2 #include <console.h> /* ctrlc */
3 #include <asm/io.h>
4
5 #include "hydra.h"
6
7 enum {
8 HWVER_100 = 0,
9 HWVER_110 = 1,
10 HWVER_120 = 2,
11 };
12
13 static struct pci_device_id hydra_supported[] = {
14 { 0x6d5e, 0xcdc1 },
15 {}
16 };
17
18 static struct ihs_fpga *fpga;
19
get_fpga(void)20 struct ihs_fpga *get_fpga(void)
21 {
22 return fpga;
23 }
24
print_hydra_version(uint index)25 void print_hydra_version(uint index)
26 {
27 u32 versions = readl(&fpga->versions);
28 u32 fpga_version = readl(&fpga->fpga_version);
29
30 uint hardware_version = versions & 0xf;
31
32 printf("FPGA%u: mapped to %p\n ", index, fpga);
33
34 switch (hardware_version) {
35 case HWVER_100:
36 printf("HW-Ver 1.00\n");
37 break;
38
39 case HWVER_110:
40 printf("HW-Ver 1.10\n");
41 break;
42
43 case HWVER_120:
44 printf("HW-Ver 1.20\n");
45 break;
46
47 default:
48 printf("HW-Ver %d(not supported)\n",
49 hardware_version);
50 break;
51 }
52
53 printf(" FPGA V %d.%02d\n",
54 fpga_version / 100, fpga_version % 100);
55 }
56
hydra_initialize(void)57 void hydra_initialize(void)
58 {
59 uint i;
60 pci_dev_t devno;
61
62 /* Find and probe all the matching PCI devices */
63 for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
64 u32 val;
65
66 /* Try to enable I/O accesses and bus-mastering */
67 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
68 pci_write_config_dword(devno, PCI_COMMAND, val);
69
70 /* Make sure it worked */
71 pci_read_config_dword(devno, PCI_COMMAND, &val);
72 if (!(val & PCI_COMMAND_MEMORY)) {
73 puts("Can't enable I/O memory\n");
74 continue;
75 }
76 if (!(val & PCI_COMMAND_MASTER)) {
77 puts("Can't enable bus-mastering\n");
78 continue;
79 }
80
81 /* read FPGA details */
82 fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
83 PCI_REGION_MEM);
84
85 print_hydra_version(i);
86 }
87 }
88
89 #define REFL_PATTERN (0xdededede)
90 #define REFL_PATTERN_INV (~REFL_PATTERN)
91
do_hydrate(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])92 int do_hydrate(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
93 {
94 uint k = 0;
95 void __iomem *pcie2_base = (void __iomem *)(MVEBU_REG_PCIE_BASE +
96 0x4000);
97
98 if (!fpga)
99 return -1;
100
101 while (1) {
102 u32 res;
103
104 writel(REFL_PATTERN, &fpga->reflection_low);
105 res = readl(&fpga->reflection_low);
106 if (res != REFL_PATTERN_INV)
107 printf("round %u: read %08x, expected %08x\n",
108 k, res, REFL_PATTERN_INV);
109 writel(REFL_PATTERN_INV, &fpga->reflection_low);
110 res = readl(&fpga->reflection_low);
111 if (res != REFL_PATTERN)
112 printf("round %u: read %08x, expected %08x\n",
113 k, res, REFL_PATTERN);
114
115 res = readl(pcie2_base + 0x118) & 0x1f;
116 if (res)
117 printf("FrstErrPtr %u\n", res);
118 res = readl(pcie2_base + 0x104);
119 if (res) {
120 printf("Uncorrectable Error Status 0x%08x\n", res);
121 writel(res, pcie2_base + 0x104);
122 }
123
124 if (!(++k % 10000))
125 printf("round %u\n", k);
126
127 if (ctrlc())
128 break;
129 }
130
131 return 0;
132 }
133
134 U_BOOT_CMD(
135 hydrate, 1, 0, do_hydrate,
136 "hydra reflection test",
137 "hydra reflection test"
138 );
139