1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007,2009-2014 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <pci.h>
9 #include <asm/processor.h>
10 #include <asm/mmu.h>
11 #include <asm/fsl_pci.h>
12 #include <asm/io.h>
13 #include <linux/libfdt.h>
14 #include <fdt_support.h>
15 #include <netdev.h>
16 #include <fdtdec.h>
17 #include <errno.h>
18 #include <malloc.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
get_fdt_virt(void)22 static void *get_fdt_virt(void)
23 {
24 return (void *)CONFIG_SYS_TMPVIRT;
25 }
26
get_fdt_phys(void)27 static uint64_t get_fdt_phys(void)
28 {
29 return (uint64_t)(uintptr_t)gd->fdt_blob;
30 }
31
map_fdt_as(int esel)32 static void map_fdt_as(int esel)
33 {
34 u32 mas0, mas1, mas2, mas3, mas7;
35 uint64_t fdt_phys = get_fdt_phys();
36 unsigned long fdt_phys_tlb = fdt_phys & ~0xffffful;
37 unsigned long fdt_virt_tlb = (ulong)get_fdt_virt() & ~0xffffful;
38
39 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(esel);
40 mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
41 mas2 = FSL_BOOKE_MAS2(fdt_virt_tlb, 0);
42 mas3 = FSL_BOOKE_MAS3(fdt_phys_tlb, 0, MAS3_SW|MAS3_SR);
43 mas7 = FSL_BOOKE_MAS7(fdt_phys_tlb);
44
45 write_tlb(mas0, mas1, mas2, mas3, mas7);
46 }
47
get_phys_ccsrbar_addr_early(void)48 uint64_t get_phys_ccsrbar_addr_early(void)
49 {
50 void *fdt = get_fdt_virt();
51 uint64_t r;
52 int size, node;
53 u32 naddr;
54 const fdt32_t *prop;
55
56 /*
57 * To be able to read the FDT we need to create a temporary TLB
58 * map for it.
59 */
60 map_fdt_as(10);
61 node = fdt_path_offset(fdt, "/soc");
62 naddr = fdt_address_cells(fdt, node);
63 prop = fdt_getprop(fdt, node, "ranges", &size);
64 r = fdt_translate_address(fdt, node, prop + naddr);
65 disable_tlb(10);
66
67 return r;
68 }
69
board_early_init_f(void)70 int board_early_init_f(void)
71 {
72 return 0;
73 }
74
checkboard(void)75 int checkboard(void)
76 {
77 return 0;
78 }
79
pci_map_region(void * fdt,int pci_node,int range_id,phys_size_t * ppaddr,pci_addr_t * pvaddr,pci_size_t * psize,ulong * pmap_addr)80 static int pci_map_region(void *fdt, int pci_node, int range_id,
81 phys_size_t *ppaddr, pci_addr_t *pvaddr,
82 pci_size_t *psize, ulong *pmap_addr)
83 {
84 uint64_t addr;
85 uint64_t size;
86 ulong map_addr;
87 int r;
88
89 r = fdt_read_range(fdt, pci_node, range_id, NULL, &addr, &size);
90 if (r)
91 return r;
92
93 if (ppaddr)
94 *ppaddr = addr;
95 if (psize)
96 *psize = size;
97
98 if (!pmap_addr)
99 return 0;
100
101 map_addr = *pmap_addr;
102
103 /* Align map_addr */
104 map_addr += size - 1;
105 map_addr &= ~(size - 1);
106
107 if (map_addr + size >= CONFIG_SYS_PCI_MAP_END)
108 return -1;
109
110 /* Map virtual memory for range */
111 assert(!tlb_map_range(map_addr, addr, size, TLB_MAP_IO));
112 *pmap_addr = map_addr + size;
113
114 if (pvaddr)
115 *pvaddr = map_addr;
116
117 return 0;
118 }
119
pci_init_board(void)120 void pci_init_board(void)
121 {
122 struct pci_controller *pci_hoses;
123 void *fdt = get_fdt_virt();
124 int pci_node = -1;
125 int pci_num = 0;
126 int pci_count = 0;
127 ulong map_addr;
128
129 puts("\n");
130
131 /* Start MMIO and PIO range maps above RAM */
132 map_addr = CONFIG_SYS_PCI_MAP_START;
133
134 /* Count and allocate PCI buses */
135 pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
136 "device_type", "pci", 4);
137 while (pci_node != -FDT_ERR_NOTFOUND) {
138 pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
139 "device_type", "pci", 4);
140 pci_count++;
141 }
142
143 if (pci_count) {
144 pci_hoses = malloc(sizeof(struct pci_controller) * pci_count);
145 } else {
146 printf("PCI: disabled\n\n");
147 return;
148 }
149
150 /* Spawn PCI buses based on device tree */
151 pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
152 "device_type", "pci", 4);
153 while (pci_node != -FDT_ERR_NOTFOUND) {
154 struct fsl_pci_info pci_info = { };
155 const fdt32_t *reg;
156 int r;
157
158 reg = fdt_getprop(fdt, pci_node, "reg", NULL);
159 pci_info.regs = fdt_translate_address(fdt, pci_node, reg);
160
161 /* Map MMIO range */
162 r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_phys, NULL,
163 &pci_info.mem_size, &map_addr);
164 if (r)
165 break;
166
167 /* Map PIO range */
168 r = pci_map_region(fdt, pci_node, 1, &pci_info.io_phys, NULL,
169 &pci_info.io_size, &map_addr);
170 if (r)
171 break;
172
173 /*
174 * The PCI framework finds virtual addresses for the buses
175 * through our address map, so tell it the physical addresses.
176 */
177 pci_info.mem_bus = pci_info.mem_phys;
178 pci_info.io_bus = pci_info.io_phys;
179
180 /* Instantiate */
181 pci_info.pci_num = pci_num + 1;
182
183 fsl_setup_hose(&pci_hoses[pci_num], pci_info.regs);
184 printf("PCI: base address %lx\n", pci_info.regs);
185
186 fsl_pci_init_port(&pci_info, &pci_hoses[pci_num], pci_num);
187
188 /* Jump to next PCI node */
189 pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
190 "device_type", "pci", 4);
191 pci_num++;
192 }
193
194 puts("\n");
195 }
196
last_stage_init(void)197 int last_stage_init(void)
198 {
199 void *fdt = get_fdt_virt();
200 int len = 0;
201 const uint64_t *prop;
202 int chosen;
203
204 chosen = fdt_path_offset(fdt, "/chosen");
205 if (chosen < 0) {
206 printf("Couldn't find /chosen node in fdt\n");
207 return -EIO;
208 }
209
210 /* -kernel boot */
211 prop = fdt_getprop(fdt, chosen, "qemu,boot-kernel", &len);
212 if (prop && (len >= 8))
213 env_set_hex("qemu_kernel_addr", *prop);
214
215 /* Give the user a variable for the host fdt */
216 env_set_hex("fdt_addr_r", (ulong)fdt);
217
218 return 0;
219 }
220
get_linear_ram_size(void)221 static uint64_t get_linear_ram_size(void)
222 {
223 void *fdt = get_fdt_virt();
224 const void *prop;
225 int memory;
226 int len;
227
228 memory = fdt_path_offset(fdt, "/memory");
229 prop = fdt_getprop(fdt, memory, "reg", &len);
230
231 if (prop && len >= 16)
232 return *(uint64_t *)(prop+8);
233
234 panic("Couldn't determine RAM size");
235 }
236
board_eth_init(bd_t * bis)237 int board_eth_init(bd_t *bis)
238 {
239 return pci_eth_init(bis);
240 }
241
242 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)243 int ft_board_setup(void *blob, bd_t *bd)
244 {
245 FT_FSL_PCI_SETUP;
246
247 return 0;
248 }
249 #endif
250
print_laws(void)251 void print_laws(void)
252 {
253 /* We don't emulate LAWs yet */
254 }
255
fixed_sdram(void)256 phys_size_t fixed_sdram(void)
257 {
258 return get_linear_ram_size();
259 }
260
fsl_ddr_sdram_size(void)261 phys_size_t fsl_ddr_sdram_size(void)
262 {
263 return get_linear_ram_size();
264 }
265
init_tlbs(void)266 void init_tlbs(void)
267 {
268 phys_size_t ram_size;
269
270 /*
271 * Create a temporary AS=1 map for the fdt
272 *
273 * We use ESEL=0 here to overwrite the previous AS=0 map for ourselves
274 * which was only 4k big. This way we don't have to clear any other maps.
275 */
276 map_fdt_as(0);
277
278 /* Fetch RAM size from the fdt */
279 ram_size = get_linear_ram_size();
280
281 /* And remove our fdt map again */
282 disable_tlb(0);
283
284 /* Create an internal map of manually created TLB maps */
285 init_used_tlb_cams();
286
287 /* Create a dynamic AS=0 CCSRBAR mapping */
288 assert(!tlb_map_range(CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
289 1024 * 1024, TLB_MAP_IO));
290
291 /* Create a RAM map that spans all accessible RAM */
292 setup_ddr_tlbs(ram_size >> 20);
293
294 /* Create a map for the TLB */
295 assert(!tlb_map_range((ulong)get_fdt_virt(), get_fdt_phys(),
296 1024 * 1024, TLB_MAP_RAM));
297 }
298
init_laws(void)299 void init_laws(void)
300 {
301 /* We don't emulate LAWs yet */
302 }
303
get_cpu_freq(void)304 static uint32_t get_cpu_freq(void)
305 {
306 void *fdt = get_fdt_virt();
307 int cpus_node = fdt_path_offset(fdt, "/cpus");
308 int cpu_node = fdt_first_subnode(fdt, cpus_node);
309 const char *prop = "clock-frequency";
310 return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0);
311 }
312
get_sys_info(sys_info_t * sys_info)313 void get_sys_info(sys_info_t *sys_info)
314 {
315 int freq = get_cpu_freq();
316
317 memset(sys_info, 0, sizeof(sys_info_t));
318 sys_info->freq_systembus = freq;
319 sys_info->freq_ddrbus = freq;
320 sys_info->freq_processor[0] = freq;
321 }
322
get_clocks(void)323 int get_clocks (void)
324 {
325 sys_info_t sys_info;
326
327 get_sys_info(&sys_info);
328
329 gd->cpu_clk = sys_info.freq_processor[0];
330 gd->bus_clk = sys_info.freq_systembus;
331 gd->mem_clk = sys_info.freq_ddrbus;
332 gd->arch.lbc_clk = sys_info.freq_ddrbus;
333
334 return 0;
335 }
336
get_tbclk(void)337 unsigned long get_tbclk (void)
338 {
339 void *fdt = get_fdt_virt();
340 int cpus_node = fdt_path_offset(fdt, "/cpus");
341 int cpu_node = fdt_first_subnode(fdt, cpus_node);
342 const char *prop = "timebase-frequency";
343 return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0);
344 }
345
346 /********************************************
347 * get_bus_freq
348 * return system bus freq in Hz
349 *********************************************/
get_bus_freq(ulong dummy)350 ulong get_bus_freq (ulong dummy)
351 {
352 sys_info_t sys_info;
353 get_sys_info(&sys_info);
354 return sys_info.freq_systembus;
355 }
356
357 /*
358 * Return the number of cores on this SOC.
359 */
cpu_numcores(void)360 int cpu_numcores(void)
361 {
362 /*
363 * The QEMU u-boot target only needs to drive the first core,
364 * spinning and device tree nodes get driven by QEMU itself
365 */
366 return 1;
367 }
368
369 /*
370 * Return a 32-bit mask indicating which cores are present on this SOC.
371 */
cpu_mask(void)372 u32 cpu_mask(void)
373 {
374 return (1 << cpu_numcores()) - 1;
375 }
376