1 /*
2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef __GICV2_PRIVATE_H__
8 #define __GICV2_PRIVATE_H__
9
10 #include <gicv2.h>
11 #include <mmio.h>
12 #include <stdint.h>
13
14 /*******************************************************************************
15 * Private function prototypes
16 ******************************************************************************/
17 void gicv2_spis_configure_defaults(uintptr_t gicd_base);
18 #if !ERROR_DEPRECATED
19 void gicv2_secure_spis_configure(uintptr_t gicd_base,
20 unsigned int num_ints,
21 const unsigned int *sec_intr_list);
22 void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base,
23 unsigned int num_ints,
24 const unsigned int *sec_intr_list);
25 #endif
26 void gicv2_secure_spis_configure_props(uintptr_t gicd_base,
27 const interrupt_prop_t *interrupt_props,
28 unsigned int interrupt_props_num);
29 void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base,
30 const interrupt_prop_t *interrupt_props,
31 unsigned int interrupt_props_num);
32 unsigned int gicv2_get_cpuif_id(uintptr_t base);
33
34 /*******************************************************************************
35 * GIC Distributor interface accessors for reading entire registers
36 ******************************************************************************/
gicd_read_pidr2(uintptr_t base)37 static inline unsigned int gicd_read_pidr2(uintptr_t base)
38 {
39 return mmio_read_32(base + GICD_PIDR2_GICV2);
40 }
41
42 /*******************************************************************************
43 * GIC Distributor interface accessors for writing entire registers
44 ******************************************************************************/
gicd_get_itargetsr(uintptr_t base,unsigned int id)45 static inline unsigned int gicd_get_itargetsr(uintptr_t base, unsigned int id)
46 {
47 return mmio_read_8(base + GICD_ITARGETSR + id);
48 }
49
gicd_set_itargetsr(uintptr_t base,unsigned int id,unsigned int target)50 static inline void gicd_set_itargetsr(uintptr_t base, unsigned int id,
51 unsigned int target)
52 {
53 mmio_write_8(base + GICD_ITARGETSR + id, target & GIC_TARGET_CPU_MASK);
54 }
55
gicd_write_sgir(uintptr_t base,unsigned int val)56 static inline void gicd_write_sgir(uintptr_t base, unsigned int val)
57 {
58 mmio_write_32(base + GICD_SGIR, val);
59 }
60
61 /*******************************************************************************
62 * GIC CPU interface accessors for reading entire registers
63 ******************************************************************************/
64
gicc_read_ctlr(uintptr_t base)65 static inline unsigned int gicc_read_ctlr(uintptr_t base)
66 {
67 return mmio_read_32(base + GICC_CTLR);
68 }
69
gicc_read_pmr(uintptr_t base)70 static inline unsigned int gicc_read_pmr(uintptr_t base)
71 {
72 return mmio_read_32(base + GICC_PMR);
73 }
74
gicc_read_BPR(uintptr_t base)75 static inline unsigned int gicc_read_BPR(uintptr_t base)
76 {
77 return mmio_read_32(base + GICC_BPR);
78 }
79
gicc_read_IAR(uintptr_t base)80 static inline unsigned int gicc_read_IAR(uintptr_t base)
81 {
82 return mmio_read_32(base + GICC_IAR);
83 }
84
gicc_read_EOIR(uintptr_t base)85 static inline unsigned int gicc_read_EOIR(uintptr_t base)
86 {
87 return mmio_read_32(base + GICC_EOIR);
88 }
89
gicc_read_hppir(uintptr_t base)90 static inline unsigned int gicc_read_hppir(uintptr_t base)
91 {
92 return mmio_read_32(base + GICC_HPPIR);
93 }
94
gicc_read_ahppir(uintptr_t base)95 static inline unsigned int gicc_read_ahppir(uintptr_t base)
96 {
97 return mmio_read_32(base + GICC_AHPPIR);
98 }
99
gicc_read_dir(uintptr_t base)100 static inline unsigned int gicc_read_dir(uintptr_t base)
101 {
102 return mmio_read_32(base + GICC_DIR);
103 }
104
gicc_read_iidr(uintptr_t base)105 static inline unsigned int gicc_read_iidr(uintptr_t base)
106 {
107 return mmio_read_32(base + GICC_IIDR);
108 }
109
gicc_read_rpr(uintptr_t base)110 static inline unsigned int gicc_read_rpr(uintptr_t base)
111 {
112 return mmio_read_32(base + GICC_RPR);
113 }
114
115 /*******************************************************************************
116 * GIC CPU interface accessors for writing entire registers
117 ******************************************************************************/
118
gicc_write_ctlr(uintptr_t base,unsigned int val)119 static inline void gicc_write_ctlr(uintptr_t base, unsigned int val)
120 {
121 mmio_write_32(base + GICC_CTLR, val);
122 }
123
gicc_write_pmr(uintptr_t base,unsigned int val)124 static inline void gicc_write_pmr(uintptr_t base, unsigned int val)
125 {
126 mmio_write_32(base + GICC_PMR, val);
127 }
128
gicc_write_BPR(uintptr_t base,unsigned int val)129 static inline void gicc_write_BPR(uintptr_t base, unsigned int val)
130 {
131 mmio_write_32(base + GICC_BPR, val);
132 }
133
134
gicc_write_IAR(uintptr_t base,unsigned int val)135 static inline void gicc_write_IAR(uintptr_t base, unsigned int val)
136 {
137 mmio_write_32(base + GICC_IAR, val);
138 }
139
gicc_write_EOIR(uintptr_t base,unsigned int val)140 static inline void gicc_write_EOIR(uintptr_t base, unsigned int val)
141 {
142 mmio_write_32(base + GICC_EOIR, val);
143 }
144
gicc_write_hppir(uintptr_t base,unsigned int val)145 static inline void gicc_write_hppir(uintptr_t base, unsigned int val)
146 {
147 mmio_write_32(base + GICC_HPPIR, val);
148 }
149
gicc_write_dir(uintptr_t base,unsigned int val)150 static inline void gicc_write_dir(uintptr_t base, unsigned int val)
151 {
152 mmio_write_32(base + GICC_DIR, val);
153 }
154
155 #endif /* __GICV2_PRIVATE_H__ */
156