1 /*
2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch.h>
8 #include <arch_helpers.h>
9 #include <assert.h>
10 #include <debug.h>
11 #include <gicv3.h>
12 #include <interrupt_props.h>
13 #include <spinlock.h>
14 #include "gicv3_private.h"
15
16 const gicv3_driver_data_t *gicv3_driver_data;
17 static unsigned int gicv2_compat;
18
19 /*
20 * Spinlock to guard registers needing read-modify-write. APIs protected by this
21 * spinlock are used either at boot time (when only a single CPU is active), or
22 * when the system is fully coherent.
23 */
24 spinlock_t gic_lock;
25
26 /*
27 * Redistributor power operations are weakly bound so that they can be
28 * overridden
29 */
30 #pragma weak gicv3_rdistif_off
31 #pragma weak gicv3_rdistif_on
32
33
34 /* Helper macros to save and restore GICD registers to and from the context */
35 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \
36 do { \
37 for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \
38 int_id += (1 << REG##_SHIFT)) { \
39 gicd_write_##reg(base, int_id, \
40 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT]); \
41 } \
42 } while (0)
43
44 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \
45 do { \
46 for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \
47 int_id += (1 << REG##_SHIFT)) { \
48 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT] =\
49 gicd_read_##reg(base, int_id); \
50 } \
51 } while (0)
52
53
54 /*******************************************************************************
55 * This function initialises the ARM GICv3 driver in EL3 with provided platform
56 * inputs.
57 ******************************************************************************/
gicv3_driver_init(const gicv3_driver_data_t * plat_driver_data)58 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
59 {
60 unsigned int gic_version;
61
62 assert(plat_driver_data);
63 assert(plat_driver_data->gicd_base);
64 assert(plat_driver_data->gicr_base);
65 assert(plat_driver_data->rdistif_num);
66 assert(plat_driver_data->rdistif_base_addrs);
67
68 assert(IS_IN_EL3());
69
70 #if !ERROR_DEPRECATED
71 if (plat_driver_data->interrupt_props == NULL) {
72 /* Interrupt properties array size must be 0 */
73 assert(plat_driver_data->interrupt_props_num == 0);
74
75 /*
76 * The platform should provide a list of at least one type of
77 * interrupt.
78 */
79 assert(plat_driver_data->g0_interrupt_array ||
80 plat_driver_data->g1s_interrupt_array);
81
82 /*
83 * If there are no interrupts of a particular type, then the
84 * number of interrupts of that type should be 0 and vice-versa.
85 */
86 assert(plat_driver_data->g0_interrupt_array ?
87 plat_driver_data->g0_interrupt_num :
88 plat_driver_data->g0_interrupt_num == 0);
89 assert(plat_driver_data->g1s_interrupt_array ?
90 plat_driver_data->g1s_interrupt_num :
91 plat_driver_data->g1s_interrupt_num == 0);
92 }
93 #else
94 assert(plat_driver_data->interrupt_props != NULL);
95 assert(plat_driver_data->interrupt_props_num > 0);
96 #endif
97
98 /* Check for system register support */
99 #ifdef AARCH32
100 assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT));
101 #else
102 assert(read_id_aa64pfr0_el1() &
103 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT));
104 #endif /* AARCH32 */
105
106 /* The GIC version should be 3.0 */
107 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
108 gic_version >>= PIDR2_ARCH_REV_SHIFT;
109 gic_version &= PIDR2_ARCH_REV_MASK;
110 assert(gic_version == ARCH_REV_GICV3);
111
112 /*
113 * Find out whether the GIC supports the GICv2 compatibility mode. The
114 * ARE_S bit resets to 0 if supported
115 */
116 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base);
117 gicv2_compat >>= CTLR_ARE_S_SHIFT;
118 gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK);
119
120 /*
121 * Find the base address of each implemented Redistributor interface.
122 * The number of interfaces should be equal to the number of CPUs in the
123 * system. The memory for saving these addresses has to be allocated by
124 * the platform port
125 */
126 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs,
127 plat_driver_data->rdistif_num,
128 plat_driver_data->gicr_base,
129 plat_driver_data->mpidr_to_core_pos);
130
131 gicv3_driver_data = plat_driver_data;
132
133 /*
134 * The GIC driver data is initialized by the primary CPU with caches
135 * enabled. When the secondary CPU boots up, it initializes the
136 * GICC/GICR interface with the caches disabled. Hence flush the
137 * driver data to ensure coherency. This is not required if the
138 * platform has HW_ASSISTED_COHERENCY enabled.
139 */
140 #if !HW_ASSISTED_COHERENCY
141 flush_dcache_range((uintptr_t) &gicv3_driver_data,
142 sizeof(gicv3_driver_data));
143 flush_dcache_range((uintptr_t) gicv3_driver_data,
144 sizeof(*gicv3_driver_data));
145 #endif
146
147 INFO("GICv3 %s legacy support detected."
148 " ARM GICV3 driver initialized in EL3\n",
149 gicv2_compat ? "with" : "without");
150 }
151
152 /*******************************************************************************
153 * This function initialises the GIC distributor interface based upon the data
154 * provided by the platform while initialising the driver.
155 ******************************************************************************/
gicv3_distif_init(void)156 void gicv3_distif_init(void)
157 {
158 unsigned int bitmap = 0;
159
160 assert(gicv3_driver_data);
161 assert(gicv3_driver_data->gicd_base);
162
163 assert(IS_IN_EL3());
164
165 /*
166 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring
167 * the ARE_S bit. The Distributor might generate a system error
168 * otherwise.
169 */
170 gicd_clr_ctlr(gicv3_driver_data->gicd_base,
171 CTLR_ENABLE_G0_BIT |
172 CTLR_ENABLE_G1S_BIT |
173 CTLR_ENABLE_G1NS_BIT,
174 RWP_TRUE);
175
176 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
177 gicd_set_ctlr(gicv3_driver_data->gicd_base,
178 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE);
179
180 /* Set the default attribute of all SPIs */
181 gicv3_spis_configure_defaults(gicv3_driver_data->gicd_base);
182
183 #if !ERROR_DEPRECATED
184 if (gicv3_driver_data->interrupt_props != NULL) {
185 #endif
186 bitmap = gicv3_secure_spis_configure_props(
187 gicv3_driver_data->gicd_base,
188 gicv3_driver_data->interrupt_props,
189 gicv3_driver_data->interrupt_props_num);
190 #if !ERROR_DEPRECATED
191 } else {
192 assert(gicv3_driver_data->g1s_interrupt_array ||
193 gicv3_driver_data->g0_interrupt_array);
194
195 /* Configure the G1S SPIs */
196 if (gicv3_driver_data->g1s_interrupt_array) {
197 gicv3_secure_spis_configure(gicv3_driver_data->gicd_base,
198 gicv3_driver_data->g1s_interrupt_num,
199 gicv3_driver_data->g1s_interrupt_array,
200 INTR_GROUP1S);
201 bitmap |= CTLR_ENABLE_G1S_BIT;
202 }
203
204 /* Configure the G0 SPIs */
205 if (gicv3_driver_data->g0_interrupt_array) {
206 gicv3_secure_spis_configure(gicv3_driver_data->gicd_base,
207 gicv3_driver_data->g0_interrupt_num,
208 gicv3_driver_data->g0_interrupt_array,
209 INTR_GROUP0);
210 bitmap |= CTLR_ENABLE_G0_BIT;
211 }
212 }
213 #endif
214
215 /* Enable the secure SPIs now that they have been configured */
216 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE);
217 }
218
219 /*******************************************************************************
220 * This function initialises the GIC Redistributor interface of the calling CPU
221 * (identified by the 'proc_num' parameter) based upon the data provided by the
222 * platform while initialising the driver.
223 ******************************************************************************/
gicv3_rdistif_init(unsigned int proc_num)224 void gicv3_rdistif_init(unsigned int proc_num)
225 {
226 uintptr_t gicr_base;
227
228 assert(gicv3_driver_data);
229 assert(proc_num < gicv3_driver_data->rdistif_num);
230 assert(gicv3_driver_data->rdistif_base_addrs);
231 assert(gicv3_driver_data->gicd_base);
232 assert(gicd_read_ctlr(gicv3_driver_data->gicd_base) & CTLR_ARE_S_BIT);
233
234 assert(IS_IN_EL3());
235
236 /* Power on redistributor */
237 gicv3_rdistif_on(proc_num);
238
239 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
240
241 /* Set the default attribute of all SGIs and PPIs */
242 gicv3_ppi_sgi_configure_defaults(gicr_base);
243
244 #if !ERROR_DEPRECATED
245 if (gicv3_driver_data->interrupt_props != NULL) {
246 #endif
247 gicv3_secure_ppi_sgi_configure_props(gicr_base,
248 gicv3_driver_data->interrupt_props,
249 gicv3_driver_data->interrupt_props_num);
250 #if !ERROR_DEPRECATED
251 } else {
252 assert(gicv3_driver_data->g1s_interrupt_array ||
253 gicv3_driver_data->g0_interrupt_array);
254
255 /* Configure the G1S SGIs/PPIs */
256 if (gicv3_driver_data->g1s_interrupt_array) {
257 gicv3_secure_ppi_sgi_configure(gicr_base,
258 gicv3_driver_data->g1s_interrupt_num,
259 gicv3_driver_data->g1s_interrupt_array,
260 INTR_GROUP1S);
261 }
262
263 /* Configure the G0 SGIs/PPIs */
264 if (gicv3_driver_data->g0_interrupt_array) {
265 gicv3_secure_ppi_sgi_configure(gicr_base,
266 gicv3_driver_data->g0_interrupt_num,
267 gicv3_driver_data->g0_interrupt_array,
268 INTR_GROUP0);
269 }
270 }
271 #endif
272 }
273
274 /*******************************************************************************
275 * Functions to perform power operations on GIC Redistributor
276 ******************************************************************************/
gicv3_rdistif_off(unsigned int proc_num)277 void gicv3_rdistif_off(unsigned int proc_num)
278 {
279 return;
280 }
281
gicv3_rdistif_on(unsigned int proc_num)282 void gicv3_rdistif_on(unsigned int proc_num)
283 {
284 return;
285 }
286
287 /*******************************************************************************
288 * This function enables the GIC CPU interface of the calling CPU using only
289 * system register accesses.
290 ******************************************************************************/
gicv3_cpuif_enable(unsigned int proc_num)291 void gicv3_cpuif_enable(unsigned int proc_num)
292 {
293 uintptr_t gicr_base;
294 unsigned int scr_el3;
295 unsigned int icc_sre_el3;
296
297 assert(gicv3_driver_data);
298 assert(proc_num < gicv3_driver_data->rdistif_num);
299 assert(gicv3_driver_data->rdistif_base_addrs);
300 assert(IS_IN_EL3());
301
302 /* Mark the connected core as awake */
303 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
304 gicv3_rdistif_mark_core_awake(gicr_base);
305
306 /* Disable the legacy interrupt bypass */
307 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT;
308
309 /*
310 * Enable system register access for EL3 and allow lower exception
311 * levels to configure the same for themselves. If the legacy mode is
312 * not supported, the SRE bit is RAO/WI
313 */
314 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT);
315 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3);
316
317 scr_el3 = read_scr_el3();
318
319 /*
320 * Switch to NS state to write Non secure ICC_SRE_EL1 and
321 * ICC_SRE_EL2 registers.
322 */
323 write_scr_el3(scr_el3 | SCR_NS_BIT);
324 isb();
325
326 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3);
327 write_icc_sre_el1(ICC_SRE_SRE_BIT);
328 isb();
329
330 /* Switch to secure state. */
331 write_scr_el3(scr_el3 & (~SCR_NS_BIT));
332 isb();
333
334 /* Program the idle priority in the PMR */
335 write_icc_pmr_el1(GIC_PRI_MASK);
336
337 /* Enable Group0 interrupts */
338 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT);
339
340 /* Enable Group1 Secure interrupts */
341 write_icc_igrpen1_el3(read_icc_igrpen1_el3() |
342 IGRPEN1_EL3_ENABLE_G1S_BIT);
343
344 /* Write the secure ICC_SRE_EL1 register */
345 write_icc_sre_el1(ICC_SRE_SRE_BIT);
346 isb();
347 }
348
349 /*******************************************************************************
350 * This function disables the GIC CPU interface of the calling CPU using
351 * only system register accesses.
352 ******************************************************************************/
gicv3_cpuif_disable(unsigned int proc_num)353 void gicv3_cpuif_disable(unsigned int proc_num)
354 {
355 uintptr_t gicr_base;
356
357 assert(gicv3_driver_data);
358 assert(proc_num < gicv3_driver_data->rdistif_num);
359 assert(gicv3_driver_data->rdistif_base_addrs);
360
361 assert(IS_IN_EL3());
362
363 /* Disable legacy interrupt bypass */
364 write_icc_sre_el3(read_icc_sre_el3() |
365 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT));
366
367 /* Disable Group0 interrupts */
368 write_icc_igrpen0_el1(read_icc_igrpen0_el1() &
369 ~IGRPEN1_EL1_ENABLE_G0_BIT);
370
371 /* Disable Group1 Secure and Non-Secure interrupts */
372 write_icc_igrpen1_el3(read_icc_igrpen1_el3() &
373 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT |
374 IGRPEN1_EL3_ENABLE_G1S_BIT));
375
376 /* Synchronise accesses to group enable registers */
377 isb();
378
379 /* Mark the connected core as asleep */
380 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
381 gicv3_rdistif_mark_core_asleep(gicr_base);
382 }
383
384 /*******************************************************************************
385 * This function returns the id of the highest priority pending interrupt at
386 * the GIC cpu interface.
387 ******************************************************************************/
gicv3_get_pending_interrupt_id(void)388 unsigned int gicv3_get_pending_interrupt_id(void)
389 {
390 unsigned int id;
391
392 assert(IS_IN_EL3());
393 id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
394
395 /*
396 * If the ID is special identifier corresponding to G1S or G1NS
397 * interrupt, then read the highest pending group 1 interrupt.
398 */
399 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID))
400 return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
401
402 return id;
403 }
404
405 /*******************************************************************************
406 * This function returns the type of the highest priority pending interrupt at
407 * the GIC cpu interface. The return values can be one of the following :
408 * PENDING_G1S_INTID : The interrupt type is secure Group 1.
409 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1.
410 * 0 - 1019 : The interrupt type is secure Group 0.
411 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with
412 * sufficient priority to be signaled
413 ******************************************************************************/
gicv3_get_pending_interrupt_type(void)414 unsigned int gicv3_get_pending_interrupt_type(void)
415 {
416 assert(IS_IN_EL3());
417 return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
418 }
419
420 /*******************************************************************************
421 * This function returns the type of the interrupt id depending upon the group
422 * this interrupt has been configured under by the interrupt controller i.e.
423 * group0 or group1 Secure / Non Secure. The return value can be one of the
424 * following :
425 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt
426 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt
427 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure
428 * interrupt.
429 ******************************************************************************/
gicv3_get_interrupt_type(unsigned int id,unsigned int proc_num)430 unsigned int gicv3_get_interrupt_type(unsigned int id,
431 unsigned int proc_num)
432 {
433 unsigned int igroup, grpmodr;
434 uintptr_t gicr_base;
435
436 assert(IS_IN_EL3());
437 assert(gicv3_driver_data);
438
439 /* Ensure the parameters are valid */
440 assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID);
441 assert(proc_num < gicv3_driver_data->rdistif_num);
442
443 /* All LPI interrupts are Group 1 non secure */
444 if (id >= MIN_LPI_ID)
445 return INTR_GROUP1NS;
446
447 if (id < MIN_SPI_ID) {
448 assert(gicv3_driver_data->rdistif_base_addrs);
449 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
450 igroup = gicr_get_igroupr0(gicr_base, id);
451 grpmodr = gicr_get_igrpmodr0(gicr_base, id);
452 } else {
453 assert(gicv3_driver_data->gicd_base);
454 igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id);
455 grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id);
456 }
457
458 /*
459 * If the IGROUP bit is set, then it is a Group 1 Non secure
460 * interrupt
461 */
462 if (igroup)
463 return INTR_GROUP1NS;
464
465 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */
466 if (grpmodr)
467 return INTR_GROUP1S;
468
469 /* Else it is a Group 0 Secure interrupt */
470 return INTR_GROUP0;
471 }
472
473 /*****************************************************************************
474 * Function to save and disable the GIC ITS register context. The power
475 * management of GIC ITS is implementation-defined and this function doesn't
476 * save any memory structures required to support ITS. As the sequence to save
477 * this state is implementation defined, it should be executed in platform
478 * specific code. Calling this function alone and then powering down the GIC and
479 * ITS without implementing the aforementioned platform specific code will
480 * corrupt the ITS state.
481 *
482 * This function must be invoked after the GIC CPU interface is disabled.
483 *****************************************************************************/
gicv3_its_save_disable(uintptr_t gits_base,gicv3_its_ctx_t * const its_ctx)484 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx)
485 {
486 int i;
487
488 assert(gicv3_driver_data);
489 assert(IS_IN_EL3());
490 assert(its_ctx);
491 assert(gits_base);
492
493 its_ctx->gits_ctlr = gits_read_ctlr(gits_base);
494
495 /* Disable the ITS */
496 gits_write_ctlr(gits_base, its_ctx->gits_ctlr &
497 (~GITS_CTLR_ENABLED_BIT));
498
499 /* Wait for quiescent state */
500 gits_wait_for_quiescent_bit(gits_base);
501
502 its_ctx->gits_cbaser = gits_read_cbaser(gits_base);
503 its_ctx->gits_cwriter = gits_read_cwriter(gits_base);
504
505 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++)
506 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i);
507 }
508
509 /*****************************************************************************
510 * Function to restore the GIC ITS register context. The power
511 * management of GIC ITS is implementation defined and this function doesn't
512 * restore any memory structures required to support ITS. The assumption is
513 * that these structures are in memory and are retained during system suspend.
514 *
515 * This must be invoked before the GIC CPU interface is enabled.
516 *****************************************************************************/
gicv3_its_restore(uintptr_t gits_base,const gicv3_its_ctx_t * const its_ctx)517 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx)
518 {
519 int i;
520
521 assert(gicv3_driver_data);
522 assert(IS_IN_EL3());
523 assert(its_ctx);
524 assert(gits_base);
525
526 /* Assert that the GITS is disabled and quiescent */
527 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0);
528 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0);
529
530 gits_write_cbaser(gits_base, its_ctx->gits_cbaser);
531 gits_write_cwriter(gits_base, its_ctx->gits_cwriter);
532
533 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++)
534 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]);
535
536 /* Restore the ITS CTLR but leave the ITS disabled */
537 gits_write_ctlr(gits_base, its_ctx->gits_ctlr &
538 (~GITS_CTLR_ENABLED_BIT));
539 }
540
541 /*****************************************************************************
542 * Function to save the GIC Redistributor register context. This function
543 * must be invoked after CPU interface disable and prior to Distributor save.
544 *****************************************************************************/
gicv3_rdistif_save(unsigned int proc_num,gicv3_redist_ctx_t * const rdist_ctx)545 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx)
546 {
547 uintptr_t gicr_base;
548 unsigned int int_id;
549
550 assert(gicv3_driver_data);
551 assert(proc_num < gicv3_driver_data->rdistif_num);
552 assert(gicv3_driver_data->rdistif_base_addrs);
553 assert(IS_IN_EL3());
554 assert(rdist_ctx);
555
556 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
557
558 /*
559 * Wait for any write to GICR_CTLR to complete before trying to save any
560 * state.
561 */
562 gicr_wait_for_pending_write(gicr_base);
563
564 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base);
565
566 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base);
567 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base);
568
569 rdist_ctx->gicr_igroupr0 = gicr_read_igroupr0(gicr_base);
570 rdist_ctx->gicr_isenabler0 = gicr_read_isenabler0(gicr_base);
571 rdist_ctx->gicr_ispendr0 = gicr_read_ispendr0(gicr_base);
572 rdist_ctx->gicr_isactiver0 = gicr_read_isactiver0(gicr_base);
573 rdist_ctx->gicr_icfgr0 = gicr_read_icfgr0(gicr_base);
574 rdist_ctx->gicr_icfgr1 = gicr_read_icfgr1(gicr_base);
575 rdist_ctx->gicr_igrpmodr0 = gicr_read_igrpmodr0(gicr_base);
576 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base);
577 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM;
578 int_id += (1 << IPRIORITYR_SHIFT)) {
579 rdist_ctx->gicr_ipriorityr[(int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT] =
580 gicr_read_ipriorityr(gicr_base, int_id);
581 }
582
583
584 /*
585 * Call the pre-save hook that implements the IMP DEF sequence that may
586 * be required on some GIC implementations. As this may need to access
587 * the Redistributor registers, we pass it proc_num.
588 */
589 gicv3_distif_pre_save(proc_num);
590 }
591
592 /*****************************************************************************
593 * Function to restore the GIC Redistributor register context. We disable
594 * LPI and per-cpu interrupts before we start restore of the Redistributor.
595 * This function must be invoked after Distributor restore but prior to
596 * CPU interface enable. The pending and active interrupts are restored
597 * after the interrupts are fully configured and enabled.
598 *****************************************************************************/
gicv3_rdistif_init_restore(unsigned int proc_num,const gicv3_redist_ctx_t * const rdist_ctx)599 void gicv3_rdistif_init_restore(unsigned int proc_num,
600 const gicv3_redist_ctx_t * const rdist_ctx)
601 {
602 uintptr_t gicr_base;
603 unsigned int int_id;
604
605 assert(gicv3_driver_data);
606 assert(proc_num < gicv3_driver_data->rdistif_num);
607 assert(gicv3_driver_data->rdistif_base_addrs);
608 assert(IS_IN_EL3());
609 assert(rdist_ctx);
610
611 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
612
613 /* Power on redistributor */
614 gicv3_rdistif_on(proc_num);
615
616 /*
617 * Call the post-restore hook that implements the IMP DEF sequence that
618 * may be required on some GIC implementations. As this may need to
619 * access the Redistributor registers, we pass it proc_num.
620 */
621 gicv3_distif_post_restore(proc_num);
622
623 /*
624 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a
625 * more scalable approach as it avoids clearing the enable bits in the
626 * GICD_CTLR
627 */
628 gicr_write_icenabler0(gicr_base, ~0);
629 /* Wait for pending writes to GICR_ICENABLER */
630 gicr_wait_for_pending_write(gicr_base);
631
632 /*
633 * Disable the LPIs to avoid unpredictable behavior when writing to
634 * GICR_PROPBASER and GICR_PENDBASER.
635 */
636 gicr_write_ctlr(gicr_base,
637 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT));
638
639 /* Restore registers' content */
640 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser);
641 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser);
642
643 gicr_write_igroupr0(gicr_base, rdist_ctx->gicr_igroupr0);
644
645 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM;
646 int_id += (1 << IPRIORITYR_SHIFT)) {
647 gicr_write_ipriorityr(gicr_base, int_id,
648 rdist_ctx->gicr_ipriorityr[
649 (int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT]);
650 }
651
652 gicr_write_icfgr0(gicr_base, rdist_ctx->gicr_icfgr0);
653 gicr_write_icfgr1(gicr_base, rdist_ctx->gicr_icfgr1);
654 gicr_write_igrpmodr0(gicr_base, rdist_ctx->gicr_igrpmodr0);
655 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr);
656
657 /* Restore after group and priorities are set */
658 gicr_write_ispendr0(gicr_base, rdist_ctx->gicr_ispendr0);
659 gicr_write_isactiver0(gicr_base, rdist_ctx->gicr_isactiver0);
660
661 /*
662 * Wait for all writes to the Distributor to complete before enabling
663 * the SGI and PPIs.
664 */
665 gicr_wait_for_upstream_pending_write(gicr_base);
666 gicr_write_isenabler0(gicr_base, rdist_ctx->gicr_isenabler0);
667
668 /*
669 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case
670 * the first write to GICR_CTLR was still in flight (this write only
671 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this
672 * bit).
673 */
674 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr);
675 gicr_wait_for_pending_write(gicr_base);
676 }
677
678 /*****************************************************************************
679 * Function to save the GIC Distributor register context. This function
680 * must be invoked after CPU interface disable and Redistributor save.
681 *****************************************************************************/
gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)682 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
683 {
684 unsigned int num_ints;
685
686 assert(gicv3_driver_data);
687 assert(gicv3_driver_data->gicd_base);
688 assert(IS_IN_EL3());
689 assert(dist_ctx);
690
691 uintptr_t gicd_base = gicv3_driver_data->gicd_base;
692
693 num_ints = gicd_read_typer(gicd_base);
694 num_ints &= TYPER_IT_LINES_NO_MASK;
695 num_ints = (num_ints + 1) << 5;
696
697 assert(num_ints <= MAX_SPI_ID + 1);
698
699 /* Wait for pending write to complete */
700 gicd_wait_for_pending_write(gicd_base);
701
702 /* Save the GICD_CTLR */
703 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base);
704
705 /* Save GICD_IGROUPR for INTIDs 32 - 1020 */
706 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR);
707
708 /* Save GICD_ISENABLER for INT_IDs 32 - 1020 */
709 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER);
710
711 /* Save GICD_ISPENDR for INTIDs 32 - 1020 */
712 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR);
713
714 /* Save GICD_ISACTIVER for INTIDs 32 - 1020 */
715 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER);
716
717 /* Save GICD_IPRIORITYR for INTIDs 32 - 1020 */
718 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR);
719
720 /* Save GICD_ICFGR for INTIDs 32 - 1020 */
721 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR);
722
723 /* Save GICD_IGRPMODR for INTIDs 32 - 1020 */
724 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR);
725
726 /* Save GICD_NSACR for INTIDs 32 - 1020 */
727 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR);
728
729 /* Save GICD_IROUTER for INTIDs 32 - 1024 */
730 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER);
731
732 /*
733 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when
734 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3
735 * driver.
736 */
737 }
738
739 /*****************************************************************************
740 * Function to restore the GIC Distributor register context. We disable G0, G1S
741 * and G1NS interrupt groups before we start restore of the Distributor. This
742 * function must be invoked prior to Redistributor restore and CPU interface
743 * enable. The pending and active interrupts are restored after the interrupts
744 * are fully configured and enabled.
745 *****************************************************************************/
gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)746 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
747 {
748 unsigned int num_ints = 0;
749
750 assert(gicv3_driver_data);
751 assert(gicv3_driver_data->gicd_base);
752 assert(IS_IN_EL3());
753 assert(dist_ctx);
754
755 uintptr_t gicd_base = gicv3_driver_data->gicd_base;
756
757 /*
758 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring
759 * the ARE_S bit. The Distributor might generate a system error
760 * otherwise.
761 */
762 gicd_clr_ctlr(gicd_base,
763 CTLR_ENABLE_G0_BIT |
764 CTLR_ENABLE_G1S_BIT |
765 CTLR_ENABLE_G1NS_BIT,
766 RWP_TRUE);
767
768 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
769 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE);
770
771 num_ints = gicd_read_typer(gicd_base);
772 num_ints &= TYPER_IT_LINES_NO_MASK;
773 num_ints = (num_ints + 1) << 5;
774
775 assert(num_ints <= MAX_SPI_ID + 1);
776
777 /* Restore GICD_IGROUPR for INTIDs 32 - 1020 */
778 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR);
779
780 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1020 */
781 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR);
782
783 /* Restore GICD_ICFGR for INTIDs 32 - 1020 */
784 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR);
785
786 /* Restore GICD_IGRPMODR for INTIDs 32 - 1020 */
787 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR);
788
789 /* Restore GICD_NSACR for INTIDs 32 - 1020 */
790 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR);
791
792 /* Restore GICD_IROUTER for INTIDs 32 - 1020 */
793 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER);
794
795 /*
796 * Restore ISENABLER, ISPENDR and ISACTIVER after the interrupts are
797 * configured.
798 */
799
800 /* Restore GICD_ISENABLER for INT_IDs 32 - 1020 */
801 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER);
802
803 /* Restore GICD_ISPENDR for INTIDs 32 - 1020 */
804 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR);
805
806 /* Restore GICD_ISACTIVER for INTIDs 32 - 1020 */
807 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER);
808
809 /* Restore the GICD_CTLR */
810 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr);
811 gicd_wait_for_pending_write(gicd_base);
812
813 }
814
815 /*******************************************************************************
816 * This function gets the priority of the interrupt the processor is currently
817 * servicing.
818 ******************************************************************************/
gicv3_get_running_priority(void)819 unsigned int gicv3_get_running_priority(void)
820 {
821 return read_icc_rpr_el1();
822 }
823
824 /*******************************************************************************
825 * This function checks if the interrupt identified by id is active (whether the
826 * state is either active, or active and pending). The proc_num is used if the
827 * interrupt is SGI or PPI and programs the corresponding Redistributor
828 * interface.
829 ******************************************************************************/
gicv3_get_interrupt_active(unsigned int id,unsigned int proc_num)830 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num)
831 {
832 unsigned int value;
833
834 assert(gicv3_driver_data);
835 assert(gicv3_driver_data->gicd_base);
836 assert(proc_num < gicv3_driver_data->rdistif_num);
837 assert(gicv3_driver_data->rdistif_base_addrs);
838 assert(id <= MAX_SPI_ID);
839
840 if (id < MIN_SPI_ID) {
841 /* For SGIs and PPIs */
842 value = gicr_get_isactiver0(
843 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
844 } else {
845 value = gicd_get_isactiver(gicv3_driver_data->gicd_base, id);
846 }
847
848 return value;
849 }
850
851 /*******************************************************************************
852 * This function enables the interrupt identified by id. The proc_num
853 * is used if the interrupt is SGI or PPI, and programs the corresponding
854 * Redistributor interface.
855 ******************************************************************************/
gicv3_enable_interrupt(unsigned int id,unsigned int proc_num)856 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num)
857 {
858 assert(gicv3_driver_data);
859 assert(gicv3_driver_data->gicd_base);
860 assert(proc_num < gicv3_driver_data->rdistif_num);
861 assert(gicv3_driver_data->rdistif_base_addrs);
862 assert(id <= MAX_SPI_ID);
863
864 /*
865 * Ensure that any shared variable updates depending on out of band
866 * interrupt trigger are observed before enabling interrupt.
867 */
868 dsbishst();
869 if (id < MIN_SPI_ID) {
870 /* For SGIs and PPIs */
871 gicr_set_isenabler0(
872 gicv3_driver_data->rdistif_base_addrs[proc_num],
873 id);
874 } else {
875 gicd_set_isenabler(gicv3_driver_data->gicd_base, id);
876 }
877 }
878
879 /*******************************************************************************
880 * This function disables the interrupt identified by id. The proc_num
881 * is used if the interrupt is SGI or PPI, and programs the corresponding
882 * Redistributor interface.
883 ******************************************************************************/
gicv3_disable_interrupt(unsigned int id,unsigned int proc_num)884 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num)
885 {
886 assert(gicv3_driver_data);
887 assert(gicv3_driver_data->gicd_base);
888 assert(proc_num < gicv3_driver_data->rdistif_num);
889 assert(gicv3_driver_data->rdistif_base_addrs);
890 assert(id <= MAX_SPI_ID);
891
892 /*
893 * Disable interrupt, and ensure that any shared variable updates
894 * depending on out of band interrupt trigger are observed afterwards.
895 */
896 if (id < MIN_SPI_ID) {
897 /* For SGIs and PPIs */
898 gicr_set_icenabler0(
899 gicv3_driver_data->rdistif_base_addrs[proc_num],
900 id);
901
902 /* Write to clear enable requires waiting for pending writes */
903 gicr_wait_for_pending_write(
904 gicv3_driver_data->rdistif_base_addrs[proc_num]);
905 } else {
906 gicd_set_icenabler(gicv3_driver_data->gicd_base, id);
907
908 /* Write to clear enable requires waiting for pending writes */
909 gicd_wait_for_pending_write(gicv3_driver_data->gicd_base);
910 }
911
912 dsbishst();
913 }
914
915 /*******************************************************************************
916 * This function sets the interrupt priority as supplied for the given interrupt
917 * id.
918 ******************************************************************************/
gicv3_set_interrupt_priority(unsigned int id,unsigned int proc_num,unsigned int priority)919 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
920 unsigned int priority)
921 {
922 uintptr_t gicr_base;
923
924 assert(gicv3_driver_data);
925 assert(gicv3_driver_data->gicd_base);
926 assert(proc_num < gicv3_driver_data->rdistif_num);
927 assert(gicv3_driver_data->rdistif_base_addrs);
928 assert(id <= MAX_SPI_ID);
929
930 if (id < MIN_SPI_ID) {
931 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
932 gicr_set_ipriorityr(gicr_base, id, priority);
933 } else {
934 gicd_set_ipriorityr(gicv3_driver_data->gicd_base, id, priority);
935 }
936 }
937
938 /*******************************************************************************
939 * This function assigns group for the interrupt identified by id. The proc_num
940 * is used if the interrupt is SGI or PPI, and programs the corresponding
941 * Redistributor interface. The group can be any of GICV3_INTR_GROUP*
942 ******************************************************************************/
gicv3_set_interrupt_type(unsigned int id,unsigned int proc_num,unsigned int type)943 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
944 unsigned int type)
945 {
946 unsigned int igroup = 0, grpmod = 0;
947 uintptr_t gicr_base;
948
949 assert(gicv3_driver_data);
950 assert(gicv3_driver_data->gicd_base);
951 assert(proc_num < gicv3_driver_data->rdistif_num);
952 assert(gicv3_driver_data->rdistif_base_addrs);
953
954 switch (type) {
955 case INTR_GROUP1S:
956 igroup = 0;
957 grpmod = 1;
958 break;
959 case INTR_GROUP0:
960 igroup = 0;
961 grpmod = 0;
962 break;
963 case INTR_GROUP1NS:
964 igroup = 1;
965 grpmod = 0;
966 break;
967 default:
968 assert(0);
969 }
970
971 if (id < MIN_SPI_ID) {
972 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
973 if (igroup)
974 gicr_set_igroupr0(gicr_base, id);
975 else
976 gicr_clr_igroupr0(gicr_base, id);
977
978 if (grpmod)
979 gicr_set_igrpmodr0(gicr_base, id);
980 else
981 gicr_clr_igrpmodr0(gicr_base, id);
982 } else {
983 /* Serialize read-modify-write to Distributor registers */
984 spin_lock(&gic_lock);
985 if (igroup)
986 gicd_set_igroupr(gicv3_driver_data->gicd_base, id);
987 else
988 gicd_clr_igroupr(gicv3_driver_data->gicd_base, id);
989
990 if (grpmod)
991 gicd_set_igrpmodr(gicv3_driver_data->gicd_base, id);
992 else
993 gicd_clr_igrpmodr(gicv3_driver_data->gicd_base, id);
994 spin_unlock(&gic_lock);
995 }
996 }
997
998 /*******************************************************************************
999 * This function raises the specified Secure Group 0 SGI.
1000 *
1001 * The target parameter must be a valid MPIDR in the system.
1002 ******************************************************************************/
gicv3_raise_secure_g0_sgi(int sgi_num,u_register_t target)1003 void gicv3_raise_secure_g0_sgi(int sgi_num, u_register_t target)
1004 {
1005 unsigned int tgt, aff3, aff2, aff1, aff0;
1006 uint64_t sgi_val;
1007
1008 /* Verify interrupt number is in the SGI range */
1009 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID));
1010
1011 /* Extract affinity fields from target */
1012 aff0 = MPIDR_AFFLVL0_VAL(target);
1013 aff1 = MPIDR_AFFLVL1_VAL(target);
1014 aff2 = MPIDR_AFFLVL2_VAL(target);
1015 aff3 = MPIDR_AFFLVL3_VAL(target);
1016
1017 /*
1018 * Make target list from affinity 0, and ensure GICv3 SGI can target
1019 * this PE.
1020 */
1021 assert(aff0 < GICV3_MAX_SGI_TARGETS);
1022 tgt = BIT(aff0);
1023
1024 /* Raise SGI to PE specified by its affinity */
1025 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF,
1026 tgt);
1027
1028 /*
1029 * Ensure that any shared variable updates depending on out of band
1030 * interrupt trigger are observed before raising SGI.
1031 */
1032 dsbishst();
1033 write_icc_sgi0r_el1(sgi_val);
1034 isb();
1035 }
1036
1037 /*******************************************************************************
1038 * This function sets the interrupt routing for the given SPI interrupt id.
1039 * The interrupt routing is specified in routing mode and mpidr.
1040 *
1041 * The routing mode can be either of:
1042 * - GICV3_IRM_ANY
1043 * - GICV3_IRM_PE
1044 *
1045 * The mpidr is the affinity of the PE to which the interrupt will be routed,
1046 * and is ignored for routing mode GICV3_IRM_ANY.
1047 ******************************************************************************/
gicv3_set_spi_routing(unsigned int id,unsigned int irm,u_register_t mpidr)1048 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr)
1049 {
1050 unsigned long long aff;
1051 uint64_t router;
1052
1053 assert(gicv3_driver_data);
1054 assert(gicv3_driver_data->gicd_base);
1055
1056 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE));
1057 assert(id >= MIN_SPI_ID && id <= MAX_SPI_ID);
1058
1059 aff = gicd_irouter_val_from_mpidr(mpidr, irm);
1060 gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff);
1061
1062 /*
1063 * In implementations that do not require 1 of N distribution of SPIs,
1064 * IRM might be RAZ/WI. Read back and verify IRM bit.
1065 */
1066 if (irm == GICV3_IRM_ANY) {
1067 router = gicd_read_irouter(gicv3_driver_data->gicd_base, id);
1068 if (!((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK)) {
1069 ERROR("GICv3 implementation doesn't support routing ANY\n");
1070 panic();
1071 }
1072 }
1073 }
1074
1075 /*******************************************************************************
1076 * This function clears the pending status of an interrupt identified by id.
1077 * The proc_num is used if the interrupt is SGI or PPI, and programs the
1078 * corresponding Redistributor interface.
1079 ******************************************************************************/
gicv3_clear_interrupt_pending(unsigned int id,unsigned int proc_num)1080 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num)
1081 {
1082 assert(gicv3_driver_data);
1083 assert(gicv3_driver_data->gicd_base);
1084 assert(proc_num < gicv3_driver_data->rdistif_num);
1085 assert(gicv3_driver_data->rdistif_base_addrs);
1086
1087 /*
1088 * Clear pending interrupt, and ensure that any shared variable updates
1089 * depending on out of band interrupt trigger are observed afterwards.
1090 */
1091 if (id < MIN_SPI_ID) {
1092 /* For SGIs and PPIs */
1093 gicr_set_icpendr0(gicv3_driver_data->rdistif_base_addrs[proc_num],
1094 id);
1095 } else {
1096 gicd_set_icpendr(gicv3_driver_data->gicd_base, id);
1097 }
1098 dsbishst();
1099 }
1100
1101 /*******************************************************************************
1102 * This function sets the pending status of an interrupt identified by id.
1103 * The proc_num is used if the interrupt is SGI or PPI and programs the
1104 * corresponding Redistributor interface.
1105 ******************************************************************************/
gicv3_set_interrupt_pending(unsigned int id,unsigned int proc_num)1106 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num)
1107 {
1108 assert(gicv3_driver_data);
1109 assert(gicv3_driver_data->gicd_base);
1110 assert(proc_num < gicv3_driver_data->rdistif_num);
1111 assert(gicv3_driver_data->rdistif_base_addrs);
1112
1113 /*
1114 * Ensure that any shared variable updates depending on out of band
1115 * interrupt trigger are observed before setting interrupt pending.
1116 */
1117 dsbishst();
1118 if (id < MIN_SPI_ID) {
1119 /* For SGIs and PPIs */
1120 gicr_set_ispendr0(gicv3_driver_data->rdistif_base_addrs[proc_num],
1121 id);
1122 } else {
1123 gicd_set_ispendr(gicv3_driver_data->gicd_base, id);
1124 }
1125 }
1126
1127 /*******************************************************************************
1128 * This function sets the PMR register with the supplied value. Returns the
1129 * original PMR.
1130 ******************************************************************************/
gicv3_set_pmr(unsigned int mask)1131 unsigned int gicv3_set_pmr(unsigned int mask)
1132 {
1133 unsigned int old_mask;
1134
1135 old_mask = read_icc_pmr_el1();
1136
1137 /*
1138 * Order memory updates w.r.t. PMR write, and ensure they're visible
1139 * before potential out of band interrupt trigger because of PMR update.
1140 * PMR system register writes are self-synchronizing, so no ISB required
1141 * thereafter.
1142 */
1143 dsbishst();
1144 write_icc_pmr_el1(mask);
1145
1146 return old_mask;
1147 }
1148