1 /**************************************************************************
2 *
3 * Copyright 2008 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include "draw/draw_context.h"
30 #include "os/os_misc.h"
31 #include "util/u_format.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_inlines.h"
34 #include "util/u_memory.h"
35 #include "util/u_string.h"
36
37 #include "i915_reg.h"
38 #include "i915_debug.h"
39 #include "i915_context.h"
40 #include "i915_screen.h"
41 #include "i915_resource.h"
42 #include "i915_winsys.h"
43 #include "i915_public.h"
44
45
46 /*
47 * Probe functions
48 */
49
50
51 static const char *
i915_get_vendor(struct pipe_screen * screen)52 i915_get_vendor(struct pipe_screen *screen)
53 {
54 return "Mesa Project";
55 }
56
57 static const char *
i915_get_device_vendor(struct pipe_screen * screen)58 i915_get_device_vendor(struct pipe_screen *screen)
59 {
60 return "Intel";
61 }
62
63 static const char *
i915_get_name(struct pipe_screen * screen)64 i915_get_name(struct pipe_screen *screen)
65 {
66 static char buffer[128];
67 const char *chipset;
68
69 switch (i915_screen(screen)->iws->pci_id) {
70 case PCI_CHIP_I915_G:
71 chipset = "915G";
72 break;
73 case PCI_CHIP_I915_GM:
74 chipset = "915GM";
75 break;
76 case PCI_CHIP_I945_G:
77 chipset = "945G";
78 break;
79 case PCI_CHIP_I945_GM:
80 chipset = "945GM";
81 break;
82 case PCI_CHIP_I945_GME:
83 chipset = "945GME";
84 break;
85 case PCI_CHIP_G33_G:
86 chipset = "G33";
87 break;
88 case PCI_CHIP_Q35_G:
89 chipset = "Q35";
90 break;
91 case PCI_CHIP_Q33_G:
92 chipset = "Q33";
93 break;
94 case PCI_CHIP_PINEVIEW_G:
95 chipset = "Pineview G";
96 break;
97 case PCI_CHIP_PINEVIEW_M:
98 chipset = "Pineview M";
99 break;
100 default:
101 chipset = "unknown";
102 break;
103 }
104
105 util_snprintf(buffer, sizeof(buffer), "i915 (chipset: %s)", chipset);
106 return buffer;
107 }
108
109 static int
i915_get_shader_param(struct pipe_screen * screen,enum pipe_shader_type shader,enum pipe_shader_cap cap)110 i915_get_shader_param(struct pipe_screen *screen,
111 enum pipe_shader_type shader,
112 enum pipe_shader_cap cap)
113 {
114 switch(shader) {
115 case PIPE_SHADER_VERTEX:
116 switch (cap) {
117 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
118 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
119 if (debug_get_bool_option("DRAW_USE_LLVM", TRUE))
120 return PIPE_MAX_SAMPLERS;
121 else
122 return 0;
123 default:
124 return draw_get_shader_param(shader, cap);
125 }
126 case PIPE_SHADER_FRAGMENT:
127 /* XXX: some of these are just shader model 2.0 values, fix this! */
128 switch(cap) {
129 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
130 return I915_MAX_ALU_INSN + I915_MAX_TEX_INSN;
131 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
132 return I915_MAX_ALU_INSN;
133 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
134 return I915_MAX_TEX_INSN;
135 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
136 return 8;
137 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
138 return 0;
139 case PIPE_SHADER_CAP_MAX_INPUTS:
140 return 10;
141 case PIPE_SHADER_CAP_MAX_OUTPUTS:
142 return 1;
143 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
144 return 32 * sizeof(float[4]);
145 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
146 return 1;
147 case PIPE_SHADER_CAP_MAX_TEMPS:
148 return 12; /* XXX: 12 -> 32 ? */
149 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
150 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
151 return 0;
152 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
153 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
154 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
155 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
156 return 1;
157 case PIPE_SHADER_CAP_SUBROUTINES:
158 return 0;
159 case PIPE_SHADER_CAP_INTEGERS:
160 case PIPE_SHADER_CAP_INT64_ATOMICS:
161 case PIPE_SHADER_CAP_FP16:
162 return 0;
163 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
164 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
165 return I915_TEX_UNITS;
166 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
167 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
168 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
169 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
170 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
171 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
172 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
173 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
174 case PIPE_SHADER_CAP_PREFERRED_IR:
175 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
176 return 0;
177 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
178 return 32;
179 default:
180 debug_printf("%s: Unknown cap %u.\n", __FUNCTION__, cap);
181 return 0;
182 }
183 break;
184 default:
185 return 0;
186 }
187
188 }
189
190 static int
i915_get_param(struct pipe_screen * screen,enum pipe_cap cap)191 i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
192 {
193 struct i915_screen *is = i915_screen(screen);
194
195 switch (cap) {
196 /* Supported features (boolean caps). */
197 case PIPE_CAP_ANISOTROPIC_FILTER:
198 case PIPE_CAP_NPOT_TEXTURES:
199 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
200 case PIPE_CAP_POINT_SPRITE:
201 case PIPE_CAP_PRIMITIVE_RESTART: /* draw module */
202 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
203 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
204 case PIPE_CAP_TGSI_INSTANCEID:
205 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
206 case PIPE_CAP_USER_VERTEX_BUFFERS:
207 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
208 return 1;
209
210 /* Unsupported features (boolean caps). */
211 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
212 case PIPE_CAP_DEPTH_CLIP_DISABLE:
213 case PIPE_CAP_INDEP_BLEND_ENABLE:
214 case PIPE_CAP_INDEP_BLEND_FUNC:
215 case PIPE_CAP_SHADER_STENCIL_EXPORT:
216 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
217 case PIPE_CAP_TEXTURE_SWIZZLE:
218 case PIPE_CAP_QUERY_TIME_ELAPSED:
219 case PIPE_CAP_SM3:
220 case PIPE_CAP_SEAMLESS_CUBE_MAP:
221 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
222 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
223 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
224 case PIPE_CAP_CONDITIONAL_RENDER:
225 case PIPE_CAP_TEXTURE_BARRIER:
226 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
227 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
228 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
229 case PIPE_CAP_START_INSTANCE:
230 case PIPE_CAP_QUERY_TIMESTAMP:
231 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
232 case PIPE_CAP_TEXTURE_MULTISAMPLE:
233 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
234 case PIPE_CAP_CUBE_MAP_ARRAY:
235 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
236 case PIPE_CAP_TGSI_TEXCOORD:
237 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
238 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
239 case PIPE_CAP_TEXTURE_GATHER_SM5:
240 case PIPE_CAP_FAKE_SW_MSAA:
241 case PIPE_CAP_TEXTURE_QUERY_LOD:
242 case PIPE_CAP_SAMPLE_SHADING:
243 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
244 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
245 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
246 case PIPE_CAP_CLIP_HALFZ:
247 case PIPE_CAP_VERTEXID_NOBASE:
248 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
249 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
250 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
251 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
252 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
253 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
254 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
255 case PIPE_CAP_DEPTH_BOUNDS_TEST:
256 case PIPE_CAP_TGSI_TXQS:
257 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
258 case PIPE_CAP_SHAREABLE_SHADERS:
259 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
260 case PIPE_CAP_CLEAR_TEXTURE:
261 case PIPE_CAP_DRAW_PARAMETERS:
262 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
263 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
264 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
265 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
266 case PIPE_CAP_INVALIDATE_BUFFER:
267 case PIPE_CAP_GENERATE_MIPMAP:
268 case PIPE_CAP_STRING_MARKER:
269 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
270 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
271 case PIPE_CAP_QUERY_MEMORY_INFO:
272 case PIPE_CAP_PCI_GROUP:
273 case PIPE_CAP_PCI_BUS:
274 case PIPE_CAP_PCI_DEVICE:
275 case PIPE_CAP_PCI_FUNCTION:
276 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
277 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
278 case PIPE_CAP_CULL_DISTANCE:
279 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
280 case PIPE_CAP_TGSI_VOTE:
281 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
282 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
283 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
284 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
285 case PIPE_CAP_POST_DEPTH_COVERAGE:
286 return 0;
287
288 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
289 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
290 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
291 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
292 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
293 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
294 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
295 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
296 case PIPE_CAP_DRAW_INDIRECT:
297 case PIPE_CAP_MULTI_DRAW_INDIRECT:
298 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
299 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
300 case PIPE_CAP_SAMPLER_VIEW_TARGET:
301 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
302 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
303 case PIPE_CAP_NATIVE_FENCE_FD:
304 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
305 case PIPE_CAP_TGSI_FS_FBFETCH:
306 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
307 case PIPE_CAP_DOUBLES:
308 case PIPE_CAP_INT64:
309 case PIPE_CAP_INT64_DIVMOD:
310 case PIPE_CAP_TGSI_TEX_TXF_LZ:
311 case PIPE_CAP_TGSI_CLOCK:
312 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
313 case PIPE_CAP_TGSI_BALLOT:
314 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
315 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
316 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
317 case PIPE_CAP_BINDLESS_TEXTURE:
318 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
319 case PIPE_CAP_QUERY_SO_OVERFLOW:
320 case PIPE_CAP_MEMOBJ:
321 case PIPE_CAP_LOAD_CONSTBUF:
322 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
323 case PIPE_CAP_TILE_RASTER_ORDER:
324 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
325 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
326 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
327 return 0;
328
329 case PIPE_CAP_MAX_VIEWPORTS:
330 return 1;
331
332 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
333 return 64;
334
335 case PIPE_CAP_GLSL_FEATURE_LEVEL:
336 return 120;
337
338 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
339 return 16;
340
341 /* Features we can lie about (boolean caps). */
342 case PIPE_CAP_OCCLUSION_QUERY:
343 return is->debug.lie ? 1 : 0;
344
345 /* Texturing. */
346 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
347 return I915_MAX_TEXTURE_2D_LEVELS;
348 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
349 return I915_MAX_TEXTURE_3D_LEVELS;
350 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
351 return I915_MAX_TEXTURE_2D_LEVELS;
352 case PIPE_CAP_MIN_TEXEL_OFFSET:
353 case PIPE_CAP_MAX_TEXEL_OFFSET:
354 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
355 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
356 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
357 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
358 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
359 return 0;
360
361 /* Render targets. */
362 case PIPE_CAP_MAX_RENDER_TARGETS:
363 return 1;
364
365 /* Geometry shader output, unsupported. */
366 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
367 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
368 case PIPE_CAP_MAX_VERTEX_STREAMS:
369 return 0;
370
371 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
372 return 2048;
373
374 /* Fragment coordinate conventions. */
375 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
376 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
377 return 1;
378 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
379 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
380 return 0;
381 case PIPE_CAP_ENDIANNESS:
382 return PIPE_ENDIAN_LITTLE;
383
384 case PIPE_CAP_VENDOR_ID:
385 return 0x8086;
386 case PIPE_CAP_DEVICE_ID:
387 return is->iws->pci_id;
388 case PIPE_CAP_ACCELERATED:
389 return 1;
390 case PIPE_CAP_VIDEO_MEMORY: {
391 /* Once a batch uses more than 75% of the maximum mappable size, we
392 * assume that there's some fragmentation, and we start doing extra
393 * flushing, etc. That's the big cliff apps will care about.
394 */
395 const int gpu_mappable_megabytes = is->iws->aperture_size(is->iws) * 3 / 4;
396 uint64_t system_memory;
397
398 if (!os_get_total_physical_memory(&system_memory))
399 return 0;
400
401 return MIN2(gpu_mappable_megabytes, (int)(system_memory >> 20));
402 }
403 case PIPE_CAP_UMA:
404 return 1;
405
406 case PIPE_CAP_COMPUTE:
407 case PIPE_CAP_QUERY_BUFFER_OBJECT:
408 return 0;
409 default:
410 debug_printf("%s: Unknown cap %u.\n", __FUNCTION__, cap);
411 return 0;
412 }
413 }
414
415 static float
i915_get_paramf(struct pipe_screen * screen,enum pipe_capf cap)416 i915_get_paramf(struct pipe_screen *screen, enum pipe_capf cap)
417 {
418 switch(cap) {
419 case PIPE_CAPF_MAX_LINE_WIDTH:
420 /* fall-through */
421 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
422 return 7.5;
423
424 case PIPE_CAPF_MAX_POINT_WIDTH:
425 /* fall-through */
426 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
427 return 255.0;
428
429 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
430 return 4.0;
431
432 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
433 return 16.0;
434
435 default:
436 debug_printf("%s: Unknown cap %u.\n", __FUNCTION__, cap);
437 return 0;
438 }
439 }
440
441 boolean
i915_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned tex_usage)442 i915_is_format_supported(struct pipe_screen *screen,
443 enum pipe_format format,
444 enum pipe_texture_target target,
445 unsigned sample_count,
446 unsigned tex_usage)
447 {
448 static const enum pipe_format tex_supported[] = {
449 PIPE_FORMAT_B8G8R8A8_UNORM,
450 PIPE_FORMAT_B8G8R8A8_SRGB,
451 PIPE_FORMAT_B8G8R8X8_UNORM,
452 PIPE_FORMAT_R8G8B8A8_UNORM,
453 PIPE_FORMAT_R8G8B8X8_UNORM,
454 PIPE_FORMAT_B4G4R4A4_UNORM,
455 PIPE_FORMAT_B5G6R5_UNORM,
456 PIPE_FORMAT_B5G5R5A1_UNORM,
457 PIPE_FORMAT_B10G10R10A2_UNORM,
458 PIPE_FORMAT_L8_UNORM,
459 PIPE_FORMAT_A8_UNORM,
460 PIPE_FORMAT_I8_UNORM,
461 PIPE_FORMAT_L8A8_UNORM,
462 PIPE_FORMAT_UYVY,
463 PIPE_FORMAT_YUYV,
464 /* XXX why not?
465 PIPE_FORMAT_Z16_UNORM, */
466 PIPE_FORMAT_DXT1_RGB,
467 PIPE_FORMAT_DXT1_RGBA,
468 PIPE_FORMAT_DXT3_RGBA,
469 PIPE_FORMAT_DXT5_RGBA,
470 PIPE_FORMAT_Z24X8_UNORM,
471 PIPE_FORMAT_Z24_UNORM_S8_UINT,
472 PIPE_FORMAT_NONE /* list terminator */
473 };
474 static const enum pipe_format render_supported[] = {
475 PIPE_FORMAT_B8G8R8A8_UNORM,
476 PIPE_FORMAT_B8G8R8X8_UNORM,
477 PIPE_FORMAT_R8G8B8A8_UNORM,
478 PIPE_FORMAT_R8G8B8X8_UNORM,
479 PIPE_FORMAT_B5G6R5_UNORM,
480 PIPE_FORMAT_B5G5R5A1_UNORM,
481 PIPE_FORMAT_B4G4R4A4_UNORM,
482 PIPE_FORMAT_B10G10R10A2_UNORM,
483 PIPE_FORMAT_L8_UNORM,
484 PIPE_FORMAT_A8_UNORM,
485 PIPE_FORMAT_I8_UNORM,
486 PIPE_FORMAT_NONE /* list terminator */
487 };
488 static const enum pipe_format depth_supported[] = {
489 /* XXX why not?
490 PIPE_FORMAT_Z16_UNORM, */
491 PIPE_FORMAT_Z24X8_UNORM,
492 PIPE_FORMAT_Z24_UNORM_S8_UINT,
493 PIPE_FORMAT_NONE /* list terminator */
494 };
495 const enum pipe_format *list;
496 uint i;
497
498 if (!util_format_is_supported(format, tex_usage))
499 return FALSE;
500
501 if (sample_count > 1)
502 return FALSE;
503
504 if(tex_usage & PIPE_BIND_DEPTH_STENCIL)
505 list = depth_supported;
506 else if (tex_usage & PIPE_BIND_RENDER_TARGET)
507 list = render_supported;
508 else if (tex_usage & PIPE_BIND_SAMPLER_VIEW)
509 list = tex_supported;
510 else
511 return TRUE; /* PIPE_BIND_{VERTEX,INDEX}_BUFFER */
512
513 for (i = 0; list[i] != PIPE_FORMAT_NONE; i++) {
514 if (list[i] == format)
515 return TRUE;
516 }
517
518 return FALSE;
519 }
520
521
522 /*
523 * Fence functions
524 */
525
526
527 static void
i915_fence_reference(struct pipe_screen * screen,struct pipe_fence_handle ** ptr,struct pipe_fence_handle * fence)528 i915_fence_reference(struct pipe_screen *screen,
529 struct pipe_fence_handle **ptr,
530 struct pipe_fence_handle *fence)
531 {
532 struct i915_screen *is = i915_screen(screen);
533
534 is->iws->fence_reference(is->iws, ptr, fence);
535 }
536
537 static boolean
i915_fence_finish(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_fence_handle * fence,uint64_t timeout)538 i915_fence_finish(struct pipe_screen *screen,
539 struct pipe_context *ctx,
540 struct pipe_fence_handle *fence,
541 uint64_t timeout)
542 {
543 struct i915_screen *is = i915_screen(screen);
544
545 if (!timeout)
546 return is->iws->fence_signalled(is->iws, fence) == 1;
547
548 return is->iws->fence_finish(is->iws, fence) == 1;
549 }
550
551
552 /*
553 * Generic functions
554 */
555
556
557 static void
i915_flush_frontbuffer(struct pipe_screen * screen,struct pipe_resource * resource,unsigned level,unsigned layer,void * winsys_drawable_handle,struct pipe_box * sub_box)558 i915_flush_frontbuffer(struct pipe_screen *screen,
559 struct pipe_resource *resource,
560 unsigned level, unsigned layer,
561 void *winsys_drawable_handle,
562 struct pipe_box *sub_box)
563 {
564 /* XXX: Dummy right now. */
565 (void)screen;
566 (void)resource;
567 (void)level;
568 (void)layer;
569 (void)winsys_drawable_handle;
570 (void)sub_box;
571 }
572
573 static void
i915_destroy_screen(struct pipe_screen * screen)574 i915_destroy_screen(struct pipe_screen *screen)
575 {
576 struct i915_screen *is = i915_screen(screen);
577
578 if (is->iws)
579 is->iws->destroy(is->iws);
580
581 FREE(is);
582 }
583
584 /**
585 * Create a new i915_screen object
586 */
587 struct pipe_screen *
i915_screen_create(struct i915_winsys * iws)588 i915_screen_create(struct i915_winsys *iws)
589 {
590 struct i915_screen *is = CALLOC_STRUCT(i915_screen);
591
592 if (!is)
593 return NULL;
594
595 switch (iws->pci_id) {
596 case PCI_CHIP_I915_G:
597 case PCI_CHIP_I915_GM:
598 is->is_i945 = FALSE;
599 break;
600
601 case PCI_CHIP_I945_G:
602 case PCI_CHIP_I945_GM:
603 case PCI_CHIP_I945_GME:
604 case PCI_CHIP_G33_G:
605 case PCI_CHIP_Q33_G:
606 case PCI_CHIP_Q35_G:
607 case PCI_CHIP_PINEVIEW_G:
608 case PCI_CHIP_PINEVIEW_M:
609 is->is_i945 = TRUE;
610 break;
611
612 default:
613 debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
614 __FUNCTION__, iws->pci_id);
615 FREE(is);
616 return NULL;
617 }
618
619 is->iws = iws;
620
621 is->base.destroy = i915_destroy_screen;
622 is->base.flush_frontbuffer = i915_flush_frontbuffer;
623
624 is->base.get_name = i915_get_name;
625 is->base.get_vendor = i915_get_vendor;
626 is->base.get_device_vendor = i915_get_device_vendor;
627 is->base.get_param = i915_get_param;
628 is->base.get_shader_param = i915_get_shader_param;
629 is->base.get_paramf = i915_get_paramf;
630 is->base.is_format_supported = i915_is_format_supported;
631
632 is->base.context_create = i915_create_context;
633
634 is->base.fence_reference = i915_fence_reference;
635 is->base.fence_finish = i915_fence_finish;
636
637 i915_init_screen_resource_functions(is);
638
639 i915_debug_init(is);
640
641 return &is->base;
642 }
643