1 /**************************************************************************
2 *
3 * Copyright 2003 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29
30 #include "main/glheader.h"
31 #include "main/mtypes.h"
32 #include "main/imports.h"
33 #include "main/macros.h"
34 #include "main/renderbuffer.h"
35 #include "main/framebuffer.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_context.h"
39 #include "tnl/t_vertex.h"
40 #include "swrast_setup/swrast_setup.h"
41
42 #include "intel_batchbuffer.h"
43 #include "intel_mipmap_tree.h"
44 #include "intel_regions.h"
45 #include "intel_tris.h"
46 #include "intel_fbo.h"
47 #include "intel_buffers.h"
48
49 #include "i915_reg.h"
50 #include "i915_context.h"
51
52 static void
i915_render_prevalidate(struct intel_context * intel)53 i915_render_prevalidate(struct intel_context *intel)
54 {
55 struct i915_context *i915 = i915_context(&intel->ctx);
56
57 i915ValidateFragmentProgram(i915);
58 }
59
60 static void
i915_render_start(struct intel_context * intel)61 i915_render_start(struct intel_context *intel)
62 {
63 intel_prepare_render(intel);
64 }
65
66
67 static void
i915_reduced_primitive_state(struct intel_context * intel,GLenum rprim)68 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
69 {
70 struct i915_context *i915 = i915_context(&intel->ctx);
71 GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
72
73 st1 &= ~ST1_ENABLE;
74
75 switch (rprim) {
76 case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
77 case GL_TRIANGLES:
78 if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
79 st1 |= ST1_ENABLE;
80 break;
81 case GL_LINES:
82 case GL_POINTS:
83 default:
84 break;
85 }
86
87 i915->intel.reduced_primitive = rprim;
88
89 if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
90 INTEL_FIREVERTICES(intel);
91
92 I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
93 i915->state.Stipple[I915_STPREG_ST1] = st1;
94 }
95 }
96
97
98 /* Pull apart the vertex format registers and figure out how large a
99 * vertex is supposed to be.
100 */
101 static bool
i915_check_vertex_size(struct intel_context * intel,GLuint expected)102 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
103 {
104 struct i915_context *i915 = i915_context(&intel->ctx);
105 int lis2 = i915->state.Ctx[I915_CTXREG_LIS2];
106 int lis4 = i915->state.Ctx[I915_CTXREG_LIS4];
107 int i, sz = 0;
108
109 switch (lis4 & S4_VFMT_XYZW_MASK) {
110 case S4_VFMT_XY:
111 sz = 2;
112 break;
113 case S4_VFMT_XYZ:
114 sz = 3;
115 break;
116 case S4_VFMT_XYW:
117 sz = 3;
118 break;
119 case S4_VFMT_XYZW:
120 sz = 4;
121 break;
122 default:
123 fprintf(stderr, "no xyzw specified\n");
124 return 0;
125 }
126
127 if (lis4 & S4_VFMT_SPEC_FOG)
128 sz++;
129 if (lis4 & S4_VFMT_COLOR)
130 sz++;
131 if (lis4 & S4_VFMT_DEPTH_OFFSET)
132 sz++;
133 if (lis4 & S4_VFMT_POINT_WIDTH)
134 sz++;
135 if (lis4 & S4_VFMT_FOG_PARAM)
136 sz++;
137
138 for (i = 0; i < 8; i++) {
139 switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
140 case TEXCOORDFMT_2D:
141 sz += 2;
142 break;
143 case TEXCOORDFMT_3D:
144 sz += 3;
145 break;
146 case TEXCOORDFMT_4D:
147 sz += 4;
148 break;
149 case TEXCOORDFMT_1D:
150 sz += 1;
151 break;
152 case TEXCOORDFMT_2D_16:
153 sz += 1;
154 break;
155 case TEXCOORDFMT_4D_16:
156 sz += 2;
157 break;
158 case TEXCOORDFMT_NOT_PRESENT:
159 break;
160 default:
161 fprintf(stderr, "bad texcoord fmt %d\n", i);
162 return false;
163 }
164 lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
165 }
166
167 if (sz != expected)
168 fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
169
170 return sz == expected;
171 }
172
173
174 static void
i915_emit_invarient_state(struct intel_context * intel)175 i915_emit_invarient_state(struct intel_context *intel)
176 {
177 BATCH_LOCALS;
178
179 BEGIN_BATCH(15);
180
181 OUT_BATCH(_3DSTATE_AA_CMD |
182 AA_LINE_ECAAR_WIDTH_ENABLE |
183 AA_LINE_ECAAR_WIDTH_1_0 |
184 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
185
186 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
187 OUT_BATCH(0);
188
189 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
190 OUT_BATCH(0);
191
192 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
193 OUT_BATCH(0);
194
195 /* Don't support texture crossbar yet */
196 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
197 CSB_TCB(0, 0) |
198 CSB_TCB(1, 1) |
199 CSB_TCB(2, 2) |
200 CSB_TCB(3, 3) |
201 CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
202
203 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
204 OUT_BATCH(0);
205 OUT_BATCH(0);
206
207 /* XXX: Use this */
208 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
209
210 OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
211
212 OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
213 OUT_BATCH(0);
214
215 ADVANCE_BATCH();
216 }
217
218
219 #define emit(intel, state, size ) \
220 intel_batchbuffer_data(intel, state, size)
221
222 static GLuint
get_dirty(struct i915_hw_state * state)223 get_dirty(struct i915_hw_state *state)
224 {
225 GLuint dirty;
226
227 /* Workaround the multitex hang - if one texture unit state is
228 * modified, emit all texture units.
229 */
230 dirty = state->active & ~state->emitted;
231 if (dirty & I915_UPLOAD_TEX_ALL)
232 state->emitted &= ~I915_UPLOAD_TEX_ALL;
233 dirty = state->active & ~state->emitted;
234 return dirty;
235 }
236
237
238 static GLuint
get_state_size(struct i915_hw_state * state)239 get_state_size(struct i915_hw_state *state)
240 {
241 GLuint dirty = get_dirty(state);
242 GLuint i;
243 GLuint sz = 0;
244
245 if (dirty & I915_UPLOAD_INVARIENT)
246 sz += 30 * 4;
247
248 if (dirty & I915_UPLOAD_RASTER_RULES)
249 sz += sizeof(state->RasterRules);
250
251 if (dirty & I915_UPLOAD_CTX)
252 sz += sizeof(state->Ctx);
253
254 if (dirty & I915_UPLOAD_BLEND)
255 sz += sizeof(state->Blend);
256
257 if (dirty & I915_UPLOAD_BUFFERS)
258 sz += sizeof(state->Buffer);
259
260 if (dirty & I915_UPLOAD_STIPPLE)
261 sz += sizeof(state->Stipple);
262
263 if (dirty & I915_UPLOAD_TEX_ALL) {
264 int nr = 0;
265 for (i = 0; i < I915_TEX_UNITS; i++)
266 if (dirty & I915_UPLOAD_TEX(i))
267 nr++;
268
269 sz += (2 + nr * 3) * sizeof(GLuint) * 2;
270 }
271
272 if (dirty & I915_UPLOAD_CONSTANTS)
273 sz += state->ConstantSize * sizeof(GLuint);
274
275 if (dirty & I915_UPLOAD_PROGRAM)
276 sz += state->ProgramSize * sizeof(GLuint);
277
278 return sz;
279 }
280
281 /* Push the state into the sarea and/or texture memory.
282 */
283 static void
i915_emit_state(struct intel_context * intel)284 i915_emit_state(struct intel_context *intel)
285 {
286 struct i915_context *i915 = i915_context(&intel->ctx);
287 struct i915_hw_state *state = &i915->state;
288 int i, count, aper_count;
289 GLuint dirty;
290 drm_intel_bo *aper_array[3 + I915_TEX_UNITS];
291 GET_CURRENT_CONTEXT(ctx);
292 BATCH_LOCALS;
293
294 /* We don't hold the lock at this point, so want to make sure that
295 * there won't be a buffer wrap between the state emits and the primitive
296 * emit header.
297 *
298 * It might be better to talk about explicit places where
299 * scheduling is allowed, rather than assume that it is whenever a
300 * batchbuffer fills up.
301 */
302 intel_batchbuffer_require_space(intel,
303 get_state_size(state) +
304 INTEL_PRIM_EMIT_SIZE);
305 count = 0;
306 again:
307 if (intel->batch.bo == NULL) {
308 _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
309 assert(0);
310 }
311 aper_count = 0;
312 dirty = get_dirty(state);
313
314 aper_array[aper_count++] = intel->batch.bo;
315 if (dirty & I915_UPLOAD_BUFFERS) {
316 if (state->draw_region)
317 aper_array[aper_count++] = state->draw_region->bo;
318 if (state->depth_region)
319 aper_array[aper_count++] = state->depth_region->bo;
320 }
321
322 if (dirty & I915_UPLOAD_TEX_ALL) {
323 for (i = 0; i < I915_TEX_UNITS; i++) {
324 if (dirty & I915_UPLOAD_TEX(i)) {
325 if (state->tex_buffer[i]) {
326 aper_array[aper_count++] = state->tex_buffer[i];
327 }
328 }
329 }
330 }
331
332 if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
333 if (count == 0) {
334 count++;
335 intel_batchbuffer_flush(intel);
336 goto again;
337 } else {
338 _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
339 assert(0);
340 }
341 }
342
343 /* work out list of buffers to emit */
344
345 /* Do this here as we may have flushed the batchbuffer above,
346 * causing more state to be dirty!
347 */
348 dirty = get_dirty(state);
349 state->emitted |= dirty;
350 assert(get_dirty(state) == 0);
351
352 if (INTEL_DEBUG & DEBUG_STATE)
353 fprintf(stderr, "%s dirty: %x\n", __func__, dirty);
354
355 if (dirty & I915_UPLOAD_INVARIENT) {
356 if (INTEL_DEBUG & DEBUG_STATE)
357 fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
358 i915_emit_invarient_state(intel);
359 }
360
361 if (dirty & I915_UPLOAD_RASTER_RULES) {
362 if (INTEL_DEBUG & DEBUG_STATE)
363 fprintf(stderr, "I915_UPLOAD_RASTER_RULES:\n");
364 emit(intel, state->RasterRules, sizeof(state->RasterRules));
365 }
366
367 if (dirty & I915_UPLOAD_CTX) {
368 if (INTEL_DEBUG & DEBUG_STATE)
369 fprintf(stderr, "I915_UPLOAD_CTX:\n");
370
371 emit(intel, state->Ctx, sizeof(state->Ctx));
372 }
373
374 if (dirty & I915_UPLOAD_BLEND) {
375 if (INTEL_DEBUG & DEBUG_STATE)
376 fprintf(stderr, "I915_UPLOAD_BLEND:\n");
377
378 emit(intel, state->Blend, sizeof(state->Blend));
379 }
380
381 if (dirty & I915_UPLOAD_BUFFERS) {
382 GLuint count;
383
384 if (INTEL_DEBUG & DEBUG_STATE)
385 fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
386
387 count = 17;
388 if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
389 count++;
390
391 BEGIN_BATCH(count);
392 OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
393 OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
394 if (state->draw_region) {
395 OUT_RELOC(state->draw_region->bo,
396 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
397 } else {
398 OUT_BATCH(0);
399 }
400
401 OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
402 OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
403 if (state->depth_region) {
404 OUT_RELOC(state->depth_region->bo,
405 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
406 } else {
407 OUT_BATCH(0);
408 }
409
410 OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
411 OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
412 OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
413 OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
414 OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
415 OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
416
417 if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
418 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
419 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
420 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
421 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
422 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
423 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
424
425 ADVANCE_BATCH();
426 }
427
428 if (dirty & I915_UPLOAD_STIPPLE) {
429 if (INTEL_DEBUG & DEBUG_STATE)
430 fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
431 emit(intel, state->Stipple, sizeof(state->Stipple));
432 }
433
434 /* Combine all the dirty texture state into a single command to
435 * avoid lockups on I915 hardware.
436 */
437 if (dirty & I915_UPLOAD_TEX_ALL) {
438 int nr = 0;
439 GLuint unwind;
440
441 for (i = 0; i < I915_TEX_UNITS; i++)
442 if (dirty & I915_UPLOAD_TEX(i))
443 nr++;
444
445 BEGIN_BATCH(2 + nr * 3);
446 OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
447 OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
448 for (i = 0; i < I915_TEX_UNITS; i++)
449 if (dirty & I915_UPLOAD_TEX(i)) {
450 OUT_RELOC(state->tex_buffer[i],
451 I915_GEM_DOMAIN_SAMPLER, 0,
452 state->tex_offset[i]);
453
454 OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
455 OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
456 }
457 ADVANCE_BATCH();
458
459 unwind = intel->batch.used;
460 BEGIN_BATCH(2 + nr * 3);
461 OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
462 OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
463 for (i = 0; i < I915_TEX_UNITS; i++)
464 if (dirty & I915_UPLOAD_TEX(i)) {
465 OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
466 OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
467 OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
468 }
469 ADVANCE_BATCH();
470 if (i915->last_sampler &&
471 memcmp(intel->batch.map + i915->last_sampler,
472 intel->batch.map + unwind,
473 (2 + nr*3)*sizeof(int)) == 0)
474 intel->batch.used = unwind;
475 else
476 i915->last_sampler = unwind;
477 }
478
479 if (dirty & I915_UPLOAD_CONSTANTS) {
480 if (INTEL_DEBUG & DEBUG_STATE)
481 fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
482 emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
483 }
484
485 if (dirty & I915_UPLOAD_PROGRAM) {
486 if (state->ProgramSize) {
487 if (INTEL_DEBUG & DEBUG_STATE)
488 fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
489
490 assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
491
492 emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
493 if (INTEL_DEBUG & DEBUG_STATE)
494 i915_disassemble_program(state->Program, state->ProgramSize);
495 }
496 }
497
498 assert(get_dirty(state) == 0);
499 }
500
501 static void
i915_destroy_context(struct intel_context * intel)502 i915_destroy_context(struct intel_context *intel)
503 {
504 GLuint i;
505 struct i915_context *i915 = i915_context(&intel->ctx);
506
507 intel_region_release(&i915->state.draw_region);
508 intel_region_release(&i915->state.depth_region);
509
510 for (i = 0; i < I915_TEX_UNITS; i++) {
511 if (i915->state.tex_buffer[i] != NULL) {
512 drm_intel_bo_unreference(i915->state.tex_buffer[i]);
513 i915->state.tex_buffer[i] = NULL;
514 }
515 }
516
517 _tnl_free_vertices(&intel->ctx);
518 }
519
520 void
i915_set_buf_info_for_region(uint32_t * state,struct intel_region * region,uint32_t buffer_id)521 i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
522 uint32_t buffer_id)
523 {
524 state[0] = _3DSTATE_BUF_INFO_CMD;
525 state[1] = buffer_id;
526
527 if (region != NULL) {
528 state[1] |= BUF_3D_PITCH(region->pitch);
529
530 if (region->tiling != I915_TILING_NONE) {
531 state[1] |= BUF_3D_TILED_SURFACE;
532 if (region->tiling == I915_TILING_Y)
533 state[1] |= BUF_3D_TILE_WALK_Y;
534 }
535 } else {
536 /* Fill in a default pitch, since 0 is invalid. We'll be
537 * setting the buffer offset to 0 and not referencing the
538 * buffer, so the pitch could really be any valid value.
539 */
540 state[1] |= BUF_3D_PITCH(4096);
541 }
542 }
543
544 static uint32_t i915_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
545 {
546 [MESA_FORMAT_B8G8R8A8_UNORM] = DV_PF_8888,
547 [MESA_FORMAT_B8G8R8X8_UNORM] = DV_PF_8888,
548 [MESA_FORMAT_B5G6R5_UNORM] = DV_PF_565 | DITHER_FULL_ALWAYS,
549 [MESA_FORMAT_B5G5R5A1_UNORM] = DV_PF_1555 | DITHER_FULL_ALWAYS,
550 [MESA_FORMAT_B4G4R4A4_UNORM] = DV_PF_4444 | DITHER_FULL_ALWAYS,
551 };
552
553 static bool
i915_render_target_supported(struct intel_context * intel,struct gl_renderbuffer * rb)554 i915_render_target_supported(struct intel_context *intel,
555 struct gl_renderbuffer *rb)
556 {
557 mesa_format format = rb->Format;
558
559 if (format == MESA_FORMAT_Z24_UNORM_S8_UINT ||
560 format == MESA_FORMAT_Z24_UNORM_X8_UINT ||
561 format == MESA_FORMAT_Z_UNORM16) {
562 return true;
563 }
564
565 return i915_render_target_format_for_mesa_format[format] != 0;
566 }
567
568 static void
i915_set_draw_region(struct intel_context * intel,struct intel_region * color_regions[],struct intel_region * depth_region,GLuint num_regions)569 i915_set_draw_region(struct intel_context *intel,
570 struct intel_region *color_regions[],
571 struct intel_region *depth_region,
572 GLuint num_regions)
573 {
574 struct i915_context *i915 = i915_context(&intel->ctx);
575 struct gl_context *ctx = &intel->ctx;
576 struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
577 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
578 struct gl_renderbuffer *drb;
579 struct intel_renderbuffer *idrb = NULL;
580 GLuint value;
581 struct i915_hw_state *state = &i915->state;
582 uint32_t draw_x, draw_y, draw_offset;
583
584 if (state->draw_region != color_regions[0]) {
585 intel_region_reference(&state->draw_region, color_regions[0]);
586 }
587 if (state->depth_region != depth_region) {
588 intel_region_reference(&state->depth_region, depth_region);
589 }
590
591 /*
592 * Set stride/cpp values
593 */
594 i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_CBUFADDR0],
595 color_regions[0], BUF_3D_ID_COLOR_BACK);
596
597 i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_DBUFADDR0],
598 depth_region, BUF_3D_ID_DEPTH);
599
600 /*
601 * Compute/set I915_DESTREG_DV1 value
602 */
603 value = (DSTORG_HORT_BIAS(0x8) | /* .5 */
604 DSTORG_VERT_BIAS(0x8) | /* .5 */
605 LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
606 if (irb != NULL) {
607 value |= i915_render_target_format_for_mesa_format[intel_rb_format(irb)];
608 } else {
609 value |= DV_PF_8888;
610 }
611
612 /* This isn't quite safe, thus being hidden behind an option. When changing
613 * the value of this bit, the pipeline needs to be MI_FLUSHed. And it
614 * can only be set when a depth buffer is already defined.
615 */
616 if (intel->is_945 && intel->use_early_z &&
617 depth_region->tiling != I915_TILING_NONE)
618 value |= CLASSIC_EARLY_DEPTH;
619
620 if (depth_region && depth_region->cpp == 4) {
621 value |= DEPTH_FRMT_24_FIXED_8_OTHER;
622 }
623 else {
624 value |= DEPTH_FRMT_16_FIXED;
625 }
626 state->Buffer[I915_DESTREG_DV1] = value;
627
628 drb = ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer;
629 if (!drb)
630 drb = ctx->DrawBuffer->Attachment[BUFFER_STENCIL].Renderbuffer;
631
632 if (drb)
633 idrb = intel_renderbuffer(drb);
634
635 /* We set up the drawing rectangle to be offset into the color
636 * region's location in the miptree. If it doesn't match with
637 * depth's offsets, we can't render to it.
638 *
639 * (Well, not actually true -- the hw grew a bit to let depth's
640 * offset get forced to 0,0. We may want to use that if people are
641 * hitting that case. Also, some configurations may be supportable
642 * by tweaking the start offset of the buffers around, which we
643 * can't do in general due to tiling)
644 */
645 FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
646 idrb && irb && (idrb->draw_x != irb->draw_x ||
647 idrb->draw_y != irb->draw_y));
648
649 if (irb) {
650 draw_x = irb->draw_x;
651 draw_y = irb->draw_y;
652 } else if (idrb) {
653 draw_x = idrb->draw_x;
654 draw_y = idrb->draw_y;
655 } else {
656 draw_x = 0;
657 draw_y = 0;
658 }
659
660 draw_offset = (draw_y << 16) | draw_x;
661
662 FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
663 (ctx->DrawBuffer->Width + draw_x > 2048) ||
664 (ctx->DrawBuffer->Height + draw_y > 2048));
665 /* When changing drawing rectangle offset, an MI_FLUSH is first required. */
666 if (draw_offset != i915->last_draw_offset) {
667 state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE;
668 i915->last_draw_offset = draw_offset;
669 } else
670 state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP;
671
672 state->Buffer[I915_DESTREG_DRAWRECT1] = _3DSTATE_DRAWRECT_INFO;
673 state->Buffer[I915_DESTREG_DRAWRECT2] = 0;
674 state->Buffer[I915_DESTREG_DRAWRECT3] = draw_offset;
675 state->Buffer[I915_DESTREG_DRAWRECT4] =
676 ((ctx->DrawBuffer->Width + draw_x - 1) & 0xffff) |
677 ((ctx->DrawBuffer->Height + draw_y - 1) << 16);
678 state->Buffer[I915_DESTREG_DRAWRECT5] = draw_offset;
679
680 I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
681 }
682
683 static void
i915_update_color_write_enable(struct i915_context * i915,bool enable)684 i915_update_color_write_enable(struct i915_context *i915, bool enable)
685 {
686 uint32_t dw = i915->state.Ctx[I915_CTXREG_LIS6];
687 if (enable)
688 dw |= S6_COLOR_WRITE_ENABLE;
689 else
690 dw &= ~S6_COLOR_WRITE_ENABLE;
691 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
692 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
693 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
694 }
695 }
696
697 /**
698 * Update the hardware state for drawing into a window or framebuffer object.
699 *
700 * Called by glDrawBuffer, glBindFramebufferEXT, MakeCurrent, and other
701 * places within the driver.
702 *
703 * Basically, this needs to be called any time the current framebuffer
704 * changes, the renderbuffers change, or we need to draw into different
705 * color buffers.
706 */
707 static void
i915_update_draw_buffer(struct intel_context * intel)708 i915_update_draw_buffer(struct intel_context *intel)
709 {
710 struct i915_context *i915 = (struct i915_context *)intel;
711 struct gl_context *ctx = &intel->ctx;
712 struct gl_framebuffer *fb = ctx->DrawBuffer;
713 struct intel_region *colorRegion = NULL, *depthRegion = NULL;
714 struct intel_renderbuffer *irbDepth = NULL, *irbStencil = NULL;
715
716 if (!fb) {
717 /* this can happen during the initial context initialization */
718 return;
719 }
720
721 irbDepth = intel_get_renderbuffer(fb, BUFFER_DEPTH);
722 irbStencil = intel_get_renderbuffer(fb, BUFFER_STENCIL);
723
724 /* Do this here, not core Mesa, since this function is called from
725 * many places within the driver.
726 */
727 if (ctx->NewState & _NEW_BUFFERS) {
728 /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */
729 _mesa_update_framebuffer(ctx, ctx->ReadBuffer, ctx->DrawBuffer);
730 /* this updates the DrawBuffer's Width/Height if it's a FBO */
731 _mesa_update_draw_buffer_bounds(ctx, ctx->DrawBuffer);
732 }
733
734 if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
735 /* this may occur when we're called by glBindFrameBuffer() during
736 * the process of someone setting up renderbuffers, etc.
737 */
738 /*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/
739 return;
740 }
741
742 /* How many color buffers are we drawing into?
743 *
744 * If there is more than one drawbuffer (GL_FRONT_AND_BACK), or the
745 * drawbuffers are too big, we have to fallback to software.
746 */
747 if ((fb->Width > ctx->Const.MaxRenderbufferSize)
748 || (fb->Height > ctx->Const.MaxRenderbufferSize)) {
749 FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, true);
750 } else if (fb->_NumColorDrawBuffers > 1) {
751 FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, true);
752 } else {
753 struct intel_renderbuffer *irb;
754 irb = intel_renderbuffer(fb->_ColorDrawBuffers[0]);
755 colorRegion = (irb && irb->mt) ? irb->mt->region : NULL;
756 FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, false);
757 }
758
759 /* Check for depth fallback. */
760 if (irbDepth && irbDepth->mt) {
761 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false);
762 depthRegion = irbDepth->mt->region;
763 } else if (irbDepth && !irbDepth->mt) {
764 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, true);
765 depthRegion = NULL;
766 } else { /* !irbDepth */
767 /* No fallback is needed because there is no depth buffer. */
768 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false);
769 depthRegion = NULL;
770 }
771
772 /* Check for stencil fallback. */
773 if (irbStencil && irbStencil->mt) {
774 assert(intel_rb_format(irbStencil) == MESA_FORMAT_Z24_UNORM_S8_UINT);
775 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
776 } else if (irbStencil && !irbStencil->mt) {
777 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, true);
778 } else { /* !irbStencil */
779 /* No fallback is needed because there is no stencil buffer. */
780 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
781 }
782
783 /* If we have a (packed) stencil buffer attached but no depth buffer,
784 * we still need to set up the shared depth/stencil state so we can use it.
785 */
786 if (depthRegion == NULL && irbStencil && irbStencil->mt
787 && intel_rb_format(irbStencil) == MESA_FORMAT_Z24_UNORM_S8_UINT) {
788 depthRegion = irbStencil->mt->region;
789 }
790
791 /*
792 * Update depth and stencil test state
793 */
794 ctx->Driver.Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
795 ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled);
796
797 i915_update_color_write_enable(i915, colorRegion != NULL);
798
799 intel->vtbl.set_draw_region(intel, &colorRegion, depthRegion,
800 fb->_NumColorDrawBuffers);
801 intel->NewGLState |= _NEW_BUFFERS;
802
803 /* Set state we know depends on drawable parameters:
804 */
805 intelCalcViewport(ctx);
806 ctx->Driver.Scissor(ctx);
807
808 /* Update culling direction which changes depending on the
809 * orientation of the buffer:
810 */
811 ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace);
812 }
813
814 static void
i915_new_batch(struct intel_context * intel)815 i915_new_batch(struct intel_context *intel)
816 {
817 struct i915_context *i915 = i915_context(&intel->ctx);
818
819 /* Mark all state as needing to be emitted when starting a new batchbuffer.
820 * Using hardware contexts would be an alternative, but they have some
821 * difficulties associated with them (physical address requirements).
822 */
823 i915->state.emitted = 0;
824 i915->last_draw_offset = 0;
825 i915->last_sampler = 0;
826
827 i915->current_vb_bo = NULL;
828 i915->current_vertex_size = 0;
829 }
830
831 static void
i915_assert_not_dirty(struct intel_context * intel)832 i915_assert_not_dirty( struct intel_context *intel )
833 {
834 struct i915_context *i915 = i915_context(&intel->ctx);
835 GLuint dirty = get_dirty(&i915->state);
836 assert(!dirty);
837 (void) dirty;
838 }
839
840 static void
i915_invalidate_state(struct intel_context * intel,GLuint new_state)841 i915_invalidate_state(struct intel_context *intel, GLuint new_state)
842 {
843 struct gl_context *ctx = &intel->ctx;
844
845 _swsetup_InvalidateState(ctx, new_state);
846 _tnl_InvalidateState(ctx, new_state);
847 _tnl_invalidate_vertex_state(ctx, new_state);
848 }
849
850 void
i915InitVtbl(struct i915_context * i915)851 i915InitVtbl(struct i915_context *i915)
852 {
853 i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
854 i915->intel.vtbl.destroy = i915_destroy_context;
855 i915->intel.vtbl.emit_state = i915_emit_state;
856 i915->intel.vtbl.new_batch = i915_new_batch;
857 i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
858 i915->intel.vtbl.render_start = i915_render_start;
859 i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
860 i915->intel.vtbl.set_draw_region = i915_set_draw_region;
861 i915->intel.vtbl.update_draw_buffer = i915_update_draw_buffer;
862 i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
863 i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
864 i915->intel.vtbl.finish_batch = intel_finish_vb;
865 i915->intel.vtbl.invalidate_state = i915_invalidate_state;
866 i915->intel.vtbl.render_target_supported = i915_render_target_supported;
867 }
868