1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20
21 /*****************************************************************************/
22 /* */
23 /* File Name : ih264d_api.c */
24 /* */
25 /* Description : Has all API related functions */
26 /* */
27 /* */
28 /* List of Functions : api_check_struct_sanity */
29 /* ih264d_set_processor */
30 /* ih264d_create */
31 /* ih264d_delete */
32 /* ih264d_init */
33 /* ih264d_map_error */
34 /* ih264d_video_decode */
35 /* ih264d_get_version */
36 /* ih264d_get_display_frame */
37 /* ih264d_set_display_frame */
38 /* ih264d_set_flush_mode */
39 /* ih264d_get_status */
40 /* ih264d_get_buf_info */
41 /* ih264d_set_params */
42 /* ih264d_set_default_params */
43 /* ih264d_reset */
44 /* ih264d_ctl */
45 /* ih264d_rel_display_frame */
46 /* ih264d_set_degrade */
47 /* ih264d_get_frame_dimensions */
48 /* ih264d_set_num_cores */
49 /* ih264d_fill_output_struct_from_context */
50 /* ih264d_api_function */
51 /* */
52 /* Issues / Problems : None */
53 /* */
54 /* Revision History : */
55 /* */
56 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
57 /* 14 10 2008 100356(SKV) Draft */
58 /* */
59 /*****************************************************************************/
60 #include "ih264_typedefs.h"
61 #include "ih264_macros.h"
62 #include "ih264_platform_macros.h"
63 #include "ih264d_tables.h"
64 #include "iv.h"
65 #include "ivd.h"
66 #include "ih264d.h"
67 #include "ih264d_defs.h"
68
69 #include <string.h>
70 #include <limits.h>
71 #include <stddef.h>
72
73 #include "ih264d_inter_pred.h"
74
75 #include "ih264d_structs.h"
76 #include "ih264d_nal.h"
77 #include "ih264d_error_handler.h"
78
79 #include "ih264d_defs.h"
80
81 #include "ithread.h"
82 #include "ih264d_parse_slice.h"
83 #include "ih264d_function_selector.h"
84 #include "ih264_error.h"
85 #include "ih264_disp_mgr.h"
86 #include "ih264_buf_mgr.h"
87 #include "ih264d_deblocking.h"
88 #include "ih264d_parse_cavlc.h"
89 #include "ih264d_parse_cabac.h"
90 #include "ih264d_utils.h"
91 #include "ih264d_format_conv.h"
92 #include "ih264d_parse_headers.h"
93 #include "ih264d_thread_compute_bs.h"
94 #include <assert.h>
95
96
97 /*********************/
98 /* Codec Versioning */
99 /*********************/
100 //Move this to where it is used
101 #define CODEC_NAME "H264VDEC"
102 #define CODEC_RELEASE_TYPE "production"
103 #define CODEC_RELEASE_VER "05.00"
104 #define CODEC_VENDOR "ITTIAM"
105 #define MAXVERSION_STRLEN 511
106 #ifdef __ANDROID__
107 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
108 snprintf(version_string, MAXVERSION_STRLEN, \
109 "@(#)Id:%s_%s Ver:%s Released by %s", \
110 codec_name, codec_release_type, codec_release_ver, codec_vendor)
111 #else
112 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
113 snprintf(version_string, MAXVERSION_STRLEN, \
114 "@(#)Id:%s_%s Ver:%s Released by %s Build: %s @ %s", \
115 codec_name, codec_release_type, codec_release_ver, codec_vendor, __DATE__, __TIME__)
116 #endif
117
118
119 #define MIN_IN_BUFS 1
120 #define MIN_OUT_BUFS_420 3
121 #define MIN_OUT_BUFS_422ILE 1
122 #define MIN_OUT_BUFS_RGB565 1
123 #define MIN_OUT_BUFS_420SP 2
124
125 #define NUM_FRAMES_LIMIT_ENABLED 0
126
127 #if NUM_FRAMES_LIMIT_ENABLED
128 #define NUM_FRAMES_LIMIT 10000
129 #else
130 #define NUM_FRAMES_LIMIT 0x7FFFFFFF
131 #endif
132
133
134 UWORD32 ih264d_get_extra_mem_external(UWORD32 width, UWORD32 height);
135 WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
136 void *pv_api_ip,
137 void *pv_api_op);
138 WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl,
139 void *pv_api_ip,
140 void *pv_api_op);
141
142 WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
143
144 WORD32 ih264d_deblock_display(dec_struct_t *ps_dec);
145
146 void ih264d_signal_decode_thread(dec_struct_t *ps_dec);
147
148 void ih264d_signal_bs_deblk_thread(dec_struct_t *ps_dec);
149 void ih264d_decode_picture_thread(dec_struct_t *ps_dec);
150
151 WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
152 void *pv_api_ip,
153 void *pv_api_op);
154
155 void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
156 ivd_video_decode_op_t *ps_dec_op);
157
api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)158 static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle,
159 void *pv_api_ip,
160 void *pv_api_op)
161 {
162 IVD_API_COMMAND_TYPE_T e_cmd;
163 UWORD32 *pu4_api_ip;
164 UWORD32 *pu4_api_op;
165 UWORD32 i, j;
166
167 if(NULL == pv_api_op)
168 return (IV_FAIL);
169
170 if(NULL == pv_api_ip)
171 return (IV_FAIL);
172
173 pu4_api_ip = (UWORD32 *)pv_api_ip;
174 pu4_api_op = (UWORD32 *)pv_api_op;
175 e_cmd = *(pu4_api_ip + 1);
176
177 /* error checks on handle */
178 switch((WORD32)e_cmd)
179 {
180 case IVD_CMD_CREATE:
181 break;
182
183 case IVD_CMD_REL_DISPLAY_FRAME:
184 case IVD_CMD_SET_DISPLAY_FRAME:
185 case IVD_CMD_GET_DISPLAY_FRAME:
186 case IVD_CMD_VIDEO_DECODE:
187 case IVD_CMD_DELETE:
188 case IVD_CMD_VIDEO_CTL:
189 if(ps_handle == NULL)
190 {
191 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
192 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
193 return IV_FAIL;
194 }
195
196 if(ps_handle->u4_size != sizeof(iv_obj_t))
197 {
198 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
199 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
200 return IV_FAIL;
201 }
202
203 if(ps_handle->pv_fxns != ih264d_api_function)
204 {
205 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
206 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
207 return IV_FAIL;
208 }
209
210 if(ps_handle->pv_codec_handle == NULL)
211 {
212 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
213 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
214 return IV_FAIL;
215 }
216 break;
217 default:
218 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
219 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
220 return IV_FAIL;
221 }
222
223 switch((WORD32)e_cmd)
224 {
225 case IVD_CMD_CREATE:
226 {
227 ih264d_create_ip_t *ps_ip = (ih264d_create_ip_t *)pv_api_ip;
228 ih264d_create_op_t *ps_op = (ih264d_create_op_t *)pv_api_op;
229
230
231 ps_op->s_ivd_create_op_t.u4_error_code = 0;
232
233 if((ps_ip->s_ivd_create_ip_t.u4_size > sizeof(ih264d_create_ip_t))
234 || (ps_ip->s_ivd_create_ip_t.u4_size
235 < sizeof(ivd_create_ip_t)))
236 {
237 ps_op->s_ivd_create_op_t.u4_error_code |= 1
238 << IVD_UNSUPPORTEDPARAM;
239 ps_op->s_ivd_create_op_t.u4_error_code |=
240 IVD_IP_API_STRUCT_SIZE_INCORRECT;
241 H264_DEC_DEBUG_PRINT("\n");
242 return (IV_FAIL);
243 }
244
245 if((ps_op->s_ivd_create_op_t.u4_size != sizeof(ih264d_create_op_t))
246 && (ps_op->s_ivd_create_op_t.u4_size
247 != sizeof(ivd_create_op_t)))
248 {
249 ps_op->s_ivd_create_op_t.u4_error_code |= 1
250 << IVD_UNSUPPORTEDPARAM;
251 ps_op->s_ivd_create_op_t.u4_error_code |=
252 IVD_OP_API_STRUCT_SIZE_INCORRECT;
253 H264_DEC_DEBUG_PRINT("\n");
254 return (IV_FAIL);
255 }
256
257
258 if((ps_ip->s_ivd_create_ip_t.e_output_format != IV_YUV_420P)
259 && (ps_ip->s_ivd_create_ip_t.e_output_format
260 != IV_YUV_422ILE)
261 && (ps_ip->s_ivd_create_ip_t.e_output_format
262 != IV_RGB_565)
263 && (ps_ip->s_ivd_create_ip_t.e_output_format
264 != IV_YUV_420SP_UV)
265 && (ps_ip->s_ivd_create_ip_t.e_output_format
266 != IV_YUV_420SP_VU))
267 {
268 ps_op->s_ivd_create_op_t.u4_error_code |= 1
269 << IVD_UNSUPPORTEDPARAM;
270 ps_op->s_ivd_create_op_t.u4_error_code |=
271 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
272 H264_DEC_DEBUG_PRINT("\n");
273 return (IV_FAIL);
274 }
275
276 }
277 break;
278
279 case IVD_CMD_GET_DISPLAY_FRAME:
280 {
281 ih264d_get_display_frame_ip_t *ps_ip =
282 (ih264d_get_display_frame_ip_t *)pv_api_ip;
283 ih264d_get_display_frame_op_t *ps_op =
284 (ih264d_get_display_frame_op_t *)pv_api_op;
285
286 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
287
288 if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size
289 != sizeof(ih264d_get_display_frame_ip_t))
290 && (ps_ip->s_ivd_get_display_frame_ip_t.u4_size
291 != sizeof(ivd_get_display_frame_ip_t)))
292 {
293 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
294 << IVD_UNSUPPORTEDPARAM;
295 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
296 IVD_IP_API_STRUCT_SIZE_INCORRECT;
297 return (IV_FAIL);
298 }
299
300 if((ps_op->s_ivd_get_display_frame_op_t.u4_size
301 != sizeof(ih264d_get_display_frame_op_t))
302 && (ps_op->s_ivd_get_display_frame_op_t.u4_size
303 != sizeof(ivd_get_display_frame_op_t)))
304 {
305 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
306 << IVD_UNSUPPORTEDPARAM;
307 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
308 IVD_OP_API_STRUCT_SIZE_INCORRECT;
309 return (IV_FAIL);
310 }
311 }
312 break;
313
314 case IVD_CMD_REL_DISPLAY_FRAME:
315 {
316 ih264d_rel_display_frame_ip_t *ps_ip =
317 (ih264d_rel_display_frame_ip_t *)pv_api_ip;
318 ih264d_rel_display_frame_op_t *ps_op =
319 (ih264d_rel_display_frame_op_t *)pv_api_op;
320
321 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
322
323 if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
324 != sizeof(ih264d_rel_display_frame_ip_t))
325 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
326 != sizeof(ivd_rel_display_frame_ip_t)))
327 {
328 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
329 << IVD_UNSUPPORTEDPARAM;
330 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
331 IVD_IP_API_STRUCT_SIZE_INCORRECT;
332 return (IV_FAIL);
333 }
334
335 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size
336 != sizeof(ih264d_rel_display_frame_op_t))
337 && (ps_op->s_ivd_rel_display_frame_op_t.u4_size
338 != sizeof(ivd_rel_display_frame_op_t)))
339 {
340 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
341 << IVD_UNSUPPORTEDPARAM;
342 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
343 IVD_OP_API_STRUCT_SIZE_INCORRECT;
344 return (IV_FAIL);
345 }
346
347 }
348 break;
349
350 case IVD_CMD_SET_DISPLAY_FRAME:
351 {
352 ih264d_set_display_frame_ip_t *ps_ip =
353 (ih264d_set_display_frame_ip_t *)pv_api_ip;
354 ih264d_set_display_frame_op_t *ps_op =
355 (ih264d_set_display_frame_op_t *)pv_api_op;
356 UWORD32 j;
357
358 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
359
360 if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size
361 != sizeof(ih264d_set_display_frame_ip_t))
362 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size
363 != sizeof(ivd_set_display_frame_ip_t)))
364 {
365 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
366 << IVD_UNSUPPORTEDPARAM;
367 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
368 IVD_IP_API_STRUCT_SIZE_INCORRECT;
369 return (IV_FAIL);
370 }
371
372 if((ps_op->s_ivd_set_display_frame_op_t.u4_size
373 != sizeof(ih264d_set_display_frame_op_t))
374 && (ps_op->s_ivd_set_display_frame_op_t.u4_size
375 != sizeof(ivd_set_display_frame_op_t)))
376 {
377 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
378 << IVD_UNSUPPORTEDPARAM;
379 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
380 IVD_OP_API_STRUCT_SIZE_INCORRECT;
381 return (IV_FAIL);
382 }
383
384 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
385 {
386 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
387 << IVD_UNSUPPORTEDPARAM;
388 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
389 IVD_DISP_FRM_ZERO_OP_BUFS;
390 return IV_FAIL;
391 }
392
393 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs;
394 j++)
395 {
396 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs
397 == 0)
398 {
399 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
400 << IVD_UNSUPPORTEDPARAM;
401 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
402 IVD_DISP_FRM_ZERO_OP_BUFS;
403 return IV_FAIL;
404 }
405
406 for(i = 0;
407 i
408 < ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;
409 i++)
410 {
411 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i]
412 == NULL)
413 {
414 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
415 << IVD_UNSUPPORTEDPARAM;
416 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
417 IVD_DISP_FRM_OP_BUF_NULL;
418 return IV_FAIL;
419 }
420
421 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i]
422 == 0)
423 {
424 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
425 << IVD_UNSUPPORTEDPARAM;
426 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
427 IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
428 return IV_FAIL;
429 }
430 }
431 }
432 }
433 break;
434
435 case IVD_CMD_VIDEO_DECODE:
436 {
437 ih264d_video_decode_ip_t *ps_ip =
438 (ih264d_video_decode_ip_t *)pv_api_ip;
439 ih264d_video_decode_op_t *ps_op =
440 (ih264d_video_decode_op_t *)pv_api_op;
441
442 H264_DEC_DEBUG_PRINT("The input bytes is: %d",
443 ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes);
444 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
445
446 if(ps_ip->s_ivd_video_decode_ip_t.u4_size
447 != sizeof(ih264d_video_decode_ip_t)&&
448 ps_ip->s_ivd_video_decode_ip_t.u4_size != offsetof(ivd_video_decode_ip_t, s_out_buffer))
449 {
450 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
451 << IVD_UNSUPPORTEDPARAM;
452 ps_op->s_ivd_video_decode_op_t.u4_error_code |=
453 IVD_IP_API_STRUCT_SIZE_INCORRECT;
454 return (IV_FAIL);
455 }
456
457 if(ps_op->s_ivd_video_decode_op_t.u4_size
458 != sizeof(ih264d_video_decode_op_t)&&
459 ps_op->s_ivd_video_decode_op_t.u4_size != offsetof(ivd_video_decode_op_t, u4_output_present))
460 {
461 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
462 << IVD_UNSUPPORTEDPARAM;
463 ps_op->s_ivd_video_decode_op_t.u4_error_code |=
464 IVD_OP_API_STRUCT_SIZE_INCORRECT;
465 return (IV_FAIL);
466 }
467
468 }
469 break;
470
471 case IVD_CMD_DELETE:
472 {
473 ih264d_delete_ip_t *ps_ip =
474 (ih264d_delete_ip_t *)pv_api_ip;
475 ih264d_delete_op_t *ps_op =
476 (ih264d_delete_op_t *)pv_api_op;
477
478 ps_op->s_ivd_delete_op_t.u4_error_code = 0;
479
480 if(ps_ip->s_ivd_delete_ip_t.u4_size
481 != sizeof(ih264d_delete_ip_t))
482 {
483 ps_op->s_ivd_delete_op_t.u4_error_code |= 1
484 << IVD_UNSUPPORTEDPARAM;
485 ps_op->s_ivd_delete_op_t.u4_error_code |=
486 IVD_IP_API_STRUCT_SIZE_INCORRECT;
487 return (IV_FAIL);
488 }
489
490 if(ps_op->s_ivd_delete_op_t.u4_size
491 != sizeof(ih264d_delete_op_t))
492 {
493 ps_op->s_ivd_delete_op_t.u4_error_code |= 1
494 << IVD_UNSUPPORTEDPARAM;
495 ps_op->s_ivd_delete_op_t.u4_error_code |=
496 IVD_OP_API_STRUCT_SIZE_INCORRECT;
497 return (IV_FAIL);
498 }
499
500 }
501 break;
502
503 case IVD_CMD_VIDEO_CTL:
504 {
505 UWORD32 *pu4_ptr_cmd;
506 UWORD32 sub_command;
507
508 pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
509 pu4_ptr_cmd += 2;
510 sub_command = *pu4_ptr_cmd;
511
512 switch(sub_command)
513 {
514 case IVD_CMD_CTL_SETPARAMS:
515 {
516 ih264d_ctl_set_config_ip_t *ps_ip;
517 ih264d_ctl_set_config_op_t *ps_op;
518 ps_ip = (ih264d_ctl_set_config_ip_t *)pv_api_ip;
519 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
520
521 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size
522 != sizeof(ih264d_ctl_set_config_ip_t))
523 {
524 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
525 << IVD_UNSUPPORTEDPARAM;
526 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
527 IVD_IP_API_STRUCT_SIZE_INCORRECT;
528 return IV_FAIL;
529 }
530 }
531 //no break; is needed here
532 case IVD_CMD_CTL_SETDEFAULT:
533 {
534 ih264d_ctl_set_config_op_t *ps_op;
535 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
536 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size
537 != sizeof(ih264d_ctl_set_config_op_t))
538 {
539 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
540 << IVD_UNSUPPORTEDPARAM;
541 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
542 IVD_OP_API_STRUCT_SIZE_INCORRECT;
543 return IV_FAIL;
544 }
545 }
546 break;
547
548 case IVD_CMD_CTL_GETPARAMS:
549 {
550 ih264d_ctl_getstatus_ip_t *ps_ip;
551 ih264d_ctl_getstatus_op_t *ps_op;
552
553 ps_ip = (ih264d_ctl_getstatus_ip_t *)pv_api_ip;
554 ps_op = (ih264d_ctl_getstatus_op_t *)pv_api_op;
555 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size
556 != sizeof(ih264d_ctl_getstatus_ip_t))
557 {
558 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
559 << IVD_UNSUPPORTEDPARAM;
560 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
561 IVD_IP_API_STRUCT_SIZE_INCORRECT;
562 return IV_FAIL;
563 }
564 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size
565 != sizeof(ih264d_ctl_getstatus_op_t))
566 {
567 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
568 << IVD_UNSUPPORTEDPARAM;
569 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
570 IVD_OP_API_STRUCT_SIZE_INCORRECT;
571 return IV_FAIL;
572 }
573 }
574 break;
575
576 case IVD_CMD_CTL_GETBUFINFO:
577 {
578 ih264d_ctl_getbufinfo_ip_t *ps_ip;
579 ih264d_ctl_getbufinfo_op_t *ps_op;
580 ps_ip = (ih264d_ctl_getbufinfo_ip_t *)pv_api_ip;
581 ps_op = (ih264d_ctl_getbufinfo_op_t *)pv_api_op;
582
583 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size
584 != sizeof(ih264d_ctl_getbufinfo_ip_t))
585 {
586 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
587 << IVD_UNSUPPORTEDPARAM;
588 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
589 IVD_IP_API_STRUCT_SIZE_INCORRECT;
590 return IV_FAIL;
591 }
592 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size
593 != sizeof(ih264d_ctl_getbufinfo_op_t))
594 {
595 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
596 << IVD_UNSUPPORTEDPARAM;
597 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
598 IVD_OP_API_STRUCT_SIZE_INCORRECT;
599 return IV_FAIL;
600 }
601 }
602 break;
603
604 case IVD_CMD_CTL_GETVERSION:
605 {
606 ih264d_ctl_getversioninfo_ip_t *ps_ip;
607 ih264d_ctl_getversioninfo_op_t *ps_op;
608 ps_ip = (ih264d_ctl_getversioninfo_ip_t *)pv_api_ip;
609 ps_op = (ih264d_ctl_getversioninfo_op_t *)pv_api_op;
610 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size
611 != sizeof(ih264d_ctl_getversioninfo_ip_t))
612 {
613 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
614 << IVD_UNSUPPORTEDPARAM;
615 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
616 IVD_IP_API_STRUCT_SIZE_INCORRECT;
617 return IV_FAIL;
618 }
619 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size
620 != sizeof(ih264d_ctl_getversioninfo_op_t))
621 {
622 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
623 << IVD_UNSUPPORTEDPARAM;
624 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
625 IVD_OP_API_STRUCT_SIZE_INCORRECT;
626 return IV_FAIL;
627 }
628 }
629 break;
630
631 case IVD_CMD_CTL_FLUSH:
632 {
633 ih264d_ctl_flush_ip_t *ps_ip;
634 ih264d_ctl_flush_op_t *ps_op;
635 ps_ip = (ih264d_ctl_flush_ip_t *)pv_api_ip;
636 ps_op = (ih264d_ctl_flush_op_t *)pv_api_op;
637 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size
638 != sizeof(ih264d_ctl_flush_ip_t))
639 {
640 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
641 << IVD_UNSUPPORTEDPARAM;
642 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
643 IVD_IP_API_STRUCT_SIZE_INCORRECT;
644 return IV_FAIL;
645 }
646 if(ps_op->s_ivd_ctl_flush_op_t.u4_size
647 != sizeof(ih264d_ctl_flush_op_t))
648 {
649 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
650 << IVD_UNSUPPORTEDPARAM;
651 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
652 IVD_OP_API_STRUCT_SIZE_INCORRECT;
653 return IV_FAIL;
654 }
655 }
656 break;
657
658 case IVD_CMD_CTL_RESET:
659 {
660 ih264d_ctl_reset_ip_t *ps_ip;
661 ih264d_ctl_reset_op_t *ps_op;
662 ps_ip = (ih264d_ctl_reset_ip_t *)pv_api_ip;
663 ps_op = (ih264d_ctl_reset_op_t *)pv_api_op;
664 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size
665 != sizeof(ih264d_ctl_reset_ip_t))
666 {
667 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
668 << IVD_UNSUPPORTEDPARAM;
669 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
670 IVD_IP_API_STRUCT_SIZE_INCORRECT;
671 return IV_FAIL;
672 }
673 if(ps_op->s_ivd_ctl_reset_op_t.u4_size
674 != sizeof(ih264d_ctl_reset_op_t))
675 {
676 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
677 << IVD_UNSUPPORTEDPARAM;
678 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
679 IVD_OP_API_STRUCT_SIZE_INCORRECT;
680 return IV_FAIL;
681 }
682 }
683 break;
684
685 case IH264D_CMD_CTL_DEGRADE:
686 {
687 ih264d_ctl_degrade_ip_t *ps_ip;
688 ih264d_ctl_degrade_op_t *ps_op;
689
690 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
691 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
692
693 if(ps_ip->u4_size != sizeof(ih264d_ctl_degrade_ip_t))
694 {
695 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
696 ps_op->u4_error_code |=
697 IVD_IP_API_STRUCT_SIZE_INCORRECT;
698 return IV_FAIL;
699 }
700
701 if(ps_op->u4_size != sizeof(ih264d_ctl_degrade_op_t))
702 {
703 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
704 ps_op->u4_error_code |=
705 IVD_OP_API_STRUCT_SIZE_INCORRECT;
706 return IV_FAIL;
707 }
708
709 if((ps_ip->i4_degrade_pics < 0)
710 || (ps_ip->i4_degrade_pics > 4)
711 || (ps_ip->i4_nondegrade_interval < 0)
712 || (ps_ip->i4_degrade_type < 0)
713 || (ps_ip->i4_degrade_type > 15))
714 {
715 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
716 return IV_FAIL;
717 }
718
719 break;
720 }
721
722 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
723 {
724 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
725 ih264d_ctl_get_frame_dimensions_op_t *ps_op;
726
727 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
728 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
729
730 if(ps_ip->u4_size
731 != sizeof(ih264d_ctl_get_frame_dimensions_ip_t))
732 {
733 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
734 ps_op->u4_error_code |=
735 IVD_IP_API_STRUCT_SIZE_INCORRECT;
736 return IV_FAIL;
737 }
738
739 if(ps_op->u4_size
740 != sizeof(ih264d_ctl_get_frame_dimensions_op_t))
741 {
742 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
743 ps_op->u4_error_code |=
744 IVD_OP_API_STRUCT_SIZE_INCORRECT;
745 return IV_FAIL;
746 }
747
748 break;
749 }
750 case IH264D_CMD_CTL_GET_VUI_PARAMS:
751 {
752 ih264d_ctl_get_vui_params_ip_t *ps_ip;
753 ih264d_ctl_get_vui_params_op_t *ps_op;
754
755 ps_ip =
756 (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip;
757 ps_op =
758 (ih264d_ctl_get_vui_params_op_t *)pv_api_op;
759
760 if(ps_ip->u4_size
761 != sizeof(ih264d_ctl_get_vui_params_ip_t))
762 {
763 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
764 ps_op->u4_error_code |=
765 IVD_IP_API_STRUCT_SIZE_INCORRECT;
766 return IV_FAIL;
767 }
768
769 if(ps_op->u4_size
770 != sizeof(ih264d_ctl_get_vui_params_op_t))
771 {
772 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
773 ps_op->u4_error_code |=
774 IVD_OP_API_STRUCT_SIZE_INCORRECT;
775 return IV_FAIL;
776 }
777
778 break;
779 }
780 case IH264D_CMD_CTL_SET_NUM_CORES:
781 {
782 ih264d_ctl_set_num_cores_ip_t *ps_ip;
783 ih264d_ctl_set_num_cores_op_t *ps_op;
784
785 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
786 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
787
788 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_num_cores_ip_t))
789 {
790 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
791 ps_op->u4_error_code |=
792 IVD_IP_API_STRUCT_SIZE_INCORRECT;
793 return IV_FAIL;
794 }
795
796 if(ps_op->u4_size != sizeof(ih264d_ctl_set_num_cores_op_t))
797 {
798 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
799 ps_op->u4_error_code |=
800 IVD_OP_API_STRUCT_SIZE_INCORRECT;
801 return IV_FAIL;
802 }
803
804 if((ps_ip->u4_num_cores != 1) && (ps_ip->u4_num_cores != 2)
805 && (ps_ip->u4_num_cores != 3)
806 && (ps_ip->u4_num_cores != 4))
807 {
808 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
809 return IV_FAIL;
810 }
811 break;
812 }
813 case IH264D_CMD_CTL_SET_PROCESSOR:
814 {
815 ih264d_ctl_set_processor_ip_t *ps_ip;
816 ih264d_ctl_set_processor_op_t *ps_op;
817
818 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
819 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
820
821 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_processor_ip_t))
822 {
823 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
824 ps_op->u4_error_code |=
825 IVD_IP_API_STRUCT_SIZE_INCORRECT;
826 return IV_FAIL;
827 }
828
829 if(ps_op->u4_size != sizeof(ih264d_ctl_set_processor_op_t))
830 {
831 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
832 ps_op->u4_error_code |=
833 IVD_OP_API_STRUCT_SIZE_INCORRECT;
834 return IV_FAIL;
835 }
836
837 break;
838 }
839 default:
840 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
841 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
842 return IV_FAIL;
843 break;
844 }
845 }
846 break;
847 }
848
849 return IV_SUCCESS;
850 }
851
852
853 /**
854 *******************************************************************************
855 *
856 * @brief
857 * Sets Processor type
858 *
859 * @par Description:
860 * Sets Processor type
861 *
862 * @param[in] ps_codec_obj
863 * Pointer to codec object at API level
864 *
865 * @param[in] pv_api_ip
866 * Pointer to input argument structure
867 *
868 * @param[out] pv_api_op
869 * Pointer to output argument structure
870 *
871 * @returns Status
872 *
873 * @remarks
874 *
875 *
876 *******************************************************************************
877 */
878
ih264d_set_processor(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)879 WORD32 ih264d_set_processor(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
880 {
881 ih264d_ctl_set_processor_ip_t *ps_ip;
882 ih264d_ctl_set_processor_op_t *ps_op;
883 dec_struct_t *ps_codec = (dec_struct_t *)dec_hdl->pv_codec_handle;
884
885 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
886 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
887
888 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
889 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
890
891 ih264d_init_function_ptr(ps_codec);
892
893 ps_op->u4_error_code = 0;
894 return IV_SUCCESS;
895 }
896
897
898 /**************************************************************************
899 * \if Function name : ih264d_init_decoder \endif
900 *
901 *
902 * \brief
903 * Initializes the decoder
904 *
905 * \param apiVersion : Version of the api being used.
906 * \param errorHandlingMechanism : Mechanism to be used for errror handling.
907 * \param postFilteringType: Type of post filtering operation to be used.
908 * \param uc_outputFormat: Format of the decoded picture [default 4:2:0].
909 * \param uc_dispBufs: Number of Display Buffers.
910 * \param p_NALBufAPI: Pointer to NAL Buffer API.
911 * \param p_DispBufAPI: Pointer to Display Buffer API.
912 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder
913 * for memory allocation and freeing.
914 *
915 * \return
916 * 0 on Success and -1 on error
917 *
918 **************************************************************************
919 */
ih264d_init_decoder(void * ps_dec_params)920 void ih264d_init_decoder(void * ps_dec_params)
921 {
922 dec_struct_t * ps_dec = (dec_struct_t *)ps_dec_params;
923 dec_slice_params_t *ps_cur_slice;
924 pocstruct_t *ps_prev_poc, *ps_cur_poc;
925 WORD32 size;
926
927 size = sizeof(pred_info_t) * 2 * 32;
928 memset(ps_dec->ps_pred, 0 , size);
929
930 size = sizeof(disp_mgr_t);
931 memset(ps_dec->pv_disp_buf_mgr, 0 , size);
932
933 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
934 memset(ps_dec->pv_pic_buf_mgr, 0, size);
935
936 size = sizeof(dec_err_status_t);
937 memset(ps_dec->ps_dec_err_status, 0, size);
938
939 size = sizeof(sei);
940 memset(ps_dec->ps_sei, 0, size);
941
942 size = sizeof(dpb_commands_t);
943 memset(ps_dec->ps_dpb_cmds, 0, size);
944
945 size = sizeof(dec_bit_stream_t);
946 memset(ps_dec->ps_bitstrm, 0, size);
947
948 size = sizeof(dec_slice_params_t);
949 memset(ps_dec->ps_cur_slice, 0, size);
950
951 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
952 memset(ps_dec->pv_scratch_sps_pps, 0, size);
953
954 size = sizeof(ctxt_inc_mb_info_t);
955 memset(ps_dec->ps_left_mb_ctxt_info, 0, size);
956
957 size = (sizeof(neighbouradd_t) << 2);
958 memset(ps_dec->ps_left_mvpred_addr, 0 ,size);
959
960 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
961 memset(ps_dec->pv_mv_buf_mgr, 0, size);
962
963 /* Free any dynamic buffers that are allocated */
964 ih264d_free_dynamic_bufs(ps_dec);
965
966 {
967 UWORD8 i;
968 struct pic_buffer_t *ps_init_dpb;
969 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[0][0];
970 for(i = 0; i < 2 * MAX_REF_BUFS; i++)
971 {
972 ps_init_dpb->pu1_buf1 = NULL;
973 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
974 ps_dec->ps_dpb_mgr->ps_init_dpb[0][i] = ps_init_dpb;
975 ps_dec->ps_dpb_mgr->ps_mod_dpb[0][i] = ps_init_dpb;
976 ps_init_dpb++;
977 }
978
979 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[1][0];
980 for(i = 0; i < 2 * MAX_REF_BUFS; i++)
981 {
982 ps_init_dpb->pu1_buf1 = NULL;
983 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
984 ps_dec->ps_dpb_mgr->ps_init_dpb[1][i] = ps_init_dpb;
985 ps_dec->ps_dpb_mgr->ps_mod_dpb[1][i] = ps_init_dpb;
986 ps_init_dpb++;
987 }
988 }
989
990 ps_cur_slice = ps_dec->ps_cur_slice;
991 ps_dec->init_done = 0;
992
993 ps_dec->u4_num_cores = 1;
994
995 ps_dec->u2_pic_ht = ps_dec->u2_pic_wd = 0;
996
997 ps_dec->u1_separate_parse = DEFAULT_SEPARATE_PARSE;
998 ps_dec->u4_app_disable_deblk_frm = 0;
999 ps_dec->i4_degrade_type = 0;
1000 ps_dec->i4_degrade_pics = 0;
1001
1002 memset(ps_dec->ps_pps, 0,
1003 ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS));
1004 memset(ps_dec->ps_sps, 0,
1005 ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS));
1006
1007 /* Initialization of function pointers ih264d_deblock_picture function*/
1008
1009 ps_dec->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff;
1010 ps_dec->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff;
1011
1012 ps_dec->s_cab_dec_env.pv_codec_handle = ps_dec;
1013
1014 ps_dec->u4_num_fld_in_frm = 0;
1015
1016 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec;
1017
1018 /* Initialize the sei validity u4_flag with zero indiacting sei is not valid*/
1019 ps_dec->ps_sei->u1_is_valid = 0;
1020
1021 /* decParams Initializations */
1022 ps_dec->ps_cur_pps = NULL;
1023 ps_dec->ps_cur_sps = NULL;
1024 ps_dec->u1_init_dec_flag = 0;
1025 ps_dec->u1_first_slice_in_stream = 1;
1026 ps_dec->u1_last_pic_not_decoded = 0;
1027 ps_dec->u4_app_disp_width = 0;
1028 ps_dec->i4_header_decoded = 0;
1029 ps_dec->u4_total_frames_decoded = 0;
1030
1031 ps_dec->i4_error_code = 0;
1032 ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
1033 ps_dec->ps_cur_slice->u1_mbaff_frame_flag = 0;
1034
1035 ps_dec->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS; //REJECT_PB_PICS;
1036 ps_dec->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN;
1037 ps_dec->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT;
1038 ps_dec->ps_dec_err_status->u4_cur_frm = INIT_FRAME;
1039 ps_dec->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN;
1040
1041 ps_dec->u1_pr_sl_type = 0xFF;
1042 ps_dec->u2_mbx = 0xffff;
1043 ps_dec->u2_mby = 0;
1044 ps_dec->u2_total_mbs_coded = 0;
1045
1046 /* POC initializations */
1047 ps_prev_poc = &ps_dec->s_prev_pic_poc;
1048 ps_cur_poc = &ps_dec->s_cur_pic_poc;
1049 ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0;
1050 ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0;
1051 ps_prev_poc->i4_delta_pic_order_cnt_bottom =
1052 ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0;
1053 ps_prev_poc->i4_delta_pic_order_cnt[0] =
1054 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
1055 ps_prev_poc->i4_delta_pic_order_cnt[1] =
1056 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
1057 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1058 ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count =
1059 0;
1060 ps_prev_poc->i4_bottom_field_order_count =
1061 ps_cur_poc->i4_bottom_field_order_count = 0;
1062 ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0;
1063 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1064 ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0;
1065 ps_cur_slice->u1_mmco_equalto5 = 0;
1066 ps_cur_slice->u2_frame_num = 0;
1067
1068 ps_dec->i4_max_poc = 0;
1069 ps_dec->i4_prev_max_display_seq = 0;
1070 ps_dec->u1_recon_mb_grp = 4;
1071
1072 /* Field PIC initializations */
1073 ps_dec->u1_second_field = 0;
1074 ps_dec->s_prev_seq_params.u1_eoseq_pending = 0;
1075
1076 /* Set the cropping parameters as zero */
1077 ps_dec->u2_crop_offset_y = 0;
1078 ps_dec->u2_crop_offset_uv = 0;
1079
1080 /* The Initial Frame Rate Info is not Present */
1081 ps_dec->i4_vui_frame_rate = -1;
1082 ps_dec->i4_pic_type = NA_SLICE;
1083 ps_dec->i4_frametype = IV_NA_FRAME;
1084 ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
1085
1086 ps_dec->u1_res_changed = 0;
1087
1088
1089 ps_dec->u1_frame_decoded_flag = 0;
1090
1091 /* Set the default frame seek mask mode */
1092 ps_dec->u4_skip_frm_mask = SKIP_NONE;
1093
1094 /********************************************************/
1095 /* Initialize CAVLC residual decoding function pointers */
1096 /********************************************************/
1097 ps_dec->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1;
1098 ps_dec->pf_cavlc_4x4res_block[1] =
1099 ih264d_cavlc_4x4res_block_totalcoeff_2to10;
1100 ps_dec->pf_cavlc_4x4res_block[2] =
1101 ih264d_cavlc_4x4res_block_totalcoeff_11to16;
1102
1103 ps_dec->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7;
1104 ps_dec->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8;
1105
1106 ps_dec->pf_cavlc_parse_8x8block[0] =
1107 ih264d_cavlc_parse_8x8block_none_available;
1108 ps_dec->pf_cavlc_parse_8x8block[1] =
1109 ih264d_cavlc_parse_8x8block_left_available;
1110 ps_dec->pf_cavlc_parse_8x8block[2] =
1111 ih264d_cavlc_parse_8x8block_top_available;
1112 ps_dec->pf_cavlc_parse_8x8block[3] =
1113 ih264d_cavlc_parse_8x8block_both_available;
1114
1115 /***************************************************************************/
1116 /* Initialize Bs calculation function pointers for P and B, 16x16/non16x16 */
1117 /***************************************************************************/
1118 ps_dec->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice;
1119 ps_dec->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice;
1120
1121 ps_dec->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice;
1122 ps_dec->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice;
1123
1124 ps_dec->pf_fill_bs_xtra_left_edge[0] =
1125 ih264d_fill_bs_xtra_left_edge_cur_frm;
1126 ps_dec->pf_fill_bs_xtra_left_edge[1] =
1127 ih264d_fill_bs_xtra_left_edge_cur_fld;
1128
1129 /* Initialize Reference Pic Buffers */
1130 ih264d_init_ref_bufs(ps_dec->ps_dpb_mgr);
1131
1132 ps_dec->u2_prv_frame_num = 0;
1133 ps_dec->u1_top_bottom_decoded = 0;
1134 ps_dec->u1_dangling_field = 0;
1135
1136 ps_dec->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table;
1137
1138 ps_dec->pu1_left_mv_ctxt_inc = ps_dec->u1_left_mv_ctxt_inc_arr[0];
1139 ps_dec->pi1_left_ref_idx_ctxt_inc =
1140 &ps_dec->i1_left_ref_idx_ctx_inc_arr[0][0];
1141 ps_dec->pu1_left_yuv_dc_csbp = &ps_dec->u1_yuv_dc_csbp_topmb;
1142
1143 /* ! */
1144 /* Initializing flush frame u4_flag */
1145 ps_dec->u1_flushfrm = 0;
1146
1147 {
1148 ps_dec->s_cab_dec_env.pv_codec_handle = (void*)ps_dec;
1149 ps_dec->ps_bitstrm->pv_codec_handle = (void*)ps_dec;
1150 ps_dec->ps_cur_slice->pv_codec_handle = (void*)ps_dec;
1151 ps_dec->ps_dpb_mgr->pv_codec_handle = (void*)ps_dec;
1152 }
1153
1154 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t));
1155 memset(ps_dec->u4_disp_buf_mapping, 0,
1156 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1157 memset(ps_dec->u4_disp_buf_to_be_freed, 0,
1158 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1159 memset(ps_dec->ps_cur_slice, 0, sizeof(dec_slice_params_t));
1160
1161 ih264d_init_arch(ps_dec);
1162 ih264d_init_function_ptr(ps_dec);
1163 ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT;
1164 ps_dec->init_done = 1;
1165
1166 }
ih264d_free_static_bufs(iv_obj_t * dec_hdl)1167 WORD32 ih264d_free_static_bufs(iv_obj_t *dec_hdl)
1168 {
1169 dec_struct_t *ps_dec;
1170
1171 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1172 void *pv_mem_ctxt;
1173
1174 ps_dec = (dec_struct_t *)dec_hdl->pv_codec_handle;
1175 pf_aligned_free = ps_dec->pf_aligned_free;
1176 pv_mem_ctxt = ps_dec->pv_mem_ctxt;
1177
1178 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sps);
1179 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pps);
1180 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_dec_thread_handle);
1181 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_bs_deblk_thread_handle);
1182 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_mgr);
1183 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred);
1184 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_disp_buf_mgr);
1185 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_pic_buf_mgr);
1186 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pic_buf_base);
1187 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_err_status);
1188 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sei);
1189 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_cmds);
1190 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_bitstrm);
1191 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_cur_slice);
1192 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_scratch_sps_pps);
1193 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_static);
1194 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ppv_map_ref_idx_to_poc_base);
1195 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_cabac_ctxt_table_t);
1196 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mb_ctxt_info);
1197 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_ref_buff_base);
1198 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_pred1);
1199 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_temp_mc_buffer);
1200 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_init_dpb_base);
1201 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_mbaff_wt_mat);
1202 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_wts_ofsts_mat);
1203 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mvpred_addr);
1204 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_mv_buf_mgr);
1205 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_col_mv_base);
1206 PS_DEC_ALIGNED_FREE(ps_dec, dec_hdl->pv_codec_handle);
1207
1208 if(dec_hdl)
1209 {
1210 pf_aligned_free(pv_mem_ctxt, dec_hdl);
1211 }
1212 return IV_SUCCESS;
1213 }
1214 /*****************************************************************************/
1215 /* */
1216 /* Function Name : ih264d_create */
1217 /* */
1218 /* Description : creates decoder */
1219 /* */
1220 /* Inputs :iv_obj_t decoder handle */
1221 /* :pv_api_ip pointer to input structure */
1222 /* :pv_api_op pointer to output structure */
1223 /* Outputs : */
1224 /* Returns : void */
1225 /* */
1226 /* Issues : none */
1227 /* */
1228 /* Revision History: */
1229 /* */
1230 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1231 /* 22 10 2008 100356 Draft */
1232 /* */
1233 /*****************************************************************************/
ih264d_allocate_static_bufs(iv_obj_t ** dec_hdl,void * pv_api_ip,void * pv_api_op)1234 WORD32 ih264d_allocate_static_bufs(iv_obj_t **dec_hdl, void *pv_api_ip, void *pv_api_op)
1235 {
1236 ih264d_create_ip_t *ps_create_ip;
1237 ih264d_create_op_t *ps_create_op;
1238 void *pv_buf;
1239 UWORD8 *pu1_buf;
1240 dec_struct_t *ps_dec;
1241 void *(*pf_aligned_alloc)(void *pv_mem_ctxt, WORD32 alignment, WORD32 size);
1242 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1243 void *pv_mem_ctxt;
1244 WORD32 size;
1245
1246 ps_create_ip = (ih264d_create_ip_t *)pv_api_ip;
1247 ps_create_op = (ih264d_create_op_t *)pv_api_op;
1248
1249 ps_create_op->s_ivd_create_op_t.u4_error_code = 0;
1250
1251 pf_aligned_alloc = ps_create_ip->s_ivd_create_ip_t.pf_aligned_alloc;
1252 pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free;
1253 pv_mem_ctxt = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt;
1254
1255 /* Initialize return handle to NULL */
1256 ps_create_op->s_ivd_create_op_t.pv_handle = NULL;
1257 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(iv_obj_t));
1258 RETURN_IF((NULL == pv_buf), IV_FAIL);
1259 memset(pv_buf, 0, sizeof(iv_obj_t));
1260 *dec_hdl = (iv_obj_t *)pv_buf;
1261 ps_create_op->s_ivd_create_op_t.pv_handle = *dec_hdl;
1262
1263 (*dec_hdl)->pv_codec_handle = NULL;
1264 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(dec_struct_t));
1265 RETURN_IF((NULL == pv_buf), IV_FAIL);
1266 (*dec_hdl)->pv_codec_handle = (dec_struct_t *)pv_buf;
1267 ps_dec = (dec_struct_t *)pv_buf;
1268
1269 memset(ps_dec, 0, sizeof(dec_struct_t));
1270
1271 #ifndef LOGO_EN
1272 ps_dec->u4_share_disp_buf = ps_create_ip->s_ivd_create_ip_t.u4_share_disp_buf;
1273 #else
1274 ps_dec->u4_share_disp_buf = 0;
1275 #endif
1276
1277 ps_dec->u1_chroma_format =
1278 (UWORD8)(ps_create_ip->s_ivd_create_ip_t.e_output_format);
1279
1280 if((ps_dec->u1_chroma_format != IV_YUV_420P)
1281 && (ps_dec->u1_chroma_format
1282 != IV_YUV_420SP_UV)
1283 && (ps_dec->u1_chroma_format
1284 != IV_YUV_420SP_VU))
1285 {
1286 ps_dec->u4_share_disp_buf = 0;
1287 }
1288
1289 ps_dec->pf_aligned_alloc = pf_aligned_alloc;
1290 ps_dec->pf_aligned_free = pf_aligned_free;
1291 ps_dec->pv_mem_ctxt = pv_mem_ctxt;
1292
1293
1294 size = ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS);
1295 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1296 RETURN_IF((NULL == pv_buf), IV_FAIL);
1297 memset(pv_buf, 0, size);
1298 ps_dec->ps_sps = pv_buf;
1299
1300 size = (sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS;
1301 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1302 RETURN_IF((NULL == pv_buf), IV_FAIL);
1303 memset(pv_buf, 0, size);
1304 ps_dec->ps_pps = pv_buf;
1305
1306 size = ithread_get_handle_size();
1307 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1308 RETURN_IF((NULL == pv_buf), IV_FAIL);
1309 memset(pv_buf, 0, size);
1310 ps_dec->pv_dec_thread_handle = pv_buf;
1311
1312 size = ithread_get_handle_size();
1313 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1314 RETURN_IF((NULL == pv_buf), IV_FAIL);
1315 memset(pv_buf, 0, size);
1316 ps_dec->pv_bs_deblk_thread_handle = pv_buf;
1317
1318 size = sizeof(dpb_manager_t);
1319 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1320 RETURN_IF((NULL == pv_buf), IV_FAIL);
1321 memset(pv_buf, 0, size);
1322 ps_dec->ps_dpb_mgr = pv_buf;
1323
1324 size = sizeof(pred_info_t) * 2 * 32;
1325 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1326 RETURN_IF((NULL == pv_buf), IV_FAIL);
1327 memset(pv_buf, 0, size);
1328 ps_dec->ps_pred = pv_buf;
1329
1330 size = sizeof(disp_mgr_t);
1331 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1332 RETURN_IF((NULL == pv_buf), IV_FAIL);
1333 memset(pv_buf, 0, size);
1334 ps_dec->pv_disp_buf_mgr = pv_buf;
1335
1336 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1337 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1338 RETURN_IF((NULL == pv_buf), IV_FAIL);
1339 memset(pv_buf, 0, size);
1340 ps_dec->pv_pic_buf_mgr = pv_buf;
1341
1342 size = sizeof(struct pic_buffer_t) * (H264_MAX_REF_PICS * 2);
1343 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1344 RETURN_IF((NULL == pv_buf), IV_FAIL);
1345 memset(pv_buf, 0, size);
1346 ps_dec->ps_pic_buf_base = pv_buf;
1347
1348 size = sizeof(dec_err_status_t);
1349 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1350 RETURN_IF((NULL == pv_buf), IV_FAIL);
1351 memset(pv_buf, 0, size);
1352 ps_dec->ps_dec_err_status = (dec_err_status_t *)pv_buf;
1353
1354 size = sizeof(sei);
1355 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1356 RETURN_IF((NULL == pv_buf), IV_FAIL);
1357 memset(pv_buf, 0, size);
1358 ps_dec->ps_sei = (sei *)pv_buf;
1359
1360 size = sizeof(dpb_commands_t);
1361 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1362 RETURN_IF((NULL == pv_buf), IV_FAIL);
1363 memset(pv_buf, 0, size);
1364 ps_dec->ps_dpb_cmds = (dpb_commands_t *)pv_buf;
1365
1366 size = sizeof(dec_bit_stream_t);
1367 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1368 RETURN_IF((NULL == pv_buf), IV_FAIL);
1369 memset(pv_buf, 0, size);
1370 ps_dec->ps_bitstrm = (dec_bit_stream_t *)pv_buf;
1371
1372 size = sizeof(dec_slice_params_t);
1373 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1374 RETURN_IF((NULL == pv_buf), IV_FAIL);
1375 memset(pv_buf, 0, size);
1376 ps_dec->ps_cur_slice = (dec_slice_params_t *)pv_buf;
1377
1378 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
1379 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1380 RETURN_IF((NULL == pv_buf), IV_FAIL);
1381 memset(pv_buf, 0, size);
1382 ps_dec->pv_scratch_sps_pps = pv_buf;
1383
1384
1385 ps_dec->u4_static_bits_buf_size = 256000;
1386 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, ps_dec->u4_static_bits_buf_size);
1387 RETURN_IF((NULL == pv_buf), IV_FAIL);
1388 memset(pv_buf, 0, ps_dec->u4_static_bits_buf_size);
1389 ps_dec->pu1_bits_buf_static = pv_buf;
1390
1391
1392 size = ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC)
1393 * sizeof(void *));
1394 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1395 RETURN_IF((NULL == pv_buf), IV_FAIL);
1396 ps_dec->ppv_map_ref_idx_to_poc_base = pv_buf;
1397 memset(ps_dec->ppv_map_ref_idx_to_poc_base, 0, size);
1398
1399 ps_dec->ppv_map_ref_idx_to_poc = ps_dec->ppv_map_ref_idx_to_poc_base + OFFSET_MAP_IDX_POC;
1400
1401
1402 size = (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS);
1403 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1404 RETURN_IF((NULL == pv_buf), IV_FAIL);
1405 memset(pv_buf, 0, size);
1406 ps_dec->p_cabac_ctxt_table_t = pv_buf;
1407
1408
1409
1410 size = sizeof(ctxt_inc_mb_info_t);
1411 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1412 RETURN_IF((NULL == pv_buf), IV_FAIL);
1413 memset(pv_buf, 0, size);
1414 ps_dec->ps_left_mb_ctxt_info = pv_buf;
1415
1416
1417
1418 size = MAX_REF_BUF_SIZE * 2;
1419 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1420 RETURN_IF((NULL == pv_buf), IV_FAIL);
1421 memset(pv_buf, 0, size);
1422 ps_dec->pu1_ref_buff_base = pv_buf;
1423 ps_dec->pu1_ref_buff = ps_dec->pu1_ref_buff_base + MAX_REF_BUF_SIZE;
1424
1425
1426 size = ((sizeof(WORD16)) * PRED_BUFFER_WIDTH
1427 * PRED_BUFFER_HEIGHT * 2);
1428 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1429 RETURN_IF((NULL == pv_buf), IV_FAIL);
1430 memset(pv_buf, 0, size);
1431 ps_dec->pi2_pred1 = pv_buf;
1432
1433
1434 size = sizeof(UWORD8) * (MB_LUM_SIZE);
1435 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1436 RETURN_IF((NULL == pv_buf), IV_FAIL);
1437 memset(pv_buf, 0, size);
1438 ps_dec->pu1_temp_mc_buffer = pv_buf;
1439
1440
1441
1442
1443 size = 8 * MAX_REF_BUFS * sizeof(struct pic_buffer_t);
1444 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1445 RETURN_IF((NULL == pv_buf), IV_FAIL);
1446 memset(pv_buf, 0, size);
1447
1448 ps_dec->pu1_init_dpb_base = pv_buf;
1449 pu1_buf = pv_buf;
1450 ps_dec->ps_dpb_mgr->ps_init_dpb[0][0] = (struct pic_buffer_t *)pu1_buf;
1451
1452 pu1_buf += size / 2;
1453 ps_dec->ps_dpb_mgr->ps_init_dpb[1][0] = (struct pic_buffer_t *)pu1_buf;
1454
1455 size = (sizeof(UWORD32) * 2 * 3
1456 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1)) * 2);
1457 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1458 RETURN_IF((NULL == pv_buf), IV_FAIL);
1459 memset(pv_buf, 0, size);
1460 ps_dec->pu4_mbaff_wt_mat = pv_buf;
1461
1462 size = sizeof(UWORD32) * 2 * 3
1463 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1));
1464 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1465 RETURN_IF((NULL == pv_buf), IV_FAIL);
1466 memset(pv_buf, 0, size);
1467 ps_dec->pu4_wts_ofsts_mat = pv_buf;
1468
1469
1470 size = (sizeof(neighbouradd_t) << 2);
1471 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1472 RETURN_IF((NULL == pv_buf), IV_FAIL);
1473 memset(pv_buf, 0, size);
1474 ps_dec->ps_left_mvpred_addr = pv_buf;
1475
1476
1477 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1478 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1479 RETURN_IF((NULL == pv_buf), IV_FAIL);
1480 memset(pv_buf, 0, size);
1481 ps_dec->pv_mv_buf_mgr = pv_buf;
1482
1483
1484 size = sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2);
1485 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1486 RETURN_IF((NULL == pv_buf), IV_FAIL);
1487 ps_dec->ps_col_mv_base = pv_buf;
1488 memset(ps_dec->ps_col_mv_base, 0, size);
1489
1490 ih264d_init_decoder(ps_dec);
1491
1492 return IV_SUCCESS;
1493 }
1494
1495
1496 /*****************************************************************************/
1497 /* */
1498 /* Function Name : ih264d_create */
1499 /* */
1500 /* Description : creates decoder */
1501 /* */
1502 /* Inputs :iv_obj_t decoder handle */
1503 /* :pv_api_ip pointer to input structure */
1504 /* :pv_api_op pointer to output structure */
1505 /* Outputs : */
1506 /* Returns : void */
1507 /* */
1508 /* Issues : none */
1509 /* */
1510 /* Revision History: */
1511 /* */
1512 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1513 /* 22 10 2008 100356 Draft */
1514 /* */
1515 /*****************************************************************************/
ih264d_create(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)1516 WORD32 ih264d_create(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1517 {
1518 ih264d_create_ip_t *ps_create_ip;
1519 ih264d_create_op_t *ps_create_op;
1520
1521 WORD32 ret;
1522
1523 ps_create_ip = (ih264d_create_ip_t *)pv_api_ip;
1524 ps_create_op = (ih264d_create_op_t *)pv_api_op;
1525
1526 ps_create_op->s_ivd_create_op_t.u4_error_code = 0;
1527 dec_hdl = NULL;
1528 ret = ih264d_allocate_static_bufs(&dec_hdl, pv_api_ip, pv_api_op);
1529
1530 /* If allocation of some buffer fails, then free buffers allocated till then */
1531 if(IV_FAIL == ret)
1532 {
1533 if(dec_hdl)
1534 {
1535 if(dec_hdl->pv_codec_handle)
1536 {
1537 ih264d_free_static_bufs(dec_hdl);
1538 }
1539 else
1540 {
1541 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1542 void *pv_mem_ctxt;
1543
1544 pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free;
1545 pv_mem_ctxt = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt;
1546 pf_aligned_free(pv_mem_ctxt, dec_hdl);
1547 }
1548 }
1549 ps_create_op->s_ivd_create_op_t.u4_error_code = IVD_MEM_ALLOC_FAILED;
1550 ps_create_op->s_ivd_create_op_t.u4_error_code |= 1 << IVD_FATALERROR;
1551
1552 return IV_FAIL;
1553 }
1554
1555 return IV_SUCCESS;
1556 }
1557
1558 /*****************************************************************************/
1559 /* */
1560 /* Function Name : ih264d_map_error */
1561 /* */
1562 /* Description : Maps error codes to IVD error groups */
1563 /* */
1564 /* Inputs : */
1565 /* Globals : <Does it use any global variables?> */
1566 /* Outputs : */
1567 /* Returns : void */
1568 /* */
1569 /* Issues : none */
1570 /* */
1571 /* Revision History: */
1572 /* */
1573 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1574 /* 22 10 2008 100356 Draft */
1575 /* */
1576 /*****************************************************************************/
ih264d_map_error(UWORD32 i4_err_status)1577 UWORD32 ih264d_map_error(UWORD32 i4_err_status)
1578 {
1579 UWORD32 temp = 0;
1580
1581 switch(i4_err_status)
1582 {
1583 case ERROR_MEM_ALLOC_ISRAM_T:
1584 case ERROR_MEM_ALLOC_SDRAM_T:
1585 case ERROR_BUF_MGR:
1586 case ERROR_MB_GROUP_ASSGN_T:
1587 case ERROR_FRAME_LIMIT_OVER:
1588 case ERROR_ACTUAL_RESOLUTION_GREATER_THAN_INIT:
1589 case ERROR_PROFILE_NOT_SUPPORTED:
1590 case ERROR_INIT_NOT_DONE:
1591 case IVD_MEM_ALLOC_FAILED:
1592 case ERROR_FEATURE_UNAVAIL:
1593 case IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED:
1594 temp = 1 << IVD_FATALERROR;
1595 H264_DEC_DEBUG_PRINT("\nFatal Error\n");
1596 break;
1597
1598 case ERROR_DBP_MANAGER_T:
1599 case ERROR_GAPS_IN_FRM_NUM:
1600 case ERROR_UNKNOWN_NAL:
1601 case ERROR_INV_MB_SLC_GRP_T:
1602 case ERROR_MULTIPLE_SLC_GRP_T:
1603 case ERROR_UNKNOWN_LEVEL:
1604 case ERROR_UNAVAIL_PICBUF_T:
1605 case ERROR_UNAVAIL_MVBUF_T:
1606 case ERROR_UNAVAIL_DISPBUF_T:
1607 case ERROR_NUM_REF:
1608 case ERROR_REFIDX_ORDER_T:
1609 case ERROR_PIC0_NOT_FOUND_T:
1610 case ERROR_MB_TYPE:
1611 case ERROR_SUB_MB_TYPE:
1612 case ERROR_CBP:
1613 case ERROR_REF_IDX:
1614 case ERROR_NUM_MV:
1615 case ERROR_CHROMA_PRED_MODE:
1616 case ERROR_INTRAPRED:
1617 case ERROR_NEXT_MB_ADDRESS_T:
1618 case ERROR_MB_ADDRESS_T:
1619 case ERROR_PIC1_NOT_FOUND_T:
1620 case ERROR_CAVLC_NUM_COEFF_T:
1621 case ERROR_CAVLC_SCAN_POS_T:
1622 case ERROR_PRED_WEIGHT_TABLE_T:
1623 case ERROR_CORRUPTED_SLICE:
1624 temp = 1 << IVD_CORRUPTEDDATA;
1625 break;
1626
1627 case ERROR_NOT_SUPP_RESOLUTION:
1628 case ERROR_ACTUAL_LEVEL_GREATER_THAN_INIT:
1629 temp = 1 << IVD_UNSUPPORTEDINPUT;
1630 break;
1631
1632 case ERROR_INVALID_PIC_PARAM:
1633 case ERROR_INVALID_SEQ_PARAM:
1634 case ERROR_EGC_EXCEED_32_1_T:
1635 case ERROR_EGC_EXCEED_32_2_T:
1636 case ERROR_INV_RANGE_TEV_T:
1637 case ERROR_INV_SLC_TYPE_T:
1638 case ERROR_INV_POC_TYPE_T:
1639 case ERROR_INV_RANGE_QP_T:
1640 case ERROR_INV_SPS_PPS_T:
1641 case ERROR_INV_SLICE_HDR_T:
1642 temp = 1 << IVD_CORRUPTEDHEADER;
1643 break;
1644
1645 case ERROR_EOB_FLUSHBITS_T:
1646 case ERROR_EOB_GETBITS_T:
1647 case ERROR_EOB_GETBIT_T:
1648 case ERROR_EOB_BYPASS_T:
1649 case ERROR_EOB_DECISION_T:
1650 case ERROR_EOB_TERMINATE_T:
1651 case ERROR_EOB_READCOEFF4X4CAB_T:
1652 temp = 1 << IVD_INSUFFICIENTDATA;
1653 break;
1654 case ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED:
1655 case ERROR_DISP_WIDTH_RESET_TO_PIC_WIDTH:
1656 temp = 1 << IVD_UNSUPPORTEDPARAM | 1 << IVD_FATALERROR;
1657 break;
1658
1659 case ERROR_DANGLING_FIELD_IN_PIC:
1660 temp = 1 << IVD_APPLIEDCONCEALMENT;
1661 break;
1662
1663 }
1664
1665 return temp;
1666
1667 }
1668
ih264d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht,UWORD8 u1_chroma_format,UWORD32 * p_buf_size)1669 UWORD32 ih264d_get_outbuf_size(WORD32 pic_wd,
1670 UWORD32 pic_ht,
1671 UWORD8 u1_chroma_format,
1672 UWORD32 *p_buf_size)
1673 {
1674 UWORD32 u4_min_num_out_bufs = 0;
1675
1676 if(u1_chroma_format == IV_YUV_420P)
1677 u4_min_num_out_bufs = MIN_OUT_BUFS_420;
1678 else if(u1_chroma_format == IV_YUV_422ILE)
1679 u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
1680 else if(u1_chroma_format == IV_RGB_565)
1681 u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
1682 else if((u1_chroma_format == IV_YUV_420SP_UV)
1683 || (u1_chroma_format == IV_YUV_420SP_VU))
1684 u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
1685
1686 if(u1_chroma_format == IV_YUV_420P)
1687 {
1688 p_buf_size[0] = (pic_wd * pic_ht);
1689 p_buf_size[1] = (pic_wd * pic_ht) >> 2;
1690 p_buf_size[2] = (pic_wd * pic_ht) >> 2;
1691 }
1692 else if(u1_chroma_format == IV_YUV_422ILE)
1693 {
1694 p_buf_size[0] = (pic_wd * pic_ht) * 2;
1695 p_buf_size[1] = p_buf_size[2] = 0;
1696 }
1697 else if(u1_chroma_format == IV_RGB_565)
1698 {
1699 p_buf_size[0] = (pic_wd * pic_ht) * 2;
1700 p_buf_size[1] = p_buf_size[2] = 0;
1701 }
1702 else if((u1_chroma_format == IV_YUV_420SP_UV)
1703 || (u1_chroma_format == IV_YUV_420SP_VU))
1704 {
1705 p_buf_size[0] = (pic_wd * pic_ht);
1706 p_buf_size[1] = (pic_wd * pic_ht) >> 1;
1707 p_buf_size[2] = 0;
1708 }
1709
1710 return u4_min_num_out_bufs;
1711 }
1712
check_app_out_buf_size(dec_struct_t * ps_dec)1713 WORD32 check_app_out_buf_size(dec_struct_t *ps_dec)
1714 {
1715 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
1716 UWORD32 u4_min_num_out_bufs, i;
1717 UWORD32 pic_wd, pic_ht;
1718
1719 if(0 == ps_dec->u4_share_disp_buf)
1720 {
1721 pic_wd = ps_dec->u2_disp_width;
1722 pic_ht = ps_dec->u2_disp_height;
1723
1724 }
1725 else
1726 {
1727 pic_wd = ps_dec->u2_frm_wd_y;
1728 pic_ht = ps_dec->u2_frm_ht_y;
1729 }
1730
1731 if(ps_dec->u4_app_disp_width > pic_wd)
1732 pic_wd = ps_dec->u4_app_disp_width;
1733
1734 u4_min_num_out_bufs = ih264d_get_outbuf_size(pic_wd, pic_ht,
1735 ps_dec->u1_chroma_format,
1736 &au4_min_out_buf_size[0]);
1737
1738
1739 if(0 == ps_dec->u4_share_disp_buf)
1740 {
1741 if(ps_dec->ps_out_buffer->u4_num_bufs < u4_min_num_out_bufs)
1742 return IV_FAIL;
1743
1744 for(i = 0; i < u4_min_num_out_bufs; i++)
1745 {
1746 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i]
1747 < au4_min_out_buf_size[i])
1748 return (IV_FAIL);
1749 }
1750 }
1751 else
1752 {
1753 if(ps_dec->disp_bufs[0].u4_num_bufs < u4_min_num_out_bufs)
1754 return IV_FAIL;
1755
1756 for(i = 0; i < u4_min_num_out_bufs; i++)
1757 {
1758 /* We need to check only with the disp_buffer[0], because we have
1759 * already ensured that all the buffers are of the same size in
1760 * ih264d_set_display_frame.
1761 */
1762 if(ps_dec->disp_bufs[0].u4_bufsize[i] < au4_min_out_buf_size[i])
1763 return (IV_FAIL);
1764 }
1765
1766 }
1767
1768 return (IV_SUCCESS);
1769 }
1770
1771
1772 /*****************************************************************************/
1773 /* */
1774 /* Function Name : ih264d_video_decode */
1775 /* */
1776 /* Description : handle video decode API command */
1777 /* */
1778 /* Inputs :iv_obj_t decoder handle */
1779 /* :pv_api_ip pointer to input structure */
1780 /* :pv_api_op pointer to output structure */
1781 /* Outputs : */
1782 /* Returns : void */
1783 /* */
1784 /* Issues : none */
1785 /* */
1786 /* Revision History: */
1787 /* */
1788 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1789 /* 22 10 2008 100356 Draft */
1790 /* */
1791 /*****************************************************************************/
1792
ih264d_video_decode(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)1793 WORD32 ih264d_video_decode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1794 {
1795 /* ! */
1796
1797 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
1798
1799 WORD32 i4_err_status = 0;
1800 UWORD8 *pu1_buf = NULL;
1801 WORD32 buflen;
1802 UWORD32 u4_max_ofst, u4_length_of_start_code = 0;
1803
1804 UWORD32 bytes_consumed = 0;
1805 UWORD32 cur_slice_is_nonref = 0;
1806 UWORD32 u4_next_is_aud;
1807 UWORD32 u4_first_start_code_found = 0;
1808 WORD32 ret = 0,api_ret_value = IV_SUCCESS;
1809 WORD32 header_data_left = 0,frame_data_left = 0;
1810 UWORD8 *pu1_bitstrm_buf;
1811 ivd_video_decode_ip_t *ps_dec_ip;
1812 ivd_video_decode_op_t *ps_dec_op;
1813
1814 ithread_set_name((void*)"Parse_thread");
1815
1816 ps_dec_ip = (ivd_video_decode_ip_t *)pv_api_ip;
1817 ps_dec_op = (ivd_video_decode_op_t *)pv_api_op;
1818
1819 {
1820 UWORD32 u4_size;
1821 u4_size = ps_dec_op->u4_size;
1822 memset(ps_dec_op, 0, sizeof(ivd_video_decode_op_t));
1823 ps_dec_op->u4_size = u4_size;
1824 }
1825
1826 ps_dec->pv_dec_out = ps_dec_op;
1827 if(ps_dec->init_done != 1)
1828 {
1829 return IV_FAIL;
1830 }
1831
1832 /*Data memory barries instruction,so that bitstream write by the application is complete*/
1833 DATA_SYNC();
1834
1835 if(0 == ps_dec->u1_flushfrm)
1836 {
1837 if(ps_dec_ip->pv_stream_buffer == NULL)
1838 {
1839 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1840 ps_dec_op->u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
1841 return IV_FAIL;
1842 }
1843 if(ps_dec_ip->u4_num_Bytes <= 0)
1844 {
1845 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1846 ps_dec_op->u4_error_code |= IVD_DEC_NUMBYTES_INV;
1847 return IV_FAIL;
1848
1849 }
1850 }
1851 ps_dec->u1_pic_decode_done = 0;
1852
1853 ps_dec_op->u4_num_bytes_consumed = 0;
1854
1855 ps_dec->ps_out_buffer = NULL;
1856
1857 if(ps_dec_ip->u4_size
1858 >= offsetof(ivd_video_decode_ip_t, s_out_buffer))
1859 ps_dec->ps_out_buffer = &ps_dec_ip->s_out_buffer;
1860
1861 ps_dec->u4_fmt_conv_cur_row = 0;
1862
1863 ps_dec->u4_output_present = 0;
1864 ps_dec->s_disp_op.u4_error_code = 1;
1865 ps_dec->u4_fmt_conv_num_rows = FMT_CONV_NUM_ROWS;
1866 if(0 == ps_dec->u4_share_disp_buf
1867 && ps_dec->i4_decode_header == 0)
1868 {
1869 UWORD32 i;
1870 if((ps_dec->ps_out_buffer->u4_num_bufs == 0) ||
1871 (ps_dec->ps_out_buffer->u4_num_bufs > IVD_VIDDEC_MAX_IO_BUFFERS))
1872 {
1873 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1874 ps_dec_op->u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
1875 return IV_FAIL;
1876 }
1877
1878 for(i = 0; i < ps_dec->ps_out_buffer->u4_num_bufs; i++)
1879 {
1880 if(ps_dec->ps_out_buffer->pu1_bufs[i] == NULL)
1881 {
1882 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1883 ps_dec_op->u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
1884 return IV_FAIL;
1885 }
1886
1887 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] == 0)
1888 {
1889 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1890 ps_dec_op->u4_error_code |=
1891 IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
1892 return IV_FAIL;
1893 }
1894 }
1895 }
1896
1897 if(ps_dec->u4_total_frames_decoded >= NUM_FRAMES_LIMIT)
1898 {
1899 ps_dec_op->u4_error_code = ERROR_FRAME_LIMIT_OVER;
1900 return IV_FAIL;
1901 }
1902
1903 /* ! */
1904 ps_dec->u4_ts = ps_dec_ip->u4_ts;
1905
1906 ps_dec_op->u4_error_code = 0;
1907 ps_dec_op->e_pic_type = IV_NA_FRAME;
1908 ps_dec_op->u4_output_present = 0;
1909 ps_dec_op->u4_frame_decoded_flag = 0;
1910
1911 ps_dec->i4_frametype = IV_NA_FRAME;
1912 ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
1913
1914 ps_dec->u4_slice_start_code_found = 0;
1915
1916 /* In case the deocder is not in flush mode(in shared mode),
1917 then decoder has to pick up a buffer to write current frame.
1918 Check if a frame is available in such cases */
1919
1920 if(ps_dec->u1_init_dec_flag == 1 && ps_dec->u4_share_disp_buf == 1
1921 && ps_dec->u1_flushfrm == 0)
1922 {
1923 UWORD32 i;
1924
1925 WORD32 disp_avail = 0, free_id;
1926
1927 /* Check if at least one buffer is available with the codec */
1928 /* If not then return to application with error */
1929 for(i = 0; i < ps_dec->u1_pic_bufs; i++)
1930 {
1931 if(0 == ps_dec->u4_disp_buf_mapping[i]
1932 || 1 == ps_dec->u4_disp_buf_to_be_freed[i])
1933 {
1934 disp_avail = 1;
1935 break;
1936 }
1937
1938 }
1939
1940 if(0 == disp_avail)
1941 {
1942 /* If something is queued for display wait for that buffer to be returned */
1943
1944 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
1945 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
1946 return (IV_FAIL);
1947 }
1948
1949 while(1)
1950 {
1951 pic_buffer_t *ps_pic_buf;
1952 ps_pic_buf = (pic_buffer_t *)ih264_buf_mgr_get_next_free(
1953 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, &free_id);
1954
1955 if(ps_pic_buf == NULL)
1956 {
1957 UWORD32 i, display_queued = 0;
1958
1959 /* check if any buffer was given for display which is not returned yet */
1960 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++)
1961 {
1962 if(0 != ps_dec->u4_disp_buf_mapping[i])
1963 {
1964 display_queued = 1;
1965 break;
1966 }
1967 }
1968 /* If some buffer is queued for display, then codec has to singal an error and wait
1969 for that buffer to be returned.
1970 If nothing is queued for display then codec has ownership of all display buffers
1971 and it can reuse any of the existing buffers and continue decoding */
1972
1973 if(1 == display_queued)
1974 {
1975 /* If something is queued for display wait for that buffer to be returned */
1976 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
1977 ps_dec_op->u4_error_code |= (1
1978 << IVD_UNSUPPORTEDPARAM);
1979 return (IV_FAIL);
1980 }
1981 }
1982 else
1983 {
1984 /* If the buffer is with display, then mark it as in use and then look for a buffer again */
1985 if(1 == ps_dec->u4_disp_buf_mapping[free_id])
1986 {
1987 ih264_buf_mgr_set_status(
1988 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
1989 free_id,
1990 BUF_MGR_IO);
1991 }
1992 else
1993 {
1994 /**
1995 * Found a free buffer for present call. Release it now.
1996 * Will be again obtained later.
1997 */
1998 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
1999 free_id,
2000 BUF_MGR_IO);
2001 break;
2002 }
2003 }
2004 }
2005
2006 }
2007
2008 if(ps_dec->u1_flushfrm)
2009 {
2010 if(ps_dec->u1_init_dec_flag == 0)
2011 {
2012 /*Come out of flush mode and return*/
2013 ps_dec->u1_flushfrm = 0;
2014 return (IV_FAIL);
2015 }
2016
2017
2018
2019 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
2020 &(ps_dec->s_disp_op));
2021 if(0 == ps_dec->s_disp_op.u4_error_code)
2022 {
2023 /* check output buffer size given by the application */
2024 if(check_app_out_buf_size(ps_dec) != IV_SUCCESS)
2025 {
2026 ps_dec_op->u4_error_code= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2027 return (IV_FAIL);
2028 }
2029
2030 ps_dec->u4_fmt_conv_cur_row = 0;
2031 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht;
2032 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
2033 ps_dec->u4_fmt_conv_cur_row,
2034 ps_dec->u4_fmt_conv_num_rows);
2035 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
2036 ps_dec->u4_output_present = 1;
2037
2038 }
2039 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
2040
2041 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
2042 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
2043
2044 ps_dec_op->u4_new_seq = 0;
2045
2046 ps_dec_op->u4_output_present = ps_dec->u4_output_present;
2047 ps_dec_op->u4_progressive_frame_flag =
2048 ps_dec->s_disp_op.u4_progressive_frame_flag;
2049 ps_dec_op->e_output_format =
2050 ps_dec->s_disp_op.e_output_format;
2051 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
2052 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
2053 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
2054 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2055
2056 /*In the case of flush ,since no frame is decoded set pic type as invalid*/
2057 ps_dec_op->u4_is_ref_flag = -1;
2058 ps_dec_op->e_pic_type = IV_NA_FRAME;
2059 ps_dec_op->u4_frame_decoded_flag = 0;
2060
2061 if(0 == ps_dec->s_disp_op.u4_error_code)
2062 {
2063 return (IV_SUCCESS);
2064 }
2065 else
2066 return (IV_FAIL);
2067
2068 }
2069 if(ps_dec->u1_res_changed == 1)
2070 {
2071 /*if resolution has changed and all buffers have been flushed, reset decoder*/
2072 ih264d_init_decoder(ps_dec);
2073 }
2074
2075 ps_dec->u2_cur_mb_addr = 0;
2076 ps_dec->u2_total_mbs_coded = 0;
2077 ps_dec->u2_cur_slice_num = 0;
2078 ps_dec->cur_dec_mb_num = 0;
2079 ps_dec->cur_recon_mb_num = 0;
2080 ps_dec->u4_first_slice_in_pic = 1;
2081 ps_dec->u1_slice_header_done = 0;
2082 ps_dec->u1_dangling_field = 0;
2083
2084 ps_dec->u4_dec_thread_created = 0;
2085 ps_dec->u4_bs_deblk_thread_created = 0;
2086 ps_dec->u4_cur_bs_mb_num = 0;
2087 ps_dec->u4_start_recon_deblk = 0;
2088 ps_dec->u4_sps_cnt_in_process = 0;
2089
2090 DEBUG_THREADS_PRINTF(" Starting process call\n");
2091
2092
2093 ps_dec->u4_pic_buf_got = 0;
2094
2095 do
2096 {
2097 WORD32 buf_size;
2098
2099 pu1_buf = (UWORD8*)ps_dec_ip->pv_stream_buffer
2100 + ps_dec_op->u4_num_bytes_consumed;
2101
2102 u4_max_ofst = ps_dec_ip->u4_num_Bytes
2103 - ps_dec_op->u4_num_bytes_consumed;
2104
2105 /* If dynamic bitstream buffer is not allocated and
2106 * header decode is done, then allocate dynamic bitstream buffer
2107 */
2108 if((NULL == ps_dec->pu1_bits_buf_dynamic) &&
2109 (ps_dec->i4_header_decoded & 1))
2110 {
2111 WORD32 size;
2112
2113 void *pv_buf;
2114 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
2115 size = MAX(256000, ps_dec->u2_pic_wd * ps_dec->u2_pic_ht * 3 / 2);
2116 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128,
2117 size + EXTRA_BS_OFFSET);
2118 RETURN_IF((NULL == pv_buf), IV_FAIL);
2119 memset(pv_buf, 0, size + EXTRA_BS_OFFSET);
2120 ps_dec->pu1_bits_buf_dynamic = pv_buf;
2121 ps_dec->u4_dynamic_bits_buf_size = size;
2122 }
2123
2124 if(ps_dec->pu1_bits_buf_dynamic)
2125 {
2126 pu1_bitstrm_buf = ps_dec->pu1_bits_buf_dynamic;
2127 buf_size = ps_dec->u4_dynamic_bits_buf_size;
2128 }
2129 else
2130 {
2131 pu1_bitstrm_buf = ps_dec->pu1_bits_buf_static;
2132 buf_size = ps_dec->u4_static_bits_buf_size;
2133 }
2134
2135 u4_next_is_aud = 0;
2136
2137 buflen = ih264d_find_start_code(pu1_buf, 0, u4_max_ofst,
2138 &u4_length_of_start_code,
2139 &u4_next_is_aud);
2140
2141 if(buflen == -1)
2142 buflen = 0;
2143 /* Ignore bytes beyond the allocated size of intermediate buffer */
2144 /* Since 8 bytes are read ahead, ensure 8 bytes are free at the
2145 end of the buffer, which will be memset to 0 after emulation prevention */
2146 buflen = MIN(buflen, buf_size - 8);
2147
2148 bytes_consumed = buflen + u4_length_of_start_code;
2149 ps_dec_op->u4_num_bytes_consumed += bytes_consumed;
2150
2151 if(buflen)
2152 {
2153 memcpy(pu1_bitstrm_buf, pu1_buf + u4_length_of_start_code,
2154 buflen);
2155 /* Decoder may read extra 8 bytes near end of the frame */
2156 if((buflen + 8) < buf_size)
2157 {
2158 memset(pu1_bitstrm_buf + buflen, 0, 8);
2159 }
2160 u4_first_start_code_found = 1;
2161
2162 }
2163 else
2164 {
2165 /*start code not found*/
2166
2167 if(u4_first_start_code_found == 0)
2168 {
2169 /*no start codes found in current process call*/
2170
2171 ps_dec->i4_error_code = ERROR_START_CODE_NOT_FOUND;
2172 ps_dec_op->u4_error_code |= 1 << IVD_INSUFFICIENTDATA;
2173
2174 if(ps_dec->u4_pic_buf_got == 0)
2175 {
2176
2177 ih264d_fill_output_struct_from_context(ps_dec,
2178 ps_dec_op);
2179
2180 ps_dec_op->u4_error_code = ps_dec->i4_error_code;
2181 ps_dec_op->u4_frame_decoded_flag = 0;
2182
2183 return (IV_FAIL);
2184 }
2185 else
2186 {
2187 ps_dec->u1_pic_decode_done = 1;
2188 continue;
2189 }
2190 }
2191 else
2192 {
2193 /* a start code has already been found earlier in the same process call*/
2194 frame_data_left = 0;
2195 header_data_left = 0;
2196 continue;
2197 }
2198
2199 }
2200
2201 ret = ih264d_parse_nal_unit(dec_hdl, ps_dec_op,
2202 pu1_bitstrm_buf, buflen);
2203 if(ret != OK)
2204 {
2205 UWORD32 error = ih264d_map_error(ret);
2206 ps_dec_op->u4_error_code = error | ret;
2207 api_ret_value = IV_FAIL;
2208
2209 if((ret == IVD_RES_CHANGED)
2210 || (ret == IVD_MEM_ALLOC_FAILED)
2211 || (ret == ERROR_UNAVAIL_PICBUF_T)
2212 || (ret == ERROR_UNAVAIL_MVBUF_T)
2213 || (ret == ERROR_INV_SPS_PPS_T)
2214 || (ret == ERROR_FEATURE_UNAVAIL)
2215 || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED)
2216 || (ret == IVD_DISP_FRM_ZERO_OP_BUF_SIZE))
2217 {
2218 ps_dec->u4_slice_start_code_found = 0;
2219 break;
2220 }
2221
2222 if((ret == ERROR_INCOMPLETE_FRAME) || (ret == ERROR_DANGLING_FIELD_IN_PIC))
2223 {
2224 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
2225 api_ret_value = IV_FAIL;
2226 break;
2227 }
2228
2229 if(ret == ERROR_IN_LAST_SLICE_OF_PIC)
2230 {
2231 api_ret_value = IV_FAIL;
2232 break;
2233 }
2234
2235 }
2236
2237 header_data_left = ((ps_dec->i4_decode_header == 1)
2238 && (ps_dec->i4_header_decoded != 3)
2239 && (ps_dec_op->u4_num_bytes_consumed
2240 < ps_dec_ip->u4_num_Bytes));
2241 frame_data_left = (((ps_dec->i4_decode_header == 0)
2242 && ((ps_dec->u1_pic_decode_done == 0)
2243 || (u4_next_is_aud == 1)))
2244 && (ps_dec_op->u4_num_bytes_consumed
2245 < ps_dec_ip->u4_num_Bytes));
2246 }
2247 while(( header_data_left == 1)||(frame_data_left == 1));
2248
2249 if((ps_dec->u4_pic_buf_got == 1)
2250 && (ret != IVD_MEM_ALLOC_FAILED)
2251 && ps_dec->u2_total_mbs_coded < ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
2252 {
2253 // last slice - missing/corruption
2254 WORD32 num_mb_skipped;
2255 WORD32 prev_slice_err;
2256 pocstruct_t temp_poc;
2257 WORD32 ret1;
2258 WORD32 ht_in_mbs;
2259 ht_in_mbs = ps_dec->u2_pic_ht >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag);
2260 num_mb_skipped = (ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
2261 - ps_dec->u2_total_mbs_coded;
2262
2263 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_pic_buf_got == 0))
2264 prev_slice_err = 1;
2265 else
2266 prev_slice_err = 2;
2267
2268 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u2_total_mbs_coded == 0))
2269 prev_slice_err = 1;
2270
2271 ret1 = ih264d_mark_err_slice_skip(ps_dec, num_mb_skipped, ps_dec->u1_nal_unit_type == IDR_SLICE_NAL, ps_dec->ps_cur_slice->u2_frame_num,
2272 &temp_poc, prev_slice_err);
2273
2274 if((ret1 == ERROR_UNAVAIL_PICBUF_T) || (ret1 == ERROR_UNAVAIL_MVBUF_T) ||
2275 (ret1 == ERROR_INV_SPS_PPS_T))
2276 {
2277 ret = ret1;
2278 }
2279 }
2280
2281 if((ret == IVD_RES_CHANGED)
2282 || (ret == IVD_MEM_ALLOC_FAILED)
2283 || (ret == ERROR_UNAVAIL_PICBUF_T)
2284 || (ret == ERROR_UNAVAIL_MVBUF_T)
2285 || (ret == ERROR_INV_SPS_PPS_T))
2286 {
2287
2288 /* signal the decode thread */
2289 ih264d_signal_decode_thread(ps_dec);
2290 /* close deblock thread if it is not closed yet */
2291 if(ps_dec->u4_num_cores == 3)
2292 {
2293 ih264d_signal_bs_deblk_thread(ps_dec);
2294 }
2295 /* dont consume bitstream for change in resolution case */
2296 if(ret == IVD_RES_CHANGED)
2297 {
2298 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
2299 }
2300 return IV_FAIL;
2301 }
2302
2303
2304 if(ps_dec->u1_separate_parse)
2305 {
2306 /* If Format conversion is not complete,
2307 complete it here */
2308 if(ps_dec->u4_num_cores == 2)
2309 {
2310
2311 /*do deblocking of all mbs*/
2312 if((ps_dec->u4_nmb_deblk == 0) &&(ps_dec->u4_start_recon_deblk == 1) && (ps_dec->ps_cur_sps->u1_mb_aff_flag == 0))
2313 {
2314 UWORD32 u4_num_mbs,u4_max_addr;
2315 tfr_ctxt_t s_tfr_ctxt;
2316 tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt;
2317 pad_mgr_t *ps_pad_mgr = &ps_dec->s_pad_mgr;
2318
2319 /*BS is done for all mbs while parsing*/
2320 u4_max_addr = (ps_dec->u2_frm_wd_in_mbs * ps_dec->u2_frm_ht_in_mbs) - 1;
2321 ps_dec->u4_cur_bs_mb_num = u4_max_addr + 1;
2322
2323
2324 ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt,
2325 ps_dec->u2_frm_wd_in_mbs, 0);
2326
2327
2328 u4_num_mbs = u4_max_addr
2329 - ps_dec->u4_cur_deblk_mb_num + 1;
2330
2331 DEBUG_PERF_PRINTF("mbs left for deblocking= %d \n",u4_num_mbs);
2332
2333 if(u4_num_mbs != 0)
2334 ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs,
2335 ps_tfr_cxt,1);
2336
2337 ps_dec->u4_start_recon_deblk = 0;
2338
2339 }
2340
2341 }
2342
2343 /*signal the decode thread*/
2344 ih264d_signal_decode_thread(ps_dec);
2345 /* close deblock thread if it is not closed yet*/
2346 if(ps_dec->u4_num_cores == 3)
2347 {
2348 ih264d_signal_bs_deblk_thread(ps_dec);
2349 }
2350 }
2351
2352
2353 DATA_SYNC();
2354
2355
2356 if((ps_dec_op->u4_error_code & 0xff)
2357 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
2358 {
2359 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
2360 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
2361 }
2362
2363 //Report if header (sps and pps) has not been decoded yet
2364 if(ps_dec->i4_decode_header == 1 && ps_dec->i4_header_decoded != 3)
2365 {
2366 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA);
2367 api_ret_value = IV_FAIL;
2368 }
2369
2370 if((ps_dec->u4_pic_buf_got == 1)
2371 && (ERROR_DANGLING_FIELD_IN_PIC != i4_err_status))
2372 {
2373 /*
2374 * For field pictures, set the bottom and top picture decoded u4_flag correctly.
2375 */
2376
2377 if(ps_dec->ps_cur_slice->u1_field_pic_flag)
2378 {
2379 if(1 == ps_dec->ps_cur_slice->u1_bottom_field_flag)
2380 {
2381 ps_dec->u1_top_bottom_decoded |= BOT_FIELD_ONLY;
2382 }
2383 else
2384 {
2385 ps_dec->u1_top_bottom_decoded |= TOP_FIELD_ONLY;
2386 }
2387 }
2388 else
2389 {
2390 ps_dec->u1_top_bottom_decoded = TOP_FIELD_ONLY | BOT_FIELD_ONLY;
2391 }
2392
2393 /* if new frame in not found (if we are still getting slices from previous frame)
2394 * ih264d_deblock_display is not called. Such frames will not be added to reference /display
2395 */
2396 if ((ps_dec->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0)
2397 {
2398 /* Calling Function to deblock Picture and Display */
2399 ret = ih264d_deblock_display(ps_dec);
2400 }
2401
2402
2403 /*set to complete ,as we dont support partial frame decode*/
2404 if(ps_dec->i4_header_decoded == 3)
2405 {
2406 ps_dec->u2_total_mbs_coded = ps_dec->ps_cur_sps->u2_max_mb_addr + 1;
2407 }
2408
2409 /*Update the i4_frametype at the end of picture*/
2410 if(ps_dec->ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL)
2411 {
2412 ps_dec->i4_frametype = IV_IDR_FRAME;
2413 }
2414 else if(ps_dec->i4_pic_type == B_SLICE)
2415 {
2416 ps_dec->i4_frametype = IV_B_FRAME;
2417 }
2418 else if(ps_dec->i4_pic_type == P_SLICE)
2419 {
2420 ps_dec->i4_frametype = IV_P_FRAME;
2421 }
2422 else if(ps_dec->i4_pic_type == I_SLICE)
2423 {
2424 ps_dec->i4_frametype = IV_I_FRAME;
2425 }
2426 else
2427 {
2428 H264_DEC_DEBUG_PRINT("Shouldn't come here\n");
2429 }
2430
2431 //Update the content type
2432 ps_dec->i4_content_type = ps_dec->ps_cur_slice->u1_field_pic_flag;
2433
2434 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded + 2;
2435 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded
2436 - ps_dec->ps_cur_slice->u1_field_pic_flag;
2437
2438 }
2439
2440 /* close deblock thread if it is not closed yet*/
2441 if(ps_dec->u4_num_cores == 3)
2442 {
2443 ih264d_signal_bs_deblk_thread(ps_dec);
2444 }
2445
2446
2447 {
2448 /* In case the decoder is configured to run in low delay mode,
2449 * then get display buffer and then format convert.
2450 * Note in this mode, format conversion does not run paralelly in a thread and adds to the codec cycles
2451 */
2452
2453 if((IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode)
2454 && ps_dec->u1_init_dec_flag)
2455 {
2456
2457 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
2458 &(ps_dec->s_disp_op));
2459 if(0 == ps_dec->s_disp_op.u4_error_code)
2460 {
2461 ps_dec->u4_fmt_conv_cur_row = 0;
2462 ps_dec->u4_output_present = 1;
2463 }
2464 }
2465
2466 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op);
2467
2468 /* If Format conversion is not complete,
2469 complete it here */
2470 if(ps_dec->u4_output_present &&
2471 (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht))
2472 {
2473 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht
2474 - ps_dec->u4_fmt_conv_cur_row;
2475 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
2476 ps_dec->u4_fmt_conv_cur_row,
2477 ps_dec->u4_fmt_conv_num_rows);
2478 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
2479 }
2480
2481 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
2482 }
2483
2484 if(ps_dec->i4_decode_header == 1 && (ps_dec->i4_header_decoded & 1) == 1)
2485 {
2486 ps_dec_op->u4_progressive_frame_flag = 1;
2487 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
2488 {
2489 if((0 == ps_dec->ps_sps->u1_frame_mbs_only_flag)
2490 && (0 == ps_dec->ps_sps->u1_mb_aff_flag))
2491 ps_dec_op->u4_progressive_frame_flag = 0;
2492
2493 }
2494 }
2495
2496 if((TOP_FIELD_ONLY | BOT_FIELD_ONLY) == ps_dec->u1_top_bottom_decoded)
2497 {
2498 ps_dec->u1_top_bottom_decoded = 0;
2499 }
2500 /*--------------------------------------------------------------------*/
2501 /* Do End of Pic processing. */
2502 /* Should be called only if frame was decoded in previous process call*/
2503 /*--------------------------------------------------------------------*/
2504 if(ps_dec->u4_pic_buf_got == 1)
2505 {
2506 if(1 == ps_dec->u1_last_pic_not_decoded)
2507 {
2508 ret = ih264d_end_of_pic_dispbuf_mgr(ps_dec);
2509
2510 if(ret != OK)
2511 return ret;
2512
2513 ret = ih264d_end_of_pic(ps_dec);
2514 if(ret != OK)
2515 return ret;
2516 }
2517 else
2518 {
2519 ret = ih264d_end_of_pic(ps_dec);
2520 if(ret != OK)
2521 return ret;
2522 }
2523
2524 }
2525
2526
2527 /*Data memory barrier instruction,so that yuv write by the library is complete*/
2528 DATA_SYNC();
2529
2530 H264_DEC_DEBUG_PRINT("The num bytes consumed: %d\n",
2531 ps_dec_op->u4_num_bytes_consumed);
2532 return api_ret_value;
2533 }
2534
ih264d_get_version(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2535 WORD32 ih264d_get_version(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2536 {
2537 char version_string[MAXVERSION_STRLEN + 1];
2538 UWORD32 version_string_len;
2539
2540 ivd_ctl_getversioninfo_ip_t *ps_ip;
2541 ivd_ctl_getversioninfo_op_t *ps_op;
2542
2543 ps_ip = (ivd_ctl_getversioninfo_ip_t *)pv_api_ip;
2544 ps_op = (ivd_ctl_getversioninfo_op_t *)pv_api_op;
2545 UNUSED(dec_hdl);
2546 ps_op->u4_error_code = IV_SUCCESS;
2547
2548 VERSION(version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
2549 CODEC_VENDOR);
2550
2551 if((WORD32)ps_ip->u4_version_buffer_size <= 0)
2552 {
2553 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
2554 return (IV_FAIL);
2555 }
2556
2557 version_string_len = strnlen(version_string, MAXVERSION_STRLEN) + 1;
2558
2559 if(ps_ip->u4_version_buffer_size >= version_string_len) //(WORD32)sizeof(sizeof(version_string)))
2560 {
2561 memcpy(ps_ip->pv_version_buffer, version_string, version_string_len);
2562 ps_op->u4_error_code = IV_SUCCESS;
2563 }
2564 else
2565 {
2566 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
2567 return IV_FAIL;
2568 }
2569 return (IV_SUCCESS);
2570 }
2571
2572 /*****************************************************************************/
2573 /* */
2574 /* Function Name : ih264d_get_display_frame */
2575 /* */
2576 /* Description : */
2577 /* Inputs :iv_obj_t decoder handle */
2578 /* :pv_api_ip pointer to input structure */
2579 /* :pv_api_op pointer to output structure */
2580 /* Outputs : */
2581 /* Returns : void */
2582 /* */
2583 /* Issues : none */
2584 /* */
2585 /* Revision History: */
2586 /* */
2587 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2588 /* 22 10 2008 100356 Draft */
2589 /* */
2590 /*****************************************************************************/
ih264d_get_display_frame(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2591 WORD32 ih264d_get_display_frame(iv_obj_t *dec_hdl,
2592 void *pv_api_ip,
2593 void *pv_api_op)
2594 {
2595
2596 UNUSED(dec_hdl);
2597 UNUSED(pv_api_ip);
2598 UNUSED(pv_api_op);
2599 // This function is no longer needed, output is returned in the process()
2600 return IV_FAIL;
2601 }
2602
2603 /*****************************************************************************/
2604 /* */
2605 /* Function Name : ih264d_set_display_frame */
2606 /* */
2607 /* Description : */
2608 /* */
2609 /* Inputs :iv_obj_t decoder handle */
2610 /* :pv_api_ip pointer to input structure */
2611 /* :pv_api_op pointer to output structure */
2612 /* Outputs : */
2613 /* Returns : void */
2614 /* */
2615 /* Issues : none */
2616 /* */
2617 /* Revision History: */
2618 /* */
2619 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2620 /* 22 10 2008 100356 Draft */
2621 /* */
2622 /*****************************************************************************/
ih264d_set_display_frame(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2623 WORD32 ih264d_set_display_frame(iv_obj_t *dec_hdl,
2624 void *pv_api_ip,
2625 void *pv_api_op)
2626 {
2627
2628 UWORD32 u4_disp_buf_size[3], u4_num_disp_bufs;
2629 ivd_set_display_frame_ip_t *dec_disp_ip;
2630 ivd_set_display_frame_op_t *dec_disp_op;
2631
2632 UWORD32 i;
2633 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2634
2635 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
2636 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
2637 dec_disp_op->u4_error_code = 0;
2638
2639
2640 ps_dec->u4_num_disp_bufs = 0;
2641 if(ps_dec->u4_share_disp_buf)
2642 {
2643 UWORD32 u4_num_bufs = dec_disp_ip->num_disp_bufs;
2644
2645 u4_num_bufs = MIN(u4_num_bufs, MAX_DISP_BUFS_NEW);
2646
2647 ps_dec->u4_num_disp_bufs = u4_num_bufs;
2648
2649 /* Get the number and sizes of the first buffer. Compare this with the
2650 * rest to make sure all the buffers are of the same size.
2651 */
2652 u4_num_disp_bufs = dec_disp_ip->s_disp_buffer[0].u4_num_bufs;
2653
2654 u4_disp_buf_size[0] =
2655 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[0];
2656 u4_disp_buf_size[1] =
2657 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[1];
2658 u4_disp_buf_size[2] =
2659 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[2];
2660
2661 for(i = 0; i < u4_num_bufs; i++)
2662 {
2663 if(dec_disp_ip->s_disp_buffer[i].u4_num_bufs != u4_num_disp_bufs)
2664 {
2665 return IV_FAIL;
2666 }
2667
2668 if((dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]
2669 != u4_disp_buf_size[0])
2670 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]
2671 != u4_disp_buf_size[1])
2672 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]
2673 != u4_disp_buf_size[2]))
2674 {
2675 return IV_FAIL;
2676 }
2677
2678 ps_dec->disp_bufs[i].u4_num_bufs =
2679 dec_disp_ip->s_disp_buffer[i].u4_num_bufs;
2680
2681 ps_dec->disp_bufs[i].buf[0] =
2682 dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
2683 ps_dec->disp_bufs[i].buf[1] =
2684 dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
2685 ps_dec->disp_bufs[i].buf[2] =
2686 dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
2687
2688 ps_dec->disp_bufs[i].u4_bufsize[0] =
2689 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0];
2690 ps_dec->disp_bufs[i].u4_bufsize[1] =
2691 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1];
2692 ps_dec->disp_bufs[i].u4_bufsize[2] =
2693 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2];
2694
2695 }
2696 }
2697 return IV_SUCCESS;
2698
2699 }
2700
2701 /*****************************************************************************/
2702 /* */
2703 /* Function Name : ih264d_set_flush_mode */
2704 /* */
2705 /* Description : */
2706 /* */
2707 /* Inputs :iv_obj_t decoder handle */
2708 /* :pv_api_ip pointer to input structure */
2709 /* :pv_api_op pointer to output structure */
2710 /* Globals : <Does it use any global variables?> */
2711 /* Outputs : */
2712 /* Returns : void */
2713 /* */
2714 /* Issues : none */
2715 /* */
2716 /* Revision History: */
2717 /* */
2718 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2719 /* 22 10 2008 100356 Draft */
2720 /* */
2721 /*****************************************************************************/
ih264d_set_flush_mode(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2722 WORD32 ih264d_set_flush_mode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2723 {
2724 dec_struct_t * ps_dec;
2725 ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op;
2726 ps_ctl_op->u4_error_code = 0;
2727
2728 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2729 UNUSED(pv_api_ip);
2730 /* ! */
2731 /* Signal flush frame control call */
2732 ps_dec->u1_flushfrm = 1;
2733
2734 if(ps_dec->u1_init_dec_flag == 1)
2735 {
2736 ih264d_release_pics_in_dpb((void *)ps_dec, ps_dec->u1_pic_bufs);
2737 ih264d_release_display_bufs(ps_dec);
2738 }
2739
2740 ps_ctl_op->u4_error_code = 0;
2741
2742 /* Ignore dangling fields during flush */
2743 ps_dec->u1_top_bottom_decoded = 0;
2744
2745 return IV_SUCCESS;
2746 }
2747
2748 /*****************************************************************************/
2749 /* */
2750 /* Function Name : ih264d_get_status */
2751 /* */
2752 /* Description : */
2753 /* */
2754 /* Inputs :iv_obj_t decoder handle */
2755 /* :pv_api_ip pointer to input structure */
2756 /* :pv_api_op pointer to output structure */
2757 /* Globals : <Does it use any global variables?> */
2758 /* Outputs : */
2759 /* Returns : void */
2760 /* */
2761 /* Issues : none */
2762 /* */
2763 /* Revision History: */
2764 /* */
2765 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2766 /* 22 10 2008 100356 Draft */
2767 /* */
2768 /*****************************************************************************/
2769
ih264d_get_status(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2770 WORD32 ih264d_get_status(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2771 {
2772
2773 UWORD32 i;
2774 dec_struct_t * ps_dec;
2775 UWORD32 pic_wd, pic_ht;
2776 ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op;
2777 UNUSED(pv_api_ip);
2778 ps_ctl_op->u4_error_code = 0;
2779
2780 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2781
2782
2783 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
2784 {
2785 ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height;
2786 ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width;
2787
2788 if(0 == ps_dec->u4_share_disp_buf)
2789 {
2790 pic_wd = ps_dec->u2_disp_width;
2791 pic_ht = ps_dec->u2_disp_height;
2792
2793 }
2794 else
2795 {
2796 pic_wd = ps_dec->u2_frm_wd_y;
2797 pic_ht = ps_dec->u2_frm_ht_y;
2798 }
2799 }
2800 else
2801 {
2802 pic_wd = 0;
2803 pic_ht = 0;
2804
2805 ps_ctl_op->u4_pic_ht = pic_wd;
2806 ps_ctl_op->u4_pic_wd = pic_ht;
2807
2808 if(1 == ps_dec->u4_share_disp_buf)
2809 {
2810 pic_wd += (PAD_LEN_Y_H << 1);
2811 pic_ht += (PAD_LEN_Y_V << 2);
2812
2813 }
2814
2815 }
2816
2817 if(ps_dec->u4_app_disp_width > pic_wd)
2818 pic_wd = ps_dec->u4_app_disp_width;
2819 if(0 == ps_dec->u4_share_disp_buf)
2820 ps_ctl_op->u4_num_disp_bufs = 1;
2821 else
2822 {
2823 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
2824 {
2825 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) &&
2826 (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag))
2827 {
2828 ps_ctl_op->u4_num_disp_bufs =
2829 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1;
2830 }
2831 else
2832 {
2833 /*if VUI is not present assume maximum possible refrence frames for the level,
2834 * as max reorder frames*/
2835 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps);
2836 }
2837
2838 ps_ctl_op->u4_num_disp_bufs +=
2839 ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
2840 }
2841 else
2842 {
2843 ps_ctl_op->u4_num_disp_bufs = 32;
2844 }
2845 ps_ctl_op->u4_num_disp_bufs = MAX(
2846 ps_ctl_op->u4_num_disp_bufs, 6);
2847 ps_ctl_op->u4_num_disp_bufs = MIN(
2848 ps_ctl_op->u4_num_disp_bufs, 32);
2849 }
2850
2851 ps_ctl_op->u4_error_code = ps_dec->i4_error_code;
2852
2853 ps_ctl_op->u4_frame_rate = 0; //make it proper
2854 ps_ctl_op->u4_bit_rate = 0; //make it proper
2855 ps_ctl_op->e_content_type = ps_dec->i4_content_type;
2856 ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format;
2857 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
2858
2859 if(ps_dec->u1_chroma_format == IV_YUV_420P)
2860 {
2861 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420;
2862 }
2863 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
2864 {
2865 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
2866 }
2867 else if(ps_dec->u1_chroma_format == IV_RGB_565)
2868 {
2869 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
2870 }
2871 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
2872 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
2873 {
2874 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
2875 }
2876
2877 else
2878 {
2879 //Invalid chroma format; Error code may be updated, verify in testing if needed
2880 ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL;
2881 return IV_FAIL;
2882 }
2883
2884 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
2885 {
2886 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2);
2887 }
2888
2889 /*!*/
2890 if(ps_dec->u1_chroma_format == IV_YUV_420P)
2891 {
2892 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
2893 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
2894 >> 2;
2895 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht)
2896 >> 2;
2897 }
2898 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
2899 {
2900 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
2901 * 2;
2902 ps_ctl_op->u4_min_out_buf_size[1] =
2903 ps_ctl_op->u4_min_out_buf_size[2] = 0;
2904 }
2905 else if(ps_dec->u1_chroma_format == IV_RGB_565)
2906 {
2907 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
2908 * 2;
2909 ps_ctl_op->u4_min_out_buf_size[1] =
2910 ps_ctl_op->u4_min_out_buf_size[2] = 0;
2911 }
2912 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
2913 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
2914 {
2915 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
2916 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
2917 >> 1;
2918 ps_ctl_op->u4_min_out_buf_size[2] = 0;
2919 }
2920
2921 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
2922 return IV_SUCCESS;
2923 }
2924
2925 /*****************************************************************************/
2926 /* */
2927 /* Function Name : ih264d_get_buf_info */
2928 /* */
2929 /* Description : */
2930 /* */
2931 /* Inputs :iv_obj_t decoder handle */
2932 /* :pv_api_ip pointer to input structure */
2933 /* :pv_api_op pointer to output structure */
2934 /* Globals : <Does it use any global variables?> */
2935 /* Outputs : */
2936 /* Returns : void */
2937 /* */
2938 /* Issues : none */
2939 /* */
2940 /* Revision History: */
2941 /* */
2942 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2943 /* 22 10 2008 100356 Draft */
2944 /* */
2945 /*****************************************************************************/
ih264d_get_buf_info(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)2946 WORD32 ih264d_get_buf_info(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2947 {
2948
2949 dec_struct_t * ps_dec;
2950 UWORD8 i = 0; // Default for 420P format
2951 UWORD16 pic_wd, pic_ht;
2952 ivd_ctl_getbufinfo_op_t *ps_ctl_op =
2953 (ivd_ctl_getbufinfo_op_t*)pv_api_op;
2954 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
2955 UNUSED(pv_api_ip);
2956
2957 ps_ctl_op->u4_error_code = 0;
2958
2959 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2960
2961 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
2962
2963
2964 ps_ctl_op->u4_num_disp_bufs = 1;
2965
2966
2967 pic_wd = 0;
2968 pic_ht = 0;
2969
2970 if(ps_dec->i4_header_decoded == 3)
2971 {
2972
2973 if(0 == ps_dec->u4_share_disp_buf)
2974 {
2975 pic_wd = ps_dec->u2_disp_width;
2976 pic_ht = ps_dec->u2_disp_height;
2977
2978 }
2979 else
2980 {
2981 pic_wd = ps_dec->u2_frm_wd_y;
2982 pic_ht = ps_dec->u2_frm_ht_y;
2983 }
2984
2985 }
2986
2987 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
2988 {
2989 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2);
2990 }
2991 if((WORD32)ps_dec->u4_app_disp_width > pic_wd)
2992 pic_wd = ps_dec->u4_app_disp_width;
2993
2994 if(0 == ps_dec->u4_share_disp_buf)
2995 ps_ctl_op->u4_num_disp_bufs = 1;
2996 else
2997 {
2998 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
2999 {
3000 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) &&
3001 (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag))
3002 {
3003 ps_ctl_op->u4_num_disp_bufs =
3004 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1;
3005 }
3006 else
3007 {
3008 /*if VUI is not present assume maximum possible refrence frames for the level,
3009 * as max reorder frames*/
3010 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps);
3011 }
3012
3013 ps_ctl_op->u4_num_disp_bufs +=
3014 ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
3015
3016 }
3017 else
3018 {
3019 ps_ctl_op->u4_num_disp_bufs = 32;
3020
3021 }
3022
3023 ps_ctl_op->u4_num_disp_bufs = MAX(
3024 ps_ctl_op->u4_num_disp_bufs, 6);
3025 ps_ctl_op->u4_num_disp_bufs = MIN(
3026 ps_ctl_op->u4_num_disp_bufs, 32);
3027 }
3028
3029 ps_ctl_op->u4_min_num_out_bufs = ih264d_get_outbuf_size(
3030 pic_wd, pic_ht, ps_dec->u1_chroma_format,
3031 &au4_min_out_buf_size[0]);
3032
3033 for(i = 0; i < ps_ctl_op->u4_min_num_out_bufs; i++)
3034 {
3035 ps_ctl_op->u4_min_out_buf_size[i] = au4_min_out_buf_size[i];
3036 }
3037
3038 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
3039
3040 return IV_SUCCESS;
3041 }
3042
3043 /*****************************************************************************/
3044 /* */
3045 /* Function Name : ih264d_set_params */
3046 /* */
3047 /* Description : */
3048 /* */
3049 /* Inputs :iv_obj_t decoder handle */
3050 /* :pv_api_ip pointer to input structure */
3051 /* :pv_api_op pointer to output structure */
3052 /* Outputs : */
3053 /* Returns : void */
3054 /* */
3055 /* Issues : none */
3056 /* */
3057 /* Revision History: */
3058 /* */
3059 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3060 /* 22 10 2008 100356 Draft */
3061 /* */
3062 /*****************************************************************************/
ih264d_set_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3063 WORD32 ih264d_set_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3064 {
3065
3066 dec_struct_t * ps_dec;
3067 WORD32 ret = IV_SUCCESS;
3068
3069 ivd_ctl_set_config_ip_t *ps_ctl_ip =
3070 (ivd_ctl_set_config_ip_t *)pv_api_ip;
3071 ivd_ctl_set_config_op_t *ps_ctl_op =
3072 (ivd_ctl_set_config_op_t *)pv_api_op;
3073
3074 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3075
3076 ps_dec->u4_skip_frm_mask = 0;
3077
3078 ps_ctl_op->u4_error_code = 0;
3079
3080 if(ps_ctl_ip->e_frm_skip_mode != IVD_SKIP_NONE)
3081 {
3082 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3083 ret = IV_FAIL;
3084 }
3085
3086 if(ps_ctl_ip->u4_disp_wd >= ps_dec->u2_pic_wd)
3087 {
3088 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
3089 }
3090 else if(0 == ps_dec->i4_header_decoded)
3091 {
3092 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
3093 }
3094 else if(ps_ctl_ip->u4_disp_wd == 0)
3095 {
3096 ps_dec->u4_app_disp_width = 0;
3097 }
3098 else
3099 {
3100 /*
3101 * Set the display width to zero. This will ensure that the wrong value we had stored (0xFFFFFFFF)
3102 * does not propogate.
3103 */
3104 ps_dec->u4_app_disp_width = 0;
3105 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
3106 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID;
3107 ret = IV_FAIL;
3108 }
3109
3110 if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_FRAME)
3111 ps_dec->i4_decode_header = 0;
3112 else if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_HEADER)
3113 ps_dec->i4_decode_header = 1;
3114 else
3115 {
3116 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3117 ps_dec->i4_decode_header = 1;
3118 ret = IV_FAIL;
3119 }
3120 ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT;
3121
3122 if((ps_ctl_ip->e_frm_out_mode != IVD_DECODE_FRAME_OUT) &&
3123 (ps_ctl_ip->e_frm_out_mode != IVD_DISPLAY_FRAME_OUT))
3124 {
3125 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3126 ret = IV_FAIL;
3127 }
3128 ps_dec->e_frm_out_mode = ps_ctl_ip->e_frm_out_mode;
3129 return ret;
3130
3131 }
3132
3133 /*****************************************************************************/
3134 /* */
3135 /* Function Name : ih264d_set_default_params */
3136 /* */
3137 /* Description : */
3138 /* */
3139 /* Inputs :iv_obj_t decoder handle */
3140 /* :pv_api_ip pointer to input structure */
3141 /* :pv_api_op pointer to output structure */
3142 /* Outputs : */
3143 /* Returns : void */
3144 /* */
3145 /* Issues : none */
3146 /* */
3147 /* Revision History: */
3148 /* */
3149 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3150 /* 08 08 2011 100421 Copied from set_params */
3151 /* */
3152 /*****************************************************************************/
ih264d_set_default_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3153 WORD32 ih264d_set_default_params(iv_obj_t *dec_hdl,
3154 void *pv_api_ip,
3155 void *pv_api_op)
3156 {
3157
3158 dec_struct_t * ps_dec;
3159 WORD32 ret = IV_SUCCESS;
3160
3161 ivd_ctl_set_config_op_t *ps_ctl_op =
3162 (ivd_ctl_set_config_op_t *)pv_api_op;
3163 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3164 UNUSED(pv_api_ip);
3165
3166
3167 {
3168 ps_dec->u4_app_disp_width = 0;
3169 ps_dec->u4_skip_frm_mask = 0;
3170 ps_dec->i4_decode_header = 1;
3171
3172 ps_ctl_op->u4_error_code = 0;
3173 }
3174
3175
3176 return ret;
3177 }
3178 /*****************************************************************************/
3179 /* */
3180 /* Function Name : ih264d_reset */
3181 /* */
3182 /* Description : */
3183 /* */
3184 /* Inputs :iv_obj_t decoder handle */
3185 /* :pv_api_ip pointer to input structure */
3186 /* :pv_api_op pointer to output structure */
3187 /* Globals : <Does it use any global variables?> */
3188 /* Outputs : */
3189 /* Returns : void */
3190 /* */
3191 /* Issues : none */
3192 /* */
3193 /* Revision History: */
3194 /* */
3195 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3196 /* 22 10 2008 100356 Draft */
3197 /* */
3198 /*****************************************************************************/
ih264d_delete(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3199 WORD32 ih264d_delete(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3200 {
3201 dec_struct_t *ps_dec;
3202 ih264d_delete_ip_t *ps_ip = (ih264d_delete_ip_t *)pv_api_ip;
3203 ih264d_delete_op_t *ps_op = (ih264d_delete_op_t *)pv_api_op;
3204
3205 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3206 UNUSED(ps_ip);
3207 ps_op->s_ivd_delete_op_t.u4_error_code = 0;
3208 ih264d_free_dynamic_bufs(ps_dec);
3209 ih264d_free_static_bufs(dec_hdl);
3210 return IV_SUCCESS;
3211 }
3212 /*****************************************************************************/
3213 /* */
3214 /* Function Name : ih264d_reset */
3215 /* */
3216 /* Description : */
3217 /* */
3218 /* Inputs :iv_obj_t decoder handle */
3219 /* :pv_api_ip pointer to input structure */
3220 /* :pv_api_op pointer to output structure */
3221 /* Globals : <Does it use any global variables?> */
3222 /* Outputs : */
3223 /* Returns : void */
3224 /* */
3225 /* Issues : none */
3226 /* */
3227 /* Revision History: */
3228 /* */
3229 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3230 /* 22 10 2008 100356 Draft */
3231 /* */
3232 /*****************************************************************************/
ih264d_reset(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3233 WORD32 ih264d_reset(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3234 {
3235 dec_struct_t * ps_dec;
3236 ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op;
3237 UNUSED(pv_api_ip);
3238 ps_ctl_op->u4_error_code = 0;
3239
3240 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3241
3242 if(ps_dec != NULL)
3243 {
3244 ih264d_init_decoder(ps_dec);
3245 }
3246 else
3247 {
3248 H264_DEC_DEBUG_PRINT(
3249 "\nReset called without Initializing the decoder\n");
3250 ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE;
3251 }
3252
3253 return IV_SUCCESS;
3254 }
3255
3256 /*****************************************************************************/
3257 /* */
3258 /* Function Name : ih264d_ctl */
3259 /* */
3260 /* Description : */
3261 /* */
3262 /* Inputs :iv_obj_t decoder handle */
3263 /* :pv_api_ip pointer to input structure */
3264 /* :pv_api_op pointer to output structure */
3265 /* Outputs : */
3266 /* Returns : void */
3267 /* */
3268 /* Issues : none */
3269 /* */
3270 /* Revision History: */
3271 /* */
3272 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3273 /* 22 10 2008 100356 Draft */
3274 /* */
3275 /*****************************************************************************/
ih264d_ctl(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3276 WORD32 ih264d_ctl(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3277 {
3278 ivd_ctl_set_config_ip_t *ps_ctl_ip;
3279 ivd_ctl_set_config_op_t *ps_ctl_op;
3280 WORD32 ret = IV_SUCCESS;
3281 UWORD32 subcommand;
3282 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3283
3284 if(ps_dec->init_done != 1)
3285 {
3286 //Return proper Error Code
3287 return IV_FAIL;
3288 }
3289 ps_ctl_ip = (ivd_ctl_set_config_ip_t*)pv_api_ip;
3290 ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op;
3291 ps_ctl_op->u4_error_code = 0;
3292 subcommand = ps_ctl_ip->e_sub_cmd;
3293
3294 switch(subcommand)
3295 {
3296 case IVD_CMD_CTL_GETPARAMS:
3297 ret = ih264d_get_status(dec_hdl, (void *)pv_api_ip,
3298 (void *)pv_api_op);
3299 break;
3300 case IVD_CMD_CTL_SETPARAMS:
3301 ret = ih264d_set_params(dec_hdl, (void *)pv_api_ip,
3302 (void *)pv_api_op);
3303 break;
3304 case IVD_CMD_CTL_RESET:
3305 ret = ih264d_reset(dec_hdl, (void *)pv_api_ip, (void *)pv_api_op);
3306 break;
3307 case IVD_CMD_CTL_SETDEFAULT:
3308 ret = ih264d_set_default_params(dec_hdl, (void *)pv_api_ip,
3309 (void *)pv_api_op);
3310 break;
3311 case IVD_CMD_CTL_FLUSH:
3312 ret = ih264d_set_flush_mode(dec_hdl, (void *)pv_api_ip,
3313 (void *)pv_api_op);
3314 break;
3315 case IVD_CMD_CTL_GETBUFINFO:
3316 ret = ih264d_get_buf_info(dec_hdl, (void *)pv_api_ip,
3317 (void *)pv_api_op);
3318 break;
3319 case IVD_CMD_CTL_GETVERSION:
3320 ret = ih264d_get_version(dec_hdl, (void *)pv_api_ip,
3321 (void *)pv_api_op);
3322 break;
3323 case IH264D_CMD_CTL_DEGRADE:
3324 ret = ih264d_set_degrade(dec_hdl, (void *)pv_api_ip,
3325 (void *)pv_api_op);
3326 break;
3327
3328 case IH264D_CMD_CTL_SET_NUM_CORES:
3329 ret = ih264d_set_num_cores(dec_hdl, (void *)pv_api_ip,
3330 (void *)pv_api_op);
3331 break;
3332 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
3333 ret = ih264d_get_frame_dimensions(dec_hdl, (void *)pv_api_ip,
3334 (void *)pv_api_op);
3335 break;
3336 case IH264D_CMD_CTL_GET_VUI_PARAMS:
3337 ret = ih264d_get_vui_params(dec_hdl, (void *)pv_api_ip,
3338 (void *)pv_api_op);
3339 break;
3340
3341 case IH264D_CMD_CTL_SET_PROCESSOR:
3342 ret = ih264d_set_processor(dec_hdl, (void *)pv_api_ip,
3343 (void *)pv_api_op);
3344 break;
3345 default:
3346 H264_DEC_DEBUG_PRINT("\ndo nothing\n")
3347 ;
3348 break;
3349 }
3350
3351 return ret;
3352 }
3353 /*****************************************************************************/
3354 /* */
3355 /* Function Name : ih264d_rel_display_frame */
3356 /* */
3357 /* Description : */
3358 /* */
3359 /* Inputs :iv_obj_t decoder handle */
3360 /* :pv_api_ip pointer to input structure */
3361 /* :pv_api_op pointer to output structure */
3362 /* Outputs : */
3363 /* Returns : void */
3364 /* */
3365 /* Issues : none */
3366 /* */
3367 /* Revision History: */
3368 /* */
3369 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3370 /* 22 10 2008 100356 Draft */
3371 /* */
3372 /*****************************************************************************/
ih264d_rel_display_frame(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3373 WORD32 ih264d_rel_display_frame(iv_obj_t *dec_hdl,
3374 void *pv_api_ip,
3375 void *pv_api_op)
3376 {
3377
3378 ivd_rel_display_frame_ip_t *ps_rel_ip;
3379 ivd_rel_display_frame_op_t *ps_rel_op;
3380 UWORD32 buf_released = 0;
3381
3382 UWORD32 u4_ts = 0;
3383 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3384
3385 ps_rel_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
3386 ps_rel_op = (ivd_rel_display_frame_op_t *)pv_api_op;
3387 ps_rel_op->u4_error_code = 0;
3388 u4_ts = ps_rel_ip->u4_disp_buf_id;
3389
3390 if(0 == ps_dec->u4_share_disp_buf)
3391 {
3392 ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
3393 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 0;
3394 return IV_SUCCESS;
3395 }
3396
3397 if(ps_dec->pv_pic_buf_mgr != NULL)
3398 {
3399 if(1 == ps_dec->u4_disp_buf_mapping[u4_ts])
3400 {
3401 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
3402 ps_rel_ip->u4_disp_buf_id,
3403 BUF_MGR_IO);
3404 ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
3405 buf_released = 1;
3406 }
3407 }
3408
3409 if((1 == ps_dec->u4_share_disp_buf) && (0 == buf_released))
3410 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 1;
3411
3412 return IV_SUCCESS;
3413 }
3414
3415 /**
3416 *******************************************************************************
3417 *
3418 * @brief
3419 * Sets degrade params
3420 *
3421 * @par Description:
3422 * Sets degrade params.
3423 * Refer to ih264d_ctl_degrade_ip_t definition for details
3424 *
3425 * @param[in] ps_codec_obj
3426 * Pointer to codec object at API level
3427 *
3428 * @param[in] pv_api_ip
3429 * Pointer to input argument structure
3430 *
3431 * @param[out] pv_api_op
3432 * Pointer to output argument structure
3433 *
3434 * @returns Status
3435 *
3436 * @remarks
3437 *
3438 *
3439 *******************************************************************************
3440 */
3441
ih264d_set_degrade(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)3442 WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
3443 void *pv_api_ip,
3444 void *pv_api_op)
3445 {
3446 ih264d_ctl_degrade_ip_t *ps_ip;
3447 ih264d_ctl_degrade_op_t *ps_op;
3448 dec_struct_t *ps_codec = (dec_struct_t *)ps_codec_obj->pv_codec_handle;
3449
3450 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
3451 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
3452
3453 ps_codec->i4_degrade_type = ps_ip->i4_degrade_type;
3454 ps_codec->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval;
3455 ps_codec->i4_degrade_pics = ps_ip->i4_degrade_pics;
3456
3457 ps_op->u4_error_code = 0;
3458 ps_codec->i4_degrade_pic_cnt = 0;
3459
3460 return IV_SUCCESS;
3461 }
3462
ih264d_get_frame_dimensions(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3463 WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
3464 void *pv_api_ip,
3465 void *pv_api_op)
3466 {
3467 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
3468 ih264d_ctl_get_frame_dimensions_op_t *ps_op;
3469 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3470 UWORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
3471
3472 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
3473
3474 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
3475 UNUSED(ps_ip);
3476 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3477 {
3478 disp_wd = ps_dec->u2_disp_width;
3479 disp_ht = ps_dec->u2_disp_height;
3480
3481 if(0 == ps_dec->u4_share_disp_buf)
3482 {
3483 buffer_wd = disp_wd;
3484 buffer_ht = disp_ht;
3485 }
3486 else
3487 {
3488 buffer_wd = ps_dec->u2_frm_wd_y;
3489 buffer_ht = ps_dec->u2_frm_ht_y;
3490 }
3491 }
3492 else
3493 {
3494 disp_wd = 0;
3495 disp_ht = 0;
3496
3497 if(0 == ps_dec->u4_share_disp_buf)
3498 {
3499 buffer_wd = disp_wd;
3500 buffer_ht = disp_ht;
3501 }
3502 else
3503 {
3504 buffer_wd = ALIGN16(disp_wd) + (PAD_LEN_Y_H << 1);
3505 buffer_ht = ALIGN16(disp_ht) + (PAD_LEN_Y_V << 2);
3506 }
3507 }
3508 if(ps_dec->u4_app_disp_width > buffer_wd)
3509 buffer_wd = ps_dec->u4_app_disp_width;
3510
3511 if(0 == ps_dec->u4_share_disp_buf)
3512 {
3513 x_offset = 0;
3514 y_offset = 0;
3515 }
3516 else
3517 {
3518 y_offset = (PAD_LEN_Y_V << 1);
3519 x_offset = PAD_LEN_Y_H;
3520
3521 if((NULL != ps_dec->ps_sps) && (1 == (ps_dec->ps_sps->u1_is_valid))
3522 && (0 != ps_dec->u2_crop_offset_y))
3523 {
3524 y_offset += ps_dec->u2_crop_offset_y / ps_dec->u2_frm_wd_y;
3525 x_offset += ps_dec->u2_crop_offset_y % ps_dec->u2_frm_wd_y;
3526 }
3527 }
3528
3529 ps_op->u4_disp_wd[0] = disp_wd;
3530 ps_op->u4_disp_ht[0] = disp_ht;
3531 ps_op->u4_buffer_wd[0] = buffer_wd;
3532 ps_op->u4_buffer_ht[0] = buffer_ht;
3533 ps_op->u4_x_offset[0] = x_offset;
3534 ps_op->u4_y_offset[0] = y_offset;
3535
3536 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
3537 >> 1);
3538 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
3539 >> 1);
3540 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
3541 >> 1);
3542 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
3543 >> 1);
3544 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] =
3545 (ps_op->u4_x_offset[0] >> 1);
3546 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] =
3547 (ps_op->u4_y_offset[0] >> 1);
3548
3549 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3550 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3551 {
3552 ps_op->u4_disp_wd[2] = 0;
3553 ps_op->u4_disp_ht[2] = 0;
3554 ps_op->u4_buffer_wd[2] = 0;
3555 ps_op->u4_buffer_ht[2] = 0;
3556 ps_op->u4_x_offset[2] = 0;
3557 ps_op->u4_y_offset[2] = 0;
3558
3559 ps_op->u4_disp_wd[1] <<= 1;
3560 ps_op->u4_buffer_wd[1] <<= 1;
3561 ps_op->u4_x_offset[1] <<= 1;
3562 }
3563
3564 return IV_SUCCESS;
3565
3566 }
3567
ih264d_get_vui_params(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3568 WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl,
3569 void *pv_api_ip,
3570 void *pv_api_op)
3571 {
3572 ih264d_ctl_get_vui_params_ip_t *ps_ip;
3573 ih264d_ctl_get_vui_params_op_t *ps_op;
3574 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3575 dec_seq_params_t *ps_sps;
3576 vui_t *ps_vui;
3577 WORD32 i;
3578 UWORD32 u4_size;
3579
3580 ps_ip = (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip;
3581 ps_op = (ih264d_ctl_get_vui_params_op_t *)pv_api_op;
3582 UNUSED(ps_ip);
3583
3584 u4_size = ps_op->u4_size;
3585 memset(ps_op, 0, sizeof(ih264d_ctl_get_vui_params_op_t));
3586 ps_op->u4_size = u4_size;
3587
3588 if(NULL == ps_dec->ps_cur_sps)
3589 {
3590 ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND;
3591 return IV_FAIL;
3592 }
3593
3594 ps_sps = ps_dec->ps_cur_sps;
3595 if((0 == ps_sps->u1_is_valid)
3596 || (0 == ps_sps->u1_vui_parameters_present_flag))
3597 {
3598 ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND;
3599 return IV_FAIL;
3600 }
3601
3602 ps_vui = &ps_sps->s_vui;
3603
3604 ps_op->u1_aspect_ratio_idc = ps_vui->u1_aspect_ratio_idc;
3605 ps_op->u2_sar_width = ps_vui->u2_sar_width;
3606 ps_op->u2_sar_height = ps_vui->u2_sar_height;
3607 ps_op->u1_overscan_appropriate_flag = ps_vui->u1_overscan_appropriate_flag;
3608 ps_op->u1_video_format = ps_vui->u1_video_format;
3609 ps_op->u1_video_full_range_flag = ps_vui->u1_video_full_range_flag;
3610 ps_op->u1_colour_primaries = ps_vui->u1_colour_primaries;
3611 ps_op->u1_tfr_chars = ps_vui->u1_tfr_chars;
3612 ps_op->u1_matrix_coeffs = ps_vui->u1_matrix_coeffs;
3613 ps_op->u1_cr_top_field = ps_vui->u1_cr_top_field;
3614 ps_op->u1_cr_bottom_field = ps_vui->u1_cr_bottom_field;
3615 ps_op->u4_num_units_in_tick = ps_vui->u4_num_units_in_tick;
3616 ps_op->u4_time_scale = ps_vui->u4_time_scale;
3617 ps_op->u1_fixed_frame_rate_flag = ps_vui->u1_fixed_frame_rate_flag;
3618 ps_op->u1_nal_hrd_params_present = ps_vui->u1_nal_hrd_params_present;
3619 ps_op->u1_vcl_hrd_params_present = ps_vui->u1_vcl_hrd_params_present;
3620 ps_op->u1_low_delay_hrd_flag = ps_vui->u1_low_delay_hrd_flag;
3621 ps_op->u1_pic_struct_present_flag = ps_vui->u1_pic_struct_present_flag;
3622 ps_op->u1_bitstream_restriction_flag = ps_vui->u1_bitstream_restriction_flag;
3623 ps_op->u1_mv_over_pic_boundaries_flag = ps_vui->u1_mv_over_pic_boundaries_flag;
3624 ps_op->u4_max_bytes_per_pic_denom = ps_vui->u4_max_bytes_per_pic_denom;
3625 ps_op->u4_max_bits_per_mb_denom = ps_vui->u4_max_bits_per_mb_denom;
3626 ps_op->u4_log2_max_mv_length_horz = ps_vui->u4_log2_max_mv_length_horz;
3627 ps_op->u4_log2_max_mv_length_vert = ps_vui->u4_log2_max_mv_length_vert;
3628 ps_op->u4_num_reorder_frames = ps_vui->u4_num_reorder_frames;
3629 ps_op->u4_max_dec_frame_buffering = ps_vui->u4_max_dec_frame_buffering;
3630
3631 return IV_SUCCESS;
3632 }
3633
ih264d_set_num_cores(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3634 WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3635 {
3636 ih264d_ctl_set_num_cores_ip_t *ps_ip;
3637 ih264d_ctl_set_num_cores_op_t *ps_op;
3638 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3639
3640 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
3641 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
3642 ps_op->u4_error_code = 0;
3643 ps_dec->u4_num_cores = ps_ip->u4_num_cores;
3644 if(ps_dec->u4_num_cores == 1)
3645 {
3646 ps_dec->u1_separate_parse = 0;
3647 }
3648 else
3649 {
3650 ps_dec->u1_separate_parse = 1;
3651 }
3652
3653 /*using only upto three threads currently*/
3654 if(ps_dec->u4_num_cores > 3)
3655 ps_dec->u4_num_cores = 3;
3656
3657 return IV_SUCCESS;
3658 }
3659
ih264d_fill_output_struct_from_context(dec_struct_t * ps_dec,ivd_video_decode_op_t * ps_dec_op)3660 void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
3661 ivd_video_decode_op_t *ps_dec_op)
3662 {
3663 if((ps_dec_op->u4_error_code & 0xff)
3664 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
3665 {
3666 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
3667 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
3668 }
3669 ps_dec_op->e_pic_type = ps_dec->i4_frametype;
3670
3671 ps_dec_op->u4_new_seq = 0;
3672 ps_dec_op->u4_output_present = ps_dec->u4_output_present;
3673 ps_dec_op->u4_progressive_frame_flag =
3674 ps_dec->s_disp_op.u4_progressive_frame_flag;
3675
3676 ps_dec_op->u4_is_ref_flag = 1;
3677 if(ps_dec_op->u4_frame_decoded_flag)
3678 {
3679 if(ps_dec->ps_cur_slice->u1_nal_ref_idc == 0)
3680 ps_dec_op->u4_is_ref_flag = 0;
3681 }
3682
3683 ps_dec_op->e_output_format = ps_dec->s_disp_op.e_output_format;
3684 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
3685 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
3686 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
3687 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
3688 }
3689
3690 /*****************************************************************************/
3691 /* */
3692 /* Function Name : ih264d_api_function */
3693 /* */
3694 /* Description : */
3695 /* */
3696 /* Inputs :iv_obj_t decoder handle */
3697 /* :pv_api_ip pointer to input structure */
3698 /* :pv_api_op pointer to output structure */
3699 /* Outputs : */
3700 /* Returns : void */
3701 /* */
3702 /* Issues : none */
3703 /* */
3704 /* Revision History: */
3705 /* */
3706 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3707 /* 22 10 2008 100356 Draft */
3708 /* */
3709 /*****************************************************************************/
ih264d_api_function(iv_obj_t * dec_hdl,void * pv_api_ip,void * pv_api_op)3710 IV_API_CALL_STATUS_T ih264d_api_function(iv_obj_t *dec_hdl,
3711 void *pv_api_ip,
3712 void *pv_api_op)
3713 {
3714 UWORD32 command;
3715 UWORD32 *pu2_ptr_cmd;
3716 UWORD32 u4_api_ret;
3717 IV_API_CALL_STATUS_T e_status;
3718 e_status = api_check_struct_sanity(dec_hdl, pv_api_ip, pv_api_op);
3719
3720 if(e_status != IV_SUCCESS)
3721 {
3722 UWORD32 *ptr_err;
3723
3724 ptr_err = (UWORD32 *)pv_api_op;
3725 UNUSED(ptr_err);
3726 H264_DEC_DEBUG_PRINT("error code = %d\n", *(ptr_err + 1));
3727 return IV_FAIL;
3728 }
3729
3730 pu2_ptr_cmd = (UWORD32 *)pv_api_ip;
3731 pu2_ptr_cmd++;
3732
3733 command = *pu2_ptr_cmd;
3734 // H264_DEC_DEBUG_PRINT("inside lib = %d\n",command);
3735 switch(command)
3736 {
3737
3738 case IVD_CMD_CREATE:
3739 u4_api_ret = ih264d_create(dec_hdl, (void *)pv_api_ip,
3740 (void *)pv_api_op);
3741 break;
3742 case IVD_CMD_DELETE:
3743 u4_api_ret = ih264d_delete(dec_hdl, (void *)pv_api_ip,
3744 (void *)pv_api_op);
3745 break;
3746
3747 case IVD_CMD_VIDEO_DECODE:
3748 u4_api_ret = ih264d_video_decode(dec_hdl, (void *)pv_api_ip,
3749 (void *)pv_api_op);
3750 break;
3751
3752 case IVD_CMD_GET_DISPLAY_FRAME:
3753 u4_api_ret = ih264d_get_display_frame(dec_hdl, (void *)pv_api_ip,
3754 (void *)pv_api_op);
3755
3756 break;
3757
3758 case IVD_CMD_SET_DISPLAY_FRAME:
3759 u4_api_ret = ih264d_set_display_frame(dec_hdl, (void *)pv_api_ip,
3760 (void *)pv_api_op);
3761
3762 break;
3763
3764 case IVD_CMD_REL_DISPLAY_FRAME:
3765 u4_api_ret = ih264d_rel_display_frame(dec_hdl, (void *)pv_api_ip,
3766 (void *)pv_api_op);
3767 break;
3768
3769 case IVD_CMD_VIDEO_CTL:
3770 u4_api_ret = ih264d_ctl(dec_hdl, (void *)pv_api_ip,
3771 (void *)pv_api_op);
3772 break;
3773 default:
3774 u4_api_ret = IV_FAIL;
3775 break;
3776 }
3777
3778 return u4_api_ret;
3779 }
3780