1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20 /*****************************************************************************/
21 /* */
22 /* File Name : decoder_api_main.c */
23 /* */
24 /* Description : Functions which recieve the API call from user */
25 /* */
26 /* List of Functions : <List the functions defined in this file> */
27 /* */
28 /* Issues / Problems : None */
29 /* */
30 /* Revision History : */
31 /* */
32 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
33 /* 30 05 2007 Rajneesh Creation */
34 /* */
35 /*****************************************************************************/
36
37 /*****************************************************************************/
38 /* File Includes */
39 /*****************************************************************************/
40
41 /* System include files */
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <stddef.h>
45 #include <string.h>
46
47 /* User include files */
48 #include "iv_datatypedef.h"
49 #include "iv.h"
50 #include "ivd.h"
51 #include "ithread.h"
52
53 #include "impeg2_job_queue.h"
54 #include "impeg2_macros.h"
55 #include "impeg2_buf_mgr.h"
56 #include "impeg2_disp_mgr.h"
57 #include "impeg2_defs.h"
58 #include "impeg2_platform_macros.h"
59 #include "impeg2_inter_pred.h"
60 #include "impeg2_idct.h"
61 #include "impeg2_format_conv.h"
62 #include "impeg2_mem_func.h"
63
64 #include "impeg2d.h"
65 #include "impeg2d_api.h"
66 #include "impeg2d_bitstream.h"
67 #include "impeg2d_debug.h"
68 #include "impeg2d_structs.h"
69 #include "impeg2d_mc.h"
70 #include "impeg2d_pic_proc.h"
71 #include "impeg2d_deinterlace.h"
72
73 #define NUM_FRAMES_LIMIT_ENABLED 0
74
75 #ifdef LOGO_EN
76 #include "impeg2_ittiam_logo.h"
77 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht) impeg2_insert_logo(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht);
78 #else
79 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht)
80 #endif
81
82 #if NUM_FRAMES_LIMIT_ENABLED
83 #define NUM_FRAMES_LIMIT 10000
84 #else
85 #define NUM_FRAMES_LIMIT 0x7FFFFFFF
86 #endif
87
88 #define CODEC_NAME "MPEG2VDEC"
89 #define CODEC_RELEASE_TYPE "eval"
90 #define CODEC_RELEASE_VER "01.00"
91 #define CODEC_VENDOR "ITTIAM"
92
93 #ifdef __ANDROID__
94 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
95 strcpy(version_string,"@(#)Id:"); \
96 strcat(version_string,codec_name); \
97 strcat(version_string,"_"); \
98 strcat(version_string,codec_release_type); \
99 strcat(version_string," Ver:"); \
100 strcat(version_string,codec_release_ver); \
101 strcat(version_string," Released by "); \
102 strcat(version_string,codec_vendor);
103 #else
104 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
105 strcpy(version_string,"@(#)Id:"); \
106 strcat(version_string,codec_name); \
107 strcat(version_string,"_"); \
108 strcat(version_string,codec_release_type); \
109 strcat(version_string," Ver:"); \
110 strcat(version_string,codec_release_ver); \
111 strcat(version_string," Released by "); \
112 strcat(version_string,codec_vendor); \
113 strcat(version_string," Build: "); \
114 strcat(version_string,__DATE__); \
115 strcat(version_string," @ "); \
116 strcat(version_string,__TIME__);
117 #endif
118
119
120 #define MIN_OUT_BUFS_420 3
121 #define MIN_OUT_BUFS_422ILE 1
122 #define MIN_OUT_BUFS_RGB565 1
123 #define MIN_OUT_BUFS_420SP 2
124
125
126 void impeg2d_init_arch(void *pv_codec);
127 void impeg2d_init_function_ptr(void *pv_codec);
128 UWORD32 impeg2d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht, WORD32 u1_chroma_format,UWORD32 *p_buf_size);
129
130 /*****************************************************************************/
131 /* */
132 /* Function Name : impeg2d_api_rel_display_frame */
133 /* */
134 /* Description : Release displ buffers that will be shared between decoder */
135 /* and application */
136 /* Inputs : Error message */
137 /* Globals : None */
138 /* Processing : Just prints error message to console */
139 /* Outputs : Error mesage to the console */
140 /* Returns : None */
141 /* */
142 /* Issues : <List any issues or problems with this function> */
143 /* */
144 /* Revision History: */
145 /* */
146 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
147 /* 27 05 2006 Sankar Creation */
148 /* */
149 /*****************************************************************************/
impeg2d_api_rel_display_frame(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)150 IV_API_CALL_STATUS_T impeg2d_api_rel_display_frame(iv_obj_t *ps_dechdl,
151 void *pv_api_ip,
152 void *pv_api_op)
153 {
154
155 ivd_rel_display_frame_ip_t *dec_rel_disp_ip;
156 ivd_rel_display_frame_op_t *dec_rel_disp_op;
157
158 dec_state_t *ps_dec_state;
159 dec_state_multi_core_t *ps_dec_state_multi_core;
160
161
162 dec_rel_disp_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
163 dec_rel_disp_op = (ivd_rel_display_frame_op_t *)pv_api_op;
164
165 dec_rel_disp_op->u4_error_code = 0;
166 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
167 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
168
169
170 /* If not in shared disp buf mode, return */
171 if(0 == ps_dec_state->u4_share_disp_buf)
172 return IV_SUCCESS;
173
174 if(NULL == ps_dec_state->pv_pic_buf_mg)
175 return IV_SUCCESS;
176
177
178 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, dec_rel_disp_ip->u4_disp_buf_id, BUF_MGR_DISP);
179
180 return IV_SUCCESS;
181 }
182
183 /*****************************************************************************/
184 /* */
185 /* Function Name : impeg2d_api_set_display_frame */
186 /* */
187 /* Description : Sets display buffers that will be shared between decoder */
188 /* and application */
189 /* Inputs : Error message */
190 /* Globals : None */
191 /* Processing : Just prints error message to console */
192 /* Outputs : Error mesage to the console */
193 /* Returns : None */
194 /* */
195 /* Issues : <List any issues or problems with this function> */
196 /* */
197 /* Revision History: */
198 /* */
199 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
200 /* 27 05 2006 Sankar Creation */
201 /* */
202 /*****************************************************************************/
impeg2d_api_set_display_frame(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)203 IV_API_CALL_STATUS_T impeg2d_api_set_display_frame(iv_obj_t *ps_dechdl,
204 void *pv_api_ip,
205 void *pv_api_op)
206 {
207
208 ivd_set_display_frame_ip_t *dec_disp_ip;
209 ivd_set_display_frame_op_t *dec_disp_op;
210
211 UWORD32 i;
212 dec_state_t *ps_dec_state;
213 dec_state_multi_core_t *ps_dec_state_multi_core;
214 UWORD32 u4_num_disp_bufs;
215 UWORD32 u4_disp_buf_size[3];
216 UWORD32 num_bufs;
217
218
219 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
220 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
221 dec_disp_op->u4_error_code = 0;
222
223 u4_num_disp_bufs = dec_disp_ip->num_disp_bufs;
224 if(u4_num_disp_bufs > BUF_MGR_MAX_CNT)
225 u4_num_disp_bufs = BUF_MGR_MAX_CNT;
226
227 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
228 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
229
230 num_bufs = dec_disp_ip->s_disp_buffer[0].u4_num_bufs;
231
232 if(ps_dec_state->u4_share_disp_buf)
233 {
234 pic_buf_t *ps_pic_buf;
235 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base;
236
237 /* Get the sizes of the first buffer structure. Compare this with the
238 * rest to make sure all the buffers are of the same size.
239 */
240 u4_disp_buf_size[0] =
241 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[0];
242 u4_disp_buf_size[1] =
243 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[1];
244 u4_disp_buf_size[2] =
245 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[2];
246 for(i = 0; i < u4_num_disp_bufs; i++)
247 {
248 /* Verify all buffer structures have the same sized buffers as the
249 * first buffer structure*/
250 if ((dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]
251 != u4_disp_buf_size[0])
252 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]
253 != u4_disp_buf_size[1])
254 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]
255 != u4_disp_buf_size[2]))
256 {
257 return IV_FAIL;
258 }
259 /* Verify all buffer structures have the same number of
260 * buffers (e.g. y, u, v) */
261 if (dec_disp_ip->s_disp_buffer[i].u4_num_bufs != num_bufs)
262 {
263 return IV_FAIL;
264 }
265
266 ps_pic_buf->pu1_y = dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
267 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat)
268 {
269 ps_pic_buf->pu1_u = dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
270 ps_pic_buf->pu1_v = dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
271 }
272 else
273 {
274 ps_pic_buf->pu1_u = ps_dec_state->pu1_chroma_ref_buf[i];
275 ps_pic_buf->pu1_v = ps_dec_state->pu1_chroma_ref_buf[i] +
276 ((ps_dec_state->u2_create_max_width * ps_dec_state->u2_create_max_height) >> 2);
277 }
278
279 ps_pic_buf->i4_buf_id = i;
280
281 ps_pic_buf->u1_used_as_ref = 0;
282
283 ps_pic_buf->u4_ts = 0;
284
285 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i);
286 impeg2_buf_mgr_set_status(ps_dec_state->pv_pic_buf_mg, i, BUF_MGR_DISP);
287 ps_pic_buf++;
288
289 }
290 }
291 memcpy(&(ps_dec_state->as_disp_buffers[0]),
292 &(dec_disp_ip->s_disp_buffer),
293 u4_num_disp_bufs * sizeof(ivd_out_bufdesc_t));
294
295 return IV_SUCCESS;
296
297 }
298
impeg2d_api_set_num_cores(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)299 IV_API_CALL_STATUS_T impeg2d_api_set_num_cores(iv_obj_t *ps_dechdl,
300 void *pv_api_ip,
301 void *pv_api_op)
302 {
303 impeg2d_ctl_set_num_cores_ip_t *ps_ip;
304 impeg2d_ctl_set_num_cores_op_t *ps_op;
305 dec_state_t *ps_dec_state;
306 dec_state_multi_core_t *ps_dec_state_multi_core;
307
308 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip;
309 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op;
310
311 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
312 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
313
314 if(ps_ip->u4_num_cores > 0)
315 {
316
317
318 WORD32 i;
319 for(i = 0; i < MAX_THREADS; i++)
320 ps_dec_state_multi_core->ps_dec_state[i]->i4_num_cores = ps_ip->u4_num_cores;
321 }
322 else
323 {
324 ps_dec_state->i4_num_cores = 1;
325 }
326 ps_op->u4_error_code = IV_SUCCESS;
327
328 return IV_SUCCESS;
329 }
330
impeg2d_api_get_seq_info(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)331 IV_API_CALL_STATUS_T impeg2d_api_get_seq_info(iv_obj_t *ps_dechdl,
332 void *pv_api_ip,
333 void *pv_api_op)
334 {
335 impeg2d_ctl_get_seq_info_ip_t *ps_ip;
336 impeg2d_ctl_get_seq_info_op_t *ps_op;
337 dec_state_t *ps_codec;
338 dec_state_multi_core_t *ps_dec_state_multi_core;
339
340 ps_ip = (impeg2d_ctl_get_seq_info_ip_t *)pv_api_ip;
341 ps_op = (impeg2d_ctl_get_seq_info_op_t *)pv_api_op;
342
343 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
344 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
345 UNUSED(ps_ip);
346 if(ps_codec->u2_header_done == 1)
347 {
348 ps_op->u1_aspect_ratio_information = ps_codec->u2_aspect_ratio_info;
349 ps_op->u1_frame_rate_code = ps_codec->u2_frame_rate_code;
350 ps_op->u1_frame_rate_extension_n = ps_codec->u2_frame_rate_extension_n;
351 ps_op->u1_frame_rate_extension_d = ps_codec->u2_frame_rate_extension_d;
352 if(ps_codec->u1_seq_disp_extn_present == 1)
353 {
354 ps_op->u1_video_format = ps_codec->u1_video_format;
355 ps_op->u1_colour_primaries = ps_codec->u1_colour_primaries;
356 ps_op->u1_transfer_characteristics = ps_codec->u1_transfer_characteristics;
357 ps_op->u1_matrix_coefficients = ps_codec->u1_matrix_coefficients;
358 ps_op->u2_display_horizontal_size = ps_codec->u2_display_horizontal_size;
359 ps_op->u2_display_vertical_size = ps_codec->u2_display_vertical_size;
360 }
361 else
362 {
363 ps_op->u1_video_format = 5;
364 ps_op->u1_colour_primaries = 2;
365 ps_op->u1_transfer_characteristics = 2;
366 ps_op->u1_matrix_coefficients = 2;
367 ps_op->u2_display_horizontal_size = ps_codec->u2_horizontal_size;
368 ps_op->u2_display_vertical_size = ps_codec->u2_vertical_size;
369 }
370 ps_op->u4_error_code = IV_SUCCESS;
371 return IV_SUCCESS;
372 }
373 else
374 {
375 ps_op->u4_error_code = IV_FAIL;
376 return IV_FAIL;
377 }
378 }
379
380 /**
381 *******************************************************************************
382 *
383 * @brief
384 * Sets Processor type
385 *
386 * @par Description:
387 * Sets Processor type
388 *
389 * @param[in] ps_codec_obj
390 * Pointer to codec object at API level
391 *
392 * @param[in] pv_api_ip
393 * Pointer to input argument structure
394 *
395 * @param[out] pv_api_op
396 * Pointer to output argument structure
397 *
398 * @returns Status
399 *
400 * @remarks
401 *
402 *
403 *******************************************************************************
404 */
405
impeg2d_set_processor(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)406 IV_API_CALL_STATUS_T impeg2d_set_processor(iv_obj_t *ps_codec_obj,
407 void *pv_api_ip,
408 void *pv_api_op)
409 {
410 impeg2d_ctl_set_processor_ip_t *ps_ip;
411 impeg2d_ctl_set_processor_op_t *ps_op;
412 dec_state_t *ps_codec;
413 dec_state_multi_core_t *ps_dec_state_multi_core;
414
415 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle);
416 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
417
418 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip;
419 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op;
420
421 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
422 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
423
424 impeg2d_init_function_ptr(ps_codec);
425
426
427 ps_op->u4_error_code = 0;
428 return IV_SUCCESS;
429 }
430 /*****************************************************************************/
431 /* */
432 /* Function Name : impeg2d_fill_mem_rec */
433 /* */
434 /* Description : */
435 /* Inputs : */
436 /* Globals : */
437 /* Processing : */
438 /* Outputs : */
439 /* Returns : */
440 /* */
441 /* Issues : */
442 /* */
443 /* Revision History: */
444 /* */
445 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
446 /* 17 09 2007 Rajendra C Y Draft */
447 /* */
448 /*****************************************************************************/
impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t * ps_ip,impeg2d_fill_mem_rec_op_t * ps_op)449 void impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t *ps_ip,
450 impeg2d_fill_mem_rec_op_t *ps_op)
451 {
452 UWORD32 u4_i;
453
454 UWORD8 u1_no_rec = 0;
455 UWORD32 max_frm_width,max_frm_height,max_frm_size;
456 iv_mem_rec_t *ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
457 WORD32 i4_num_threads;
458 WORD32 i4_share_disp_buf, i4_chroma_format;
459 WORD32 i4_chroma_size;
460 UWORD32 u4_deinterlace;
461 UNUSED(u4_deinterlace);
462 max_frm_width = ALIGN16(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd);
463 /* In error clips with field prediction, the mv may incorrectly refer to
464 * the last MB row, causing an out of bounds read access. Allocating 8 extra
465 * rows to handle this. Adding another extra row to handle half_y prediction.
466 */
467 max_frm_height = ALIGN32(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht) + 9;
468
469 max_frm_size = (max_frm_width * max_frm_height * 3) >> 1;/* 420 P */
470
471 i4_chroma_size = max_frm_width * max_frm_height / 4;
472
473 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_share_disp_buf))
474 {
475 #ifndef LOGO_EN
476 i4_share_disp_buf = ps_ip->u4_share_disp_buf;
477 #else
478 i4_share_disp_buf = 0;
479 #endif
480 }
481 else
482 {
483 i4_share_disp_buf = 0;
484 }
485 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, e_output_format))
486 {
487 i4_chroma_format = ps_ip->e_output_format;
488 }
489 else
490 {
491 i4_chroma_format = -1;
492 }
493
494 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_deinterlace))
495 {
496 u4_deinterlace = ps_ip->u4_deinterlace;
497 }
498 else
499 {
500 u4_deinterlace = 0;
501 }
502
503
504 if( (i4_chroma_format != IV_YUV_420P) &&
505 (i4_chroma_format != IV_YUV_420SP_UV) &&
506 (i4_chroma_format != IV_YUV_420SP_VU))
507 {
508 i4_share_disp_buf = 0;
509 }
510
511 /* Disable deinterlacer in shared mode */
512 if(i4_share_disp_buf)
513 {
514 u4_deinterlace = 0;
515 }
516
517 /*************************************************************************/
518 /* Fill the memory requirement XDM Handle */
519 /*************************************************************************/
520 /* ! */
521 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
522 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
523 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t);
524
525 ps_mem_rec++;
526 u1_no_rec++;
527
528 {
529 /*************************************************************************/
530 /* Fill the memory requirement for threads context */
531 /*************************************************************************/
532 /* ! */
533 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
534 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
535 ps_mem_rec->u4_mem_size = sizeof(dec_state_multi_core_t);
536
537 ps_mem_rec++;
538 u1_no_rec++;
539 }
540
541 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
542 {
543 /*************************************************************************/
544 /* Fill the memory requirement for MPEG2 Decoder Context */
545 /*************************************************************************/
546 /* ! */
547 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
548 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
549 ps_mem_rec->u4_mem_size = sizeof(dec_state_t);
550
551 ps_mem_rec++;
552 u1_no_rec++;
553
554 /* To store thread handle */
555 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
556 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
557 ps_mem_rec->u4_mem_size = ithread_get_handle_size();
558
559 ps_mem_rec++;
560 u1_no_rec++;
561
562 /*************************************************************************/
563 /* Fill the memory requirement for Motion Compensation Buffers */
564 /*************************************************************************/
565 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
566 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_SCRATCH_MEM;
567
568 /* for mc_fw_buf.pu1_y */
569 ps_mem_rec->u4_mem_size = MB_LUMA_MEM_SIZE;
570
571 /* for mc_fw_buf.pu1_u */
572 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
573
574 /* for mc_fw_buf.pu1_v */
575 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
576
577 /* for mc_bk_buf.pu1_y */
578 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE;
579
580 /* for mc_bk_buf.pu1_u */
581 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
582
583 /* for mc_bk_buf.pu1_v */
584 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
585
586 /* for mc_buf.pu1_y */
587 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE;
588
589 /* for mc_buf.pu1_u */
590 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
591
592 /* for mc_buf.pu1_v */
593 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
594
595 ps_mem_rec++;
596 u1_no_rec++;
597
598
599 /*************************************************************************/
600 /* Fill the memory requirement Stack Context */
601 /*************************************************************************/
602 /* ! */
603 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
604 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
605 ps_mem_rec->u4_mem_size = 392;
606
607 ps_mem_rec++;
608 u1_no_rec++;
609 }
610
611
612
613 {
614 /*************************************************************************/
615 /* Fill the memory requirement for Picture Buffer Manager */
616 /*************************************************************************/
617 /* ! */
618 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
619 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
620 ps_mem_rec->u4_mem_size = sizeof(buf_mgr_t) + sizeof(pic_buf_t) * BUF_MGR_MAX_CNT;
621
622 ps_mem_rec++;
623 u1_no_rec++;
624 }
625 /*************************************************************************/
626 /* Internal Frame Buffers */
627 /*************************************************************************/
628 /* ! */
629
630 {
631 for(u4_i = 0; u4_i < NUM_INT_FRAME_BUFFERS; u4_i++)
632 {
633 /* ! */
634 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
635 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
636 if(0 == i4_share_disp_buf)
637 ps_mem_rec->u4_mem_size = max_frm_size;
638 else if(IV_YUV_420P != i4_chroma_format)
639 {
640 /* If color format is not 420P and it is shared, then allocate for chroma */
641 ps_mem_rec->u4_mem_size = i4_chroma_size * 2;
642 }
643 else
644 ps_mem_rec->u4_mem_size = 64;
645 ps_mem_rec++;
646 u1_no_rec++;
647 }
648 }
649
650 ps_mem_rec->u4_mem_alignment = 128;
651 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
652 ps_mem_rec->u4_mem_size = MAX_BITSTREAM_BUFFER_SIZE + MIN_BUFFER_BYTES_AT_EOS;
653 ps_mem_rec++;
654 u1_no_rec++;
655
656 {
657 WORD32 i4_job_queue_size;
658 WORD32 i4_num_jobs;
659
660 /* One job per row of MBs */
661 i4_num_jobs = max_frm_height >> 4;
662
663 /* One format convert/frame copy job per row of MBs for non-shared mode*/
664 i4_num_jobs += max_frm_height >> 4;
665
666
667 i4_job_queue_size = impeg2_jobq_ctxt_size();
668 i4_job_queue_size += i4_num_jobs * sizeof(job_t);
669 ps_mem_rec->u4_mem_size = i4_job_queue_size;
670 ps_mem_rec->u4_mem_alignment = 128;
671 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
672
673 ps_mem_rec++;
674 u1_no_rec++;
675
676 }
677
678 ps_mem_rec->u4_mem_alignment = 128;
679 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
680 ps_mem_rec->u4_mem_size = impeg2d_deint_ctxt_size();
681 ps_mem_rec++;
682 u1_no_rec++;
683
684 ps_mem_rec->u4_mem_alignment = 128;
685 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
686
687 if(IV_YUV_420P != i4_chroma_format)
688 ps_mem_rec->u4_mem_size = max_frm_size;
689 else
690 ps_mem_rec->u4_mem_size = 64;
691
692 ps_mem_rec++;
693 u1_no_rec++;
694
695 ps_mem_rec->u4_mem_alignment = 128;
696 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
697 ps_mem_rec->u4_mem_size = sizeof(iv_mem_rec_t) * (NUM_MEM_RECORDS);
698 ps_mem_rec++;
699 u1_no_rec++;
700
701 ps_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled = u1_no_rec;
702 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
703 }
704
705
706 /*****************************************************************************/
707 /* */
708 /* Function Name : impeg2d_api_get_version */
709 /* */
710 /* Description : */
711 /* */
712 /* Inputs : */
713 /* Globals : <Does it use any global variables?> */
714 /* Outputs : */
715 /* Returns : void */
716 /* */
717 /* Issues : none */
718 /* */
719 /* Revision History: */
720 /* */
721 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
722 /* 22 10 2008 100356 Draft */
723 /* */
724 /*****************************************************************************/
impeg2d_api_get_version(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)725 IV_API_CALL_STATUS_T impeg2d_api_get_version(iv_obj_t *ps_dechdl,
726 void *pv_api_ip,
727 void *pv_api_op)
728 {
729 char au1_version_string[512];
730
731 impeg2d_ctl_getversioninfo_ip_t *ps_ip;
732 impeg2d_ctl_getversioninfo_op_t *ps_op;
733
734 UNUSED(ps_dechdl);
735
736 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip;
737 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op;
738
739 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS;
740
741 VERSION(au1_version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
742 CODEC_VENDOR);
743
744 if((WORD32)ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size <= 0)
745 {
746 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL;
747 return (IV_FAIL);
748 }
749
750 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size
751 >= (strlen(au1_version_string) + 1))
752 {
753 memcpy(ps_ip->s_ivd_ctl_getversioninfo_ip_t.pv_version_buffer,
754 au1_version_string, (strlen(au1_version_string) + 1));
755 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS;
756 }
757 else
758 {
759 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL;
760 }
761
762 return (IV_SUCCESS);
763 }
764
765 /*****************************************************************************/
766 /* */
767 /* Function Name : impeg2d_api_get_buf_info */
768 /* */
769 /* Description : */
770 /* */
771 /* Inputs : */
772 /* Globals : <Does it use any global variables?> */
773 /* Outputs : */
774 /* Returns : void */
775 /* */
776 /* Issues : none */
777 /* */
778 /* Revision History: */
779 /* */
780 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
781 /* 22 10 2008 100356 Draft */
782 /* */
783 /*****************************************************************************/
impeg2d_api_get_buf_info(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)784 IV_API_CALL_STATUS_T impeg2d_api_get_buf_info(iv_obj_t *ps_dechdl,
785 void *pv_api_ip,
786 void *pv_api_op)
787 {
788 dec_state_t *ps_dec_state;
789 dec_state_multi_core_t *ps_dec_state_multi_core;
790 impeg2d_ctl_getbufinfo_ip_t *ps_ctl_bufinfo_ip =
791 (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip;
792 impeg2d_ctl_getbufinfo_op_t *ps_ctl_bufinfo_op =
793 (impeg2d_ctl_getbufinfo_op_t *)pv_api_op;
794 UWORD32 u4_i, u4_stride, u4_height;
795 UNUSED(ps_ctl_bufinfo_ip);
796
797 ps_dec_state_multi_core =
798 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
799 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
800
801 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs = 1;
802 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs = 1;
803
804 for(u4_i = 0; u4_i < IVD_VIDDEC_MAX_IO_BUFFERS; u4_i++)
805 {
806 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] =
807 0;
808 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[u4_i] =
809 0;
810 }
811
812 for(u4_i = 0;
813 u4_i < ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs;
814 u4_i++)
815 {
816 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] =
817 MAX_BITSTREAM_BUFFER_SIZE;
818 }
819
820 if (0 == ps_dec_state->u4_frm_buf_stride)
821 {
822 if (1 == ps_dec_state->u2_header_done)
823 {
824 u4_stride = ps_dec_state->u2_horizontal_size;
825 }
826 else
827 {
828 u4_stride = ps_dec_state->u2_create_max_width;
829 }
830 }
831 else
832 {
833 u4_stride = ps_dec_state->u4_frm_buf_stride;
834 }
835 u4_stride = ALIGN16(u4_stride);
836 u4_height = ALIGN32(ps_dec_state->u2_frame_height) + 9;
837
838 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
839 impeg2d_get_outbuf_size(
840 u4_stride,
841 u4_height,
842 ps_dec_state->i4_chromaFormat,
843 &ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0]);
844
845 if (0 == ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs)
846 {
847 //Invalid chroma format; Error code may be updated, verify in testing if needed
848 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code =
849 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
850 return IV_FAIL;
851 }
852
853 /* Adding initialization for 2 uninitialized values */
854 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs = 1;
855 if(ps_dec_state->u4_share_disp_buf)
856 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs =
857 NUM_INT_FRAME_BUFFERS;
858 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_size = MAX_FRM_SIZE;
859
860 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = IV_SUCCESS;
861
862 return (IV_SUCCESS);
863 }
864
865 /*****************************************************************************/
866 /* */
867 /* Function Name : impeg2d_api_set_flush_mode */
868 /* */
869 /* Description : */
870 /* */
871 /* Inputs : */
872 /* Globals : <Does it use any global variables?> */
873 /* Outputs : */
874 /* Returns : void */
875 /* */
876 /* Issues : none */
877 /* */
878 /* Revision History: */
879 /* */
880 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
881 /* 08 06 2009 100356 RAVI */
882 /* */
883 /*****************************************************************************/
impeg2d_api_set_flush_mode(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)884 IV_API_CALL_STATUS_T impeg2d_api_set_flush_mode(iv_obj_t *ps_dechdl,
885 void *pv_api_ip,
886 void *pv_api_op)
887 {
888 dec_state_t *ps_dec_state;
889 dec_state_multi_core_t *ps_dec_state_multi_core;
890 impeg2d_ctl_flush_op_t *ps_ctl_dec_op =
891 (impeg2d_ctl_flush_op_t*)pv_api_op;
892
893 UNUSED(pv_api_ip);
894
895 ps_dec_state_multi_core =
896 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
897 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
898
899 ps_dec_state->u1_flushfrm = 1;
900
901 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_size =
902 sizeof(impeg2d_ctl_flush_op_t);
903 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_error_code = IV_SUCCESS;
904
905 return (IV_SUCCESS);
906 }
907
908 /*****************************************************************************/
909 /* */
910 /* Function Name : impeg2d_api_set_default */
911 /* */
912 /* Description : */
913 /* */
914 /* Inputs : */
915 /* Globals : <Does it use any global variables?> */
916 /* Outputs : */
917 /* Returns : void */
918 /* */
919 /* Issues : none */
920 /* */
921 /* Revision History: */
922 /* */
923 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
924 /* 08 06 2009 100356 RAVI */
925 /* */
926 /*****************************************************************************/
impeg2d_api_set_default(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)927 IV_API_CALL_STATUS_T impeg2d_api_set_default(iv_obj_t *ps_dechdl,
928 void *pv_api_ip,
929 void *pv_api_op)
930 {
931 dec_state_t *ps_dec_state;
932 dec_state_multi_core_t *ps_dec_state_multi_core;
933 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op =
934 (impeg2d_ctl_set_config_op_t *)pv_api_op;
935
936 UNUSED(pv_api_ip);
937
938 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
939 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_size =
940 sizeof(impeg2d_ctl_set_config_op_t);
941
942 ps_dec_state_multi_core =
943 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
944 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
945
946 ps_dec_state->u1_flushfrm = 0;
947 ps_dec_state->u2_decode_header = 1;
948
949 if (1 == ps_dec_state->u2_header_done)
950 {
951 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width;
952 }
953
954 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
955
956 return (IV_SUCCESS);
957
958 }
959
960 /*****************************************************************************/
961 /* */
962 /* Function Name : impeg2d_api_reset */
963 /* */
964 /* Description : */
965 /* */
966 /* Inputs : */
967 /* Globals : <Does it use any global variables?> */
968 /* Outputs : */
969 /* Returns : void */
970 /* */
971 /* Issues : none */
972 /* */
973 /* Revision History: */
974 /* */
975 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
976 /* 08 06 2009 100356 RAVI */
977 /* */
978 /*****************************************************************************/
impeg2d_api_reset(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)979 IV_API_CALL_STATUS_T impeg2d_api_reset(iv_obj_t *ps_dechdl,
980 void *pv_api_ip,
981 void *pv_api_op)
982 {
983 dec_state_t *ps_dec_state;
984 dec_state_multi_core_t *ps_dec_state_multi_core;
985 UNUSED(pv_api_ip);
986 impeg2d_ctl_reset_op_t *s_ctl_reset_op = (impeg2d_ctl_reset_op_t *)pv_api_op;
987
988 WORD32 i4_num_threads;
989
990 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
991 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
992
993 if(ps_dec_state_multi_core != NULL)
994 {
995 impeg2_buf_mgr_reset(ps_dec_state->pv_pic_buf_mg);
996 /* Display buffer manager init behaves like a reset
997 * as it doesn't need to preserve picture buffer addresses
998 * like buffer manager */
999 impeg2_disp_mgr_init(&ps_dec_state->s_disp_mgr);
1000
1001 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1002 {
1003 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads];
1004
1005
1006 /* --------------------------------------------------------------------- */
1007 /* Initializations */
1008
1009 ps_dec_state->u2_header_done = 0; /* Header decoding not done */
1010 ps_dec_state->u4_frm_buf_stride = 0;
1011 ps_dec_state->i4_pic_count = 0;
1012 ps_dec_state->u2_is_mpeg2 = 0;
1013 ps_dec_state->aps_ref_pics[0] = NULL;
1014 ps_dec_state->aps_ref_pics[1] = NULL;
1015 ps_dec_state->ps_deint_pic = NULL;
1016 }
1017 }
1018 else
1019 {
1020 s_ctl_reset_op->s_ivd_ctl_reset_op_t.u4_error_code =
1021 IMPEG2D_INIT_NOT_DONE;
1022 }
1023
1024 return(IV_SUCCESS);
1025 }
1026
1027 /*****************************************************************************/
1028 /* */
1029 /* Function Name : impeg2d_api_set_params */
1030 /* */
1031 /* Description : */
1032 /* */
1033 /* Inputs : */
1034 /* Globals : <Does it use any global variables?> */
1035 /* Outputs : */
1036 /* Returns : void */
1037 /* */
1038 /* Issues : none */
1039 /* */
1040 /* Revision History: */
1041 /* */
1042 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1043 /* 08 06 2009 100356 RAVI */
1044 /* */
1045 /*****************************************************************************/
impeg2d_api_set_params(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1046 IV_API_CALL_STATUS_T impeg2d_api_set_params(iv_obj_t *ps_dechdl,void *pv_api_ip,void *pv_api_op)
1047 {
1048 dec_state_t *ps_dec_state;
1049 dec_state_multi_core_t *ps_dec_state_multi_core;
1050 impeg2d_ctl_set_config_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip;
1051 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
1052
1053 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1054 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1055
1056 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_HEADER) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_FRAME))
1057 {
1058 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1059 return(IV_FAIL);
1060 }
1061
1062 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DISPLAY_FRAME_OUT) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DECODE_FRAME_OUT))
1063 {
1064 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1065 return(IV_FAIL);
1066 }
1067
1068 if( (WORD32) ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_skip_mode < IVD_SKIP_NONE)
1069 {
1070 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1071 return(IV_FAIL);
1072 }
1073
1074 if(ps_dec_state->u2_header_done == 1)
1075 {
1076 if(((WORD32)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < 0) ||
1077 ((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < ps_dec_state->u2_frame_width)))
1078 {
1079 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1080 return(IV_FAIL);
1081 }
1082
1083 }
1084
1085
1086 ps_dec_state->u2_decode_header = (UWORD8)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode;
1087
1088 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0)
1089 {
1090 ps_dec_state->u4_frm_buf_stride = ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd;
1091 }
1092 else
1093 {
1094
1095 if(ps_dec_state->u2_header_done == 1)
1096 {
1097 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width;
1098 }
1099 else
1100 {
1101 ps_dec_state->u4_frm_buf_stride = 0;
1102 }
1103 }
1104
1105
1106 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode == IVD_DECODE_FRAME)
1107 {
1108 ps_dec_state->u1_flushfrm = 0;
1109 }
1110
1111
1112 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
1113 return(IV_SUCCESS);
1114
1115 }
1116
1117 /*****************************************************************************/
1118 /* */
1119 /* Function Name : impeg2d_api_get_status */
1120 /* */
1121 /* Description : */
1122 /* */
1123 /* Inputs : */
1124 /* Globals : <Does it use any global variables?> */
1125 /* Outputs : */
1126 /* Returns : void */
1127 /* */
1128 /* Issues : none */
1129 /* */
1130 /* Revision History: */
1131 /* */
1132 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1133 /* 08 06 2009 100356 RAVI */
1134 /* */
1135 /*****************************************************************************/
impeg2d_api_get_status(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1136 IV_API_CALL_STATUS_T impeg2d_api_get_status(iv_obj_t *ps_dechdl,
1137 void *pv_api_ip,
1138 void *pv_api_op)
1139 {
1140 dec_state_t *ps_dec_state;
1141 dec_state_multi_core_t *ps_dec_state_multi_core;
1142 UWORD32 u4_i,u4_stride,u4_height;
1143 impeg2d_ctl_getstatus_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip;
1144 impeg2d_ctl_getstatus_op_t *ps_ctl_dec_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op;
1145 UNUSED(ps_ctl_dec_ip);
1146
1147 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1148 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1149
1150 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_size = sizeof(impeg2d_ctl_getstatus_op_t);
1151 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_num_disp_bufs = 1;
1152 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_ht = ps_dec_state->u2_frame_height;
1153 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_wd = ps_dec_state->u2_frame_width;
1154 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_frame_rate = ps_dec_state->u2_framePeriod;
1155
1156
1157 if(ps_dec_state->u2_progressive_sequence == 1)
1158 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_PROGRESSIVE ;
1159 else
1160 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_INTERLACED;
1161
1162
1163 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_output_chroma_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
1164 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs = 1;
1165 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = 1;
1166
1167
1168 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
1169 {
1170 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_420;
1171 }
1172 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1173 {
1174 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
1175 }
1176 else if(ps_dec_state->i4_chromaFormat == IV_RGB_565)
1177 {
1178 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
1179 }
1180 else
1181 {
1182 //Invalid chroma format; Error code may be updated, verify in testing if needed
1183 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
1184 return IV_FAIL;
1185 }
1186
1187 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS));
1188 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS));
1189
1190 for(u4_i = 0; u4_i < ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs; u4_i++)
1191 {
1192 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[u4_i] = MAX_BITSTREAM_BUFFER_SIZE;
1193 }
1194
1195 u4_stride = ps_dec_state->u4_frm_buf_stride;
1196 u4_height = ((ps_dec_state->u2_frame_height + 15) >> 4) << 4;
1197
1198 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
1199 {
1200 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height);
1201 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>2 ;
1202 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = (u4_stride * u4_height)>>2;
1203 }
1204 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV) || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU))
1205 {
1206 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height);
1207 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>1 ;
1208 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0;
1209 }
1210 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1211 {
1212 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height)*2;
1213 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0;
1214 }
1215
1216 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IV_SUCCESS;
1217
1218 return(IV_SUCCESS);
1219
1220 }
1221
1222 /**
1223 *******************************************************************************
1224 *
1225 * @brief
1226 * Gets frame dimensions/offsets
1227 *
1228 * @par Description:
1229 * Gets frame buffer chararacteristics such a x & y offsets display and
1230 * buffer dimensions
1231 *
1232 * @param[in] ps_codec_obj
1233 * Pointer to codec object at API level
1234 *
1235 * @param[in] pv_api_ip
1236 * Pointer to input argument structure
1237 *
1238 * @param[out] pv_api_op
1239 * Pointer to output argument structure
1240 *
1241 * @returns Status
1242 *
1243 * @remarks
1244 *
1245 *
1246 *******************************************************************************
1247 */
impeg2d_get_frame_dimensions(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)1248 IV_API_CALL_STATUS_T impeg2d_get_frame_dimensions(iv_obj_t *ps_codec_obj,
1249 void *pv_api_ip,
1250 void *pv_api_op)
1251 {
1252 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip;
1253 impeg2d_ctl_get_frame_dimensions_op_t *ps_op;
1254 WORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
1255 dec_state_t *ps_codec;
1256 dec_state_multi_core_t *ps_dec_state_multi_core;
1257
1258 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle);
1259 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
1260
1261
1262 ps_ip = (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
1263 ps_op = (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op;
1264 UNUSED(ps_ip);
1265 if(ps_codec->u2_header_done)
1266 {
1267 disp_wd = ps_codec->u2_horizontal_size;
1268 disp_ht = ps_codec->u2_vertical_size;
1269
1270 if(0 == ps_codec->u4_share_disp_buf)
1271 {
1272 buffer_wd = disp_wd;
1273 buffer_ht = disp_ht;
1274 }
1275 else
1276 {
1277 buffer_wd = ps_codec->u2_frame_width;
1278 buffer_ht = ps_codec->u2_frame_height;
1279 }
1280 }
1281 else
1282 {
1283
1284 disp_wd = ps_codec->u2_create_max_width;
1285 disp_ht = ps_codec->u2_create_max_height;
1286
1287 if(0 == ps_codec->u4_share_disp_buf)
1288 {
1289 buffer_wd = disp_wd;
1290 buffer_ht = disp_ht;
1291 }
1292 else
1293 {
1294 buffer_wd = ALIGN16(disp_wd);
1295 buffer_ht = ALIGN16(disp_ht);
1296
1297 }
1298 }
1299 if(ps_codec->u2_frame_width > buffer_wd)
1300 buffer_wd = ps_codec->u2_frame_width;
1301
1302 x_offset = 0;
1303 y_offset = 0;
1304
1305
1306 ps_op->u4_disp_wd[0] = disp_wd;
1307 ps_op->u4_disp_ht[0] = disp_ht;
1308 ps_op->u4_buffer_wd[0] = buffer_wd;
1309 ps_op->u4_buffer_ht[0] = buffer_ht;
1310 ps_op->u4_x_offset[0] = x_offset;
1311 ps_op->u4_y_offset[0] = y_offset;
1312
1313 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
1314 >> 1);
1315 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
1316 >> 1);
1317 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
1318 >> 1);
1319 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
1320 >> 1);
1321 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] = (ps_op->u4_x_offset[0]
1322 >> 1);
1323 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] = (ps_op->u4_y_offset[0]
1324 >> 1);
1325
1326 if((ps_codec->i4_chromaFormat == IV_YUV_420SP_UV)
1327 || (ps_codec->i4_chromaFormat == IV_YUV_420SP_VU))
1328 {
1329 ps_op->u4_disp_wd[2] = 0;
1330 ps_op->u4_disp_ht[2] = 0;
1331 ps_op->u4_buffer_wd[2] = 0;
1332 ps_op->u4_buffer_ht[2] = 0;
1333 ps_op->u4_x_offset[2] = 0;
1334 ps_op->u4_y_offset[2] = 0;
1335
1336 ps_op->u4_disp_wd[1] <<= 1;
1337 ps_op->u4_buffer_wd[1] <<= 1;
1338 ps_op->u4_x_offset[1] <<= 1;
1339 }
1340
1341 return IV_SUCCESS;
1342
1343 }
1344
impeg2d_api_function(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1345 IV_API_CALL_STATUS_T impeg2d_api_function (iv_obj_t *ps_dechdl, void *pv_api_ip,void *pv_api_op)
1346 {
1347 WORD32 i4_cmd;
1348 IV_API_CALL_STATUS_T u4_error_code;
1349 UWORD32 *pu4_api_ip;
1350
1351 u4_error_code = impeg2d_api_check_struct_sanity(ps_dechdl,pv_api_ip,pv_api_op);
1352 if(IV_SUCCESS != u4_error_code)
1353 {
1354 return u4_error_code;
1355 }
1356
1357
1358 pu4_api_ip = (UWORD32 *)pv_api_ip;
1359 i4_cmd = *(pu4_api_ip + 1);
1360
1361 switch(i4_cmd)
1362 {
1363
1364 case IV_CMD_GET_NUM_MEM_REC:
1365 u4_error_code = impeg2d_api_num_mem_rec((void *)pv_api_ip,(void *)pv_api_op);
1366 break;
1367
1368 case IV_CMD_FILL_NUM_MEM_REC:
1369 u4_error_code = impeg2d_api_fill_mem_rec((void *)pv_api_ip,(void *)pv_api_op);
1370 break;
1371
1372 case IV_CMD_INIT:
1373 u4_error_code = impeg2d_api_init(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1374 break;
1375
1376 case IVD_CMD_SET_DISPLAY_FRAME:
1377 u4_error_code = impeg2d_api_set_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1378 break;
1379
1380 case IVD_CMD_REL_DISPLAY_FRAME:
1381 u4_error_code = impeg2d_api_rel_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1382 break;
1383
1384 case IVD_CMD_VIDEO_DECODE:
1385 u4_error_code = impeg2d_api_entity(ps_dechdl, (void *)pv_api_ip,(void *)pv_api_op);
1386 break;
1387
1388 case IV_CMD_RETRIEVE_MEMREC:
1389 u4_error_code = impeg2d_api_retrieve_mem_rec(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1390 break;
1391
1392 case IVD_CMD_VIDEO_CTL:
1393 u4_error_code = impeg2d_api_ctl(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1394 break;
1395
1396 default:
1397 break;
1398 }
1399
1400 return(u4_error_code);
1401
1402 }
1403
1404 /*****************************************************************************/
1405 /* */
1406 /* Function Name : impeg2d_api_num_mem_rec */
1407 /* */
1408 /* Description : The function get the number mem records library needs */
1409 /* Inputs : Error message */
1410 /* Globals : None */
1411 /* Processing : Just prints error message to console */
1412 /* Outputs : Error mesage to the console */
1413 /* Returns : None */
1414 /* */
1415 /* Issues : <List any issues or problems with this function> */
1416 /* */
1417 /* Revision History: */
1418 /* */
1419 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1420 /* 23 09 2010 Hamsalekha Creation */
1421 /* */
1422 /*****************************************************************************/
1423
1424
impeg2d_api_num_mem_rec(void * pv_api_ip,void * pv_api_op)1425 IV_API_CALL_STATUS_T impeg2d_api_num_mem_rec(void *pv_api_ip,void *pv_api_op)
1426 {
1427 /* To Query No of Memory Records */
1428 impeg2d_num_mem_rec_ip_t *ps_query_mem_rec_ip;
1429 impeg2d_num_mem_rec_op_t *ps_query_mem_rec_op;
1430
1431 ps_query_mem_rec_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip;
1432 ps_query_mem_rec_op = (impeg2d_num_mem_rec_op_t *)pv_api_op;
1433
1434 UNUSED(ps_query_mem_rec_ip);
1435 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_size = sizeof(impeg2d_num_mem_rec_op_t);
1436
1437 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_num_mem_rec = (UWORD32)NUM_MEM_RECORDS;
1438
1439 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_error_code = IV_SUCCESS;
1440
1441
1442 return(IV_SUCCESS);
1443
1444 }
1445
1446
1447 /*****************************************************************************/
1448 /* */
1449 /* Function Name : impeg2d_api_fill_mem_rec */
1450 /* */
1451 /* Description : Thsi functions fills details of each mem record lib needs*/
1452 /* Inputs : Error message */
1453 /* Globals : None */
1454 /* Processing : Just prints error message to console */
1455 /* Outputs : Error mesage to the console */
1456 /* Returns : None */
1457 /* */
1458 /* Issues : <List any issues or problems with this function> */
1459 /* */
1460 /* Revision History: */
1461 /* */
1462 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1463 /* 23 09 2010 Hamsalekha Creation */
1464 /* */
1465 /*****************************************************************************/
1466
1467
impeg2d_api_fill_mem_rec(void * pv_api_ip,void * pv_api_op)1468 IV_API_CALL_STATUS_T impeg2d_api_fill_mem_rec(void *pv_api_ip,void *pv_api_op)
1469 {
1470
1471 impeg2d_fill_mem_rec_ip_t *ps_mem_q_ip;
1472 impeg2d_fill_mem_rec_op_t *ps_mem_q_op;
1473
1474
1475 ps_mem_q_ip = pv_api_ip;
1476 ps_mem_q_op = pv_api_op;
1477
1478
1479 impeg2d_fill_mem_rec((impeg2d_fill_mem_rec_ip_t *)ps_mem_q_ip,
1480 (impeg2d_fill_mem_rec_op_t *)ps_mem_q_op);
1481
1482
1483 return(IV_SUCCESS);
1484
1485 }
1486
impeg2d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht,WORD32 u1_chroma_format,UWORD32 * p_buf_size)1487 UWORD32 impeg2d_get_outbuf_size(WORD32 pic_wd,UWORD32 pic_ht, WORD32 u1_chroma_format,UWORD32 *p_buf_size)
1488 {
1489 UWORD32 u4_min_num_out_bufs = 0;
1490 if(u1_chroma_format == IV_YUV_420P)
1491 u4_min_num_out_bufs = MIN_OUT_BUFS_420;
1492 else if(u1_chroma_format == IV_YUV_422ILE)
1493 u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
1494 else if(u1_chroma_format == IV_RGB_565)
1495 u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
1496 else if((u1_chroma_format == IV_YUV_420SP_UV)
1497 || (u1_chroma_format == IV_YUV_420SP_VU))
1498 u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
1499
1500 if(u1_chroma_format == IV_YUV_420P)
1501 {
1502 p_buf_size[0] = (pic_wd * pic_ht);
1503 p_buf_size[1] = (pic_wd * pic_ht)
1504 >> 2;
1505 p_buf_size[2] = (pic_wd * pic_ht)
1506 >> 2;
1507 }
1508 else if(u1_chroma_format == IV_YUV_422ILE)
1509 {
1510 p_buf_size[0] = (pic_wd * pic_ht)
1511 * 2;
1512 p_buf_size[1] =
1513 p_buf_size[2] = 0;
1514 }
1515 else if(u1_chroma_format == IV_RGB_565)
1516 {
1517 p_buf_size[0] = (pic_wd * pic_ht)
1518 * 2;
1519 p_buf_size[1] =
1520 p_buf_size[2] = 0;
1521 }
1522 else if((u1_chroma_format == IV_YUV_420SP_UV)
1523 || (u1_chroma_format == IV_YUV_420SP_VU))
1524 {
1525 p_buf_size[0] = (pic_wd * pic_ht);
1526 p_buf_size[1] = (pic_wd * pic_ht)
1527 >> 1;
1528 p_buf_size[2] = 0;
1529 }
1530
1531 return u4_min_num_out_bufs;
1532 }
1533
check_app_out_buf_size(dec_state_t * ps_dec)1534 WORD32 check_app_out_buf_size(dec_state_t *ps_dec)
1535 {
1536 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
1537 UWORD32 u4_min_num_out_bufs, i;
1538 UWORD32 pic_wd, pic_ht;
1539
1540 pic_wd = ps_dec->u2_horizontal_size;
1541 pic_ht = ps_dec->u2_vertical_size;
1542
1543 if(ps_dec->u4_frm_buf_stride > pic_wd)
1544 pic_wd = ps_dec->u4_frm_buf_stride;
1545
1546 u4_min_num_out_bufs = impeg2d_get_outbuf_size(pic_wd, pic_ht, ps_dec->i4_chromaFormat, &au4_min_out_buf_size[0]);
1547
1548 if (0 == ps_dec->u4_share_disp_buf)
1549 {
1550 if(ps_dec->ps_out_buf->u4_num_bufs < u4_min_num_out_bufs)
1551 {
1552 return IV_FAIL;
1553 }
1554
1555 for (i = 0 ; i < u4_min_num_out_bufs; i++)
1556 {
1557 if(ps_dec->ps_out_buf->u4_min_out_buf_size[i] < au4_min_out_buf_size[i])
1558 return (IV_FAIL);
1559 }
1560 }
1561 else
1562 {
1563 if(ps_dec->as_disp_buffers[0].u4_num_bufs < u4_min_num_out_bufs)
1564 return IV_FAIL;
1565
1566 for (i = 0 ; i < u4_min_num_out_bufs; i++)
1567 {
1568 /* We need to check only with the disp_buffer[0], because we have
1569 * already ensured that all the buffers are of the same size in
1570 * impeg2d_api_set_display_frame.
1571 */
1572 if(ps_dec->as_disp_buffers[0].u4_min_out_buf_size[i] <
1573 au4_min_out_buf_size[i])
1574 return (IV_FAIL);
1575 }
1576 }
1577
1578 return(IV_SUCCESS);
1579 }
1580
1581
1582
1583 /*****************************************************************************/
1584 /* */
1585 /* Function Name : impeg2d_api_init */
1586 /* */
1587 /* Description : */
1588 /* Inputs : */
1589 /* Globals : */
1590 /* Processing : */
1591 /* Outputs : */
1592 /* Returns : */
1593 /* */
1594 /* Issues : */
1595 /* */
1596 /* Revision History: */
1597 /* */
1598 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1599 /* 17 09 2007 Rajendra C Y Draft */
1600 /* */
1601 /*****************************************************************************/
impeg2d_api_init(iv_obj_t * ps_dechdl,void * ps_ip,void * ps_op)1602 IV_API_CALL_STATUS_T impeg2d_api_init(iv_obj_t *ps_dechdl,
1603 void *ps_ip,
1604 void *ps_op)
1605 {
1606 UWORD32 i;
1607
1608 void *pv;
1609 UWORD32 u4_size;
1610
1611 dec_state_t *ps_dec_state;
1612 dec_state_multi_core_t *ps_dec_state_multi_core;
1613 UWORD32 u4_num_mem_rec;
1614 iv_mem_rec_t *ps_mem_rec ;
1615 iv_mem_rec_t *ps_frm_buf;
1616 iv_obj_t *ps_dec_handle;
1617 WORD32 i4_max_wd, i4_max_ht;
1618
1619 impeg2d_init_ip_t *ps_dec_init_ip;
1620 impeg2d_init_op_t *ps_dec_init_op;
1621 WORD32 i4_num_threads;
1622 UWORD32 u4_share_disp_buf, u4_chroma_format;
1623 UWORD32 u4_deinterlace;
1624
1625 ps_dec_init_ip = (impeg2d_init_ip_t *)ps_ip;
1626 ps_dec_init_op = (impeg2d_init_op_t *)ps_op;
1627
1628 i4_max_wd = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd);
1629 i4_max_ht = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht);
1630
1631 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_share_disp_buf))
1632 {
1633 #ifndef LOGO_EN
1634 u4_share_disp_buf = ps_dec_init_ip->u4_share_disp_buf;
1635 #else
1636 u4_share_disp_buf = 0;
1637 #endif
1638 }
1639 else
1640 {
1641 u4_share_disp_buf = 0;
1642 }
1643
1644 u4_chroma_format = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format;
1645
1646 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_deinterlace))
1647 {
1648 u4_deinterlace = ps_dec_init_ip->u4_deinterlace;
1649 }
1650 else
1651 {
1652 u4_deinterlace = 0;
1653 }
1654
1655 if( (u4_chroma_format != IV_YUV_420P) &&
1656 (u4_chroma_format != IV_YUV_420SP_UV) &&
1657 (u4_chroma_format != IV_YUV_420SP_VU))
1658 {
1659 u4_share_disp_buf = 0;
1660 }
1661
1662 /* Disable deinterlacer in shared mode */
1663 if(u4_share_disp_buf)
1664 {
1665 u4_deinterlace = 0;
1666 }
1667
1668 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1669 ps_mem_rec ++;
1670
1671
1672 ps_dec_init_op->s_ivd_init_op_t.u4_size = sizeof(impeg2d_init_op_t);
1673
1674
1675 /* Except memTab[0], all other memTabs are initialized to zero */
1676 for(i = 1; i < ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
1677 {
1678 memset(ps_mem_rec->pv_base,0,ps_mem_rec->u4_mem_size);
1679 ps_mem_rec++;
1680 }
1681
1682 /* Reinitializing memTab[0] memory base address */
1683 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1684
1685
1686 /* memTab[0] is for codec Handle,redundant currently not being used */
1687 ps_dec_handle = ps_mem_rec->pv_base;
1688 u4_num_mem_rec = 1;
1689 ps_mem_rec++;
1690
1691
1692
1693
1694
1695 /* decoder handle */
1696 ps_dec_state_multi_core = ps_mem_rec->pv_base;
1697 u4_num_mem_rec++;
1698 ps_mem_rec++;
1699
1700
1701 {
1702 ps_dec_handle->pv_codec_handle = (void *)ps_dec_state_multi_core; /* Initializing codec context */
1703
1704 ps_dechdl->pv_codec_handle = (void *)ps_dec_state_multi_core;
1705 ps_dechdl->pv_fxns = (void *)impeg2d_api_function;
1706 }
1707
1708
1709 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1710 {
1711 /*************************************************************************/
1712 /* For MPEG2 Decoder Context */
1713 /*************************************************************************/
1714 ps_dec_state = ps_mem_rec->pv_base;
1715
1716 ps_dec_state_multi_core->ps_dec_state[i4_num_threads] = ps_dec_state;
1717
1718 ps_dec_state->ps_dec_state_multi_core = ps_dec_state_multi_core;
1719
1720 ps_dec_state->i4_num_cores = 1;
1721 /* @ */ /* Used for storing MemRecords */
1722 u4_num_mem_rec++;
1723 ps_mem_rec++;
1724
1725 /* Thread handle */
1726 ps_dec_state->pv_codec_thread_handle = ps_mem_rec->pv_base;
1727 u4_num_mem_rec++;
1728 ps_mem_rec++;
1729
1730 /*************************************************************************/
1731 /* For Motion Compensation Buffers */
1732 /*************************************************************************/
1733 pv = ps_mem_rec->pv_base;
1734
1735 /* for mc_fw_buf.pu1_y */
1736
1737 ps_dec_state->s_mc_fw_buf.pu1_y = pv;
1738 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1739
1740 u4_size = sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1741 /* for mc_fw_buf.pu1_u */
1742
1743 ps_dec_state->s_mc_fw_buf.pu1_u = pv;
1744 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1745
1746 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1747
1748 /* for mc_fw_buf.pu1_v */
1749
1750 ps_dec_state->s_mc_fw_buf.pu1_v = pv;
1751 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1752
1753 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1754
1755 /* for mc_bk_buf.pu1_y */
1756
1757 ps_dec_state->s_mc_bk_buf.pu1_y = pv;
1758 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1759
1760 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1761
1762 /* for mc_bk_buf.pu1_u */
1763
1764 ps_dec_state->s_mc_bk_buf.pu1_u = pv;
1765 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1766
1767 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1768
1769 /* for mc_bk_buf.pu1_v */
1770
1771 ps_dec_state->s_mc_bk_buf.pu1_v = pv;
1772 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1773
1774 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1775
1776 /* for mc_buf.pu1_y */
1777
1778 ps_dec_state->s_mc_buf.pu1_y = pv;
1779 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1780
1781 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1782
1783 /* for mc_buf.pu1_u */
1784
1785 ps_dec_state->s_mc_buf.pu1_u = pv;
1786 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1787
1788 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1789
1790 /* for mc_buf.pu1_v */
1791
1792 ps_dec_state->s_mc_buf.pu1_v = pv;
1793
1794 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1795
1796 u4_num_mem_rec++;
1797 ps_mem_rec++;
1798
1799
1800
1801 ps_dec_state->pv_pic_buf_mg = 0;
1802
1803 /*************************************************************************/
1804 /* For saving stack context to support global error handling */
1805 /*************************************************************************/
1806 ps_dec_state->pv_stack_cntxt = ps_mem_rec->pv_base;
1807 u4_num_mem_rec++;
1808 ps_mem_rec++;
1809
1810 }
1811
1812
1813
1814
1815
1816 /*************************************************************************/
1817 /* For Picture Buffer Manager */
1818 /*************************************************************************/
1819 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1820
1821 ps_dec_state->pv_pic_buf_mg = ps_mem_rec->pv_base;
1822 ps_dec_state->pv_pic_buf_base = (UWORD8 *)ps_mem_rec->pv_base + sizeof(buf_mgr_t);
1823
1824 u4_num_mem_rec++;
1825 ps_mem_rec++;
1826
1827
1828
1829 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1830 {
1831
1832 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads];
1833
1834
1835 /* --------------------------------------------------------------------- */
1836 /* Initializations */
1837
1838 ps_dec_state->u2_header_done = 0; /* Header decoding not done */
1839
1840
1841 {
1842 UWORD32 u4_max_frm_width,u4_max_frm_height;
1843
1844 u4_max_frm_width = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd);
1845 u4_max_frm_height = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht);
1846
1847 ps_dec_state->u2_create_max_width = u4_max_frm_width;
1848 ps_dec_state->u2_create_max_height = u4_max_frm_height;
1849
1850 ps_dec_state->i4_chromaFormat = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format;
1851 ps_dec_state->u4_frm_buf_stride = 0 ;
1852 ps_dec_state->u2_frame_width = u4_max_frm_width;
1853 ps_dec_state->u2_picture_width = u4_max_frm_width;
1854 ps_dec_state->u2_horizontal_size = u4_max_frm_width;
1855
1856 ps_dec_state->u2_frame_height = u4_max_frm_height;
1857 ps_dec_state->u2_vertical_size = u4_max_frm_height;
1858 ps_dec_state->u4_share_disp_buf = u4_share_disp_buf;
1859 ps_dec_state->u4_deinterlace = u4_deinterlace;
1860 ps_dec_state->ps_deint_pic = NULL;
1861 }
1862 }
1863
1864 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1865
1866 if((ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1867 &&((ps_dec_state->u2_vertical_size & 0x1) != 0))
1868 {
1869 //printf("Error! Height should be multiple of 2 if Chroma format is 422ILE\n");
1870 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_CHROMA_FORMAT_HEIGHT_ERROR;
1871 return(IV_FAIL);
1872
1873
1874 }
1875
1876 /* --------------------------------------------------------------------- */
1877
1878
1879 /* ! */
1880 // picture buffer manager initialization will be done only for first thread
1881 impeg2_disp_mgr_init(&ps_dec_state->s_disp_mgr);
1882 impeg2_buf_mgr_init((buf_mgr_t *)ps_dec_state->pv_pic_buf_mg);
1883
1884 /*************************************************************************/
1885 /* Internal Frame Buffers */
1886 /*************************************************************************/
1887
1888
1889 /* Set first frame to grey */
1890 {
1891 ps_frm_buf = ps_mem_rec;
1892 memset(ps_frm_buf->pv_base, 128, ps_frm_buf->u4_mem_size);
1893 ps_frm_buf++;
1894 }
1895
1896 if(0 == ps_dec_state->u4_share_disp_buf)
1897 {
1898 pic_buf_t *ps_pic_buf;
1899 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base;
1900 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++)
1901 {
1902 UWORD8 *pu1_buf;
1903 pu1_buf = ps_mem_rec->pv_base;
1904
1905 ps_pic_buf->pu1_y = pu1_buf;
1906 pu1_buf += i4_max_ht * i4_max_wd;
1907
1908 ps_pic_buf->pu1_u = pu1_buf;
1909 pu1_buf += i4_max_ht * i4_max_wd >> 2;
1910
1911 ps_pic_buf->pu1_v = pu1_buf;
1912 pu1_buf += i4_max_ht * i4_max_wd >> 2;
1913
1914 ps_pic_buf->i4_buf_id = i;
1915
1916 ps_pic_buf->u1_used_as_ref = 0;
1917
1918 ps_pic_buf->u4_ts = 0;
1919
1920 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i);
1921 ps_mem_rec++;
1922 ps_pic_buf++;
1923 }
1924 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1925 }
1926 else if (ps_dec_state->i4_chromaFormat != IV_YUV_420P)
1927 {
1928 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++)
1929 {
1930 ps_dec_state->pu1_chroma_ref_buf[i] = ps_mem_rec->pv_base;
1931 ps_mem_rec++;
1932 }
1933
1934 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1935 }
1936 else
1937 {
1938 ps_mem_rec+=NUM_INT_FRAME_BUFFERS;
1939 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1940 }
1941
1942
1943 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1944
1945 ps_dec_state->pu1_input_buffer = ps_mem_rec->pv_base;
1946 u4_num_mem_rec++;
1947 ps_mem_rec++;
1948
1949 ps_dec_state->pv_jobq_buf = ps_mem_rec->pv_base;
1950 ps_dec_state->i4_jobq_buf_size = ps_mem_rec->u4_mem_size;
1951 u4_num_mem_rec++;
1952 ps_mem_rec++;
1953
1954 if(u4_num_mem_rec > ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec)
1955 {
1956 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_NUM_MEM_REC_NOT_SUFFICIENT;
1957 return(IV_FAIL);
1958
1959 }
1960
1961 ps_dec_state->u1_flushfrm = 0;
1962 ps_dec_state->u1_flushcnt = 0;
1963 ps_dec_state->pv_jobq = impeg2_jobq_init(ps_dec_state->pv_jobq_buf, ps_dec_state->i4_jobq_buf_size);
1964
1965
1966 ps_dec_state->pv_deinterlacer_ctxt = ps_mem_rec->pv_base;
1967 u4_num_mem_rec++;
1968 ps_mem_rec++;
1969
1970 ps_dec_state->pu1_deint_fmt_buf = ps_mem_rec->pv_base;
1971 u4_num_mem_rec++;
1972 ps_mem_rec++;
1973
1974
1975 /*************************************************************************/
1976 /* Last MemTab is used for storing TabRecords */
1977 /*************************************************************************/
1978 ps_dec_state->pv_memTab = (void *)ps_mem_rec->pv_base;
1979 memcpy(ps_mem_rec->pv_base,ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location, ps_mem_rec->u4_mem_size);
1980 /* Updating in Decoder Context with memRecords */
1981 u4_num_mem_rec++;
1982 ps_mem_rec++;
1983 ps_dec_state->u4_num_mem_records = u4_num_mem_rec;
1984
1985
1986 ps_dec_state->u4_num_frames_decoded = 0;
1987 ps_dec_state->aps_ref_pics[0] = NULL;
1988 ps_dec_state->aps_ref_pics[1] = NULL;
1989
1990 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IV_SUCCESS;
1991
1992 impeg2d_init_arch(ps_dec_state);
1993
1994 impeg2d_init_function_ptr(ps_dec_state);
1995
1996 return(IV_SUCCESS);
1997 }
1998
1999 /*****************************************************************************/
2000 /* */
2001 /* Function Name : impeg2d_api_retrieve_mem_rec */
2002 /* */
2003 /* Description : */
2004 /* */
2005 /* Inputs : */
2006 /* Globals : <Does it use any global variables?> */
2007 /* Outputs : */
2008 /* Returns : void */
2009 /* */
2010 /* Issues : none */
2011 /* */
2012 /* Revision History: */
2013 /* */
2014 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2015 /* 22 10 2008 100356 Draft */
2016 /* */
2017 /*****************************************************************************/
impeg2d_api_retrieve_mem_rec(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)2018 IV_API_CALL_STATUS_T impeg2d_api_retrieve_mem_rec(iv_obj_t *ps_dechdl,
2019 void *pv_api_ip,
2020 void *pv_api_op)
2021 {
2022 UWORD32 u4_i;
2023 dec_state_t *ps_dec_state;
2024 dec_state_multi_core_t *ps_dec_state_multi_core;
2025 iv_mem_rec_t *ps_mem_rec;
2026 iv_mem_rec_t *ps_temp_rec;
2027
2028
2029
2030 impeg2d_retrieve_mem_rec_ip_t *ps_retr_mem_rec_ip;
2031 impeg2d_retrieve_mem_rec_op_t *ps_retr_mem_rec_op;
2032
2033 ps_retr_mem_rec_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip;
2034 ps_retr_mem_rec_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op;
2035
2036 ps_mem_rec = ps_retr_mem_rec_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
2037 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
2038 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
2039 ps_temp_rec = ps_dec_state->pv_memTab;
2040
2041 for(u4_i = 0; u4_i < (ps_dec_state->u4_num_mem_records);u4_i++)
2042 {
2043 ps_mem_rec[u4_i].u4_mem_size = ps_temp_rec[u4_i].u4_mem_size;
2044 ps_mem_rec[u4_i].u4_mem_alignment = ps_temp_rec[u4_i].u4_mem_alignment;
2045 ps_mem_rec[u4_i].e_mem_type = ps_temp_rec[u4_i].e_mem_type;
2046 ps_mem_rec[u4_i].pv_base = ps_temp_rec[u4_i].pv_base;
2047 }
2048
2049 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = IV_SUCCESS;
2050 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_num_mem_rec_filled = ps_dec_state->u4_num_mem_records;
2051
2052 impeg2_jobq_deinit(ps_dec_state->pv_jobq);
2053 IMPEG2D_PRINT_STATISTICS();
2054
2055
2056 return(IV_SUCCESS);
2057
2058 }
2059
2060 /*****************************************************************************/
2061 /* */
2062 /* Function Name : impeg2d_api_ctl */
2063 /* */
2064 /* Description : */
2065 /* */
2066 /* Inputs : */
2067 /* Globals : <Does it use any global variables?> */
2068 /* Outputs : */
2069 /* Returns : void */
2070 /* */
2071 /* Issues : none */
2072 /* */
2073 /* Revision History: */
2074 /* */
2075 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2076 /* 22 10 2008 100356 Draft */
2077 /* */
2078 /*****************************************************************************/
impeg2d_api_ctl(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)2079 IV_API_CALL_STATUS_T impeg2d_api_ctl(iv_obj_t *ps_dechdl,
2080 void *pv_api_ip,
2081 void *pv_api_op)
2082 {
2083 WORD32 i4_sub_cmd;
2084 UWORD32 *pu4_api_ip;
2085 IV_API_CALL_STATUS_T u4_error_code;
2086
2087 pu4_api_ip = (UWORD32 *)pv_api_ip;
2088 i4_sub_cmd = *(pu4_api_ip + 2);
2089
2090 switch(i4_sub_cmd)
2091 {
2092 case IVD_CMD_CTL_GETPARAMS:
2093 u4_error_code = impeg2d_api_get_status(ps_dechdl, (void *)pv_api_ip,
2094 (void *)pv_api_op);
2095 break;
2096
2097 case IVD_CMD_CTL_SETPARAMS:
2098 u4_error_code = impeg2d_api_set_params(ps_dechdl, (void *)pv_api_ip,
2099 (void *)pv_api_op);
2100 break;
2101
2102 case IVD_CMD_CTL_RESET:
2103 u4_error_code = impeg2d_api_reset(ps_dechdl, (void *)pv_api_ip,
2104 (void *)pv_api_op);
2105 break;
2106
2107 case IVD_CMD_CTL_SETDEFAULT:
2108 u4_error_code = impeg2d_api_set_default(ps_dechdl,
2109 (void *)pv_api_ip,
2110 (void *)pv_api_op);
2111 break;
2112
2113 case IVD_CMD_CTL_FLUSH:
2114 u4_error_code = impeg2d_api_set_flush_mode(ps_dechdl,
2115 (void *)pv_api_ip,
2116 (void *)pv_api_op);
2117 break;
2118
2119 case IVD_CMD_CTL_GETBUFINFO:
2120 u4_error_code = impeg2d_api_get_buf_info(ps_dechdl,
2121 (void *)pv_api_ip,
2122 (void *)pv_api_op);
2123 break;
2124
2125 case IVD_CMD_CTL_GETVERSION:
2126 u4_error_code = impeg2d_api_get_version(ps_dechdl, (void *)pv_api_ip,
2127 (void *)pv_api_op);
2128 break;
2129
2130 case IMPEG2D_CMD_CTL_SET_NUM_CORES:
2131 u4_error_code = impeg2d_api_set_num_cores(ps_dechdl,
2132 (void *)pv_api_ip,
2133 (void *)pv_api_op);
2134 break;
2135
2136 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS:
2137 u4_error_code = impeg2d_get_frame_dimensions(ps_dechdl,
2138 (void *)pv_api_ip,
2139 (void *)pv_api_op);
2140 break;
2141
2142 case IMPEG2D_CMD_CTL_GET_SEQ_INFO:
2143 u4_error_code = impeg2d_api_get_seq_info(ps_dechdl,
2144 (void *)pv_api_ip,
2145 (void *)pv_api_op);
2146 break;
2147
2148 case IMPEG2D_CMD_CTL_SET_PROCESSOR:
2149 u4_error_code = impeg2d_set_processor(ps_dechdl, (void *)pv_api_ip,
2150 (void *)pv_api_op);
2151 break;
2152
2153 default:
2154 u4_error_code = IV_FAIL;
2155 break;
2156 }
2157
2158 return (u4_error_code);
2159
2160 }
2161
2162 /*****************************************************************************/
2163 /* */
2164 /* Function Name : impeg2d_api_check_struct_sanity */
2165 /* */
2166 /* Description : */
2167 /* */
2168 /* Inputs : */
2169 /* Globals : <Does it use any global variables?> */
2170 /* Outputs : */
2171 /* Returns : void */
2172 /* */
2173 /* Issues : none */
2174 /* */
2175 /* Revision History: */
2176 /* */
2177 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2178 /* 22 10 2008 100356 Draft */
2179 /* */
2180 /*****************************************************************************/
impeg2d_api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)2181 IV_API_CALL_STATUS_T impeg2d_api_check_struct_sanity(iv_obj_t *ps_handle,
2182 void *pv_api_ip,
2183 void *pv_api_op)
2184 {
2185 WORD32 i4_cmd;
2186 UWORD32 *pu4_api_ip;
2187 UWORD32 *pu4_api_op;
2188 WORD32 i,j;
2189
2190 if(NULL == pv_api_op)
2191 return(IV_FAIL);
2192
2193 if(NULL == pv_api_ip)
2194 return(IV_FAIL);
2195
2196 pu4_api_ip = (UWORD32 *)pv_api_ip;
2197 pu4_api_op = (UWORD32 *)pv_api_op;
2198 i4_cmd = (IVD_API_COMMAND_TYPE_T)*(pu4_api_ip + 1);
2199
2200 /* error checks on handle */
2201 switch(i4_cmd)
2202 {
2203 case IV_CMD_GET_NUM_MEM_REC:
2204 case IV_CMD_FILL_NUM_MEM_REC:
2205 break;
2206 case IV_CMD_INIT:
2207 if(ps_handle == NULL)
2208 {
2209 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2210 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
2211 return IV_FAIL;
2212 }
2213
2214 if(ps_handle->u4_size != sizeof(iv_obj_t))
2215 {
2216 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2217 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
2218 return IV_FAIL;
2219 }
2220 break;
2221 case IVD_CMD_GET_DISPLAY_FRAME:
2222 case IVD_CMD_VIDEO_DECODE:
2223 case IV_CMD_RETRIEVE_MEMREC:
2224 case IVD_CMD_SET_DISPLAY_FRAME:
2225 case IVD_CMD_REL_DISPLAY_FRAME:
2226 case IVD_CMD_VIDEO_CTL:
2227 {
2228 if(ps_handle == NULL)
2229 {
2230 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2231 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
2232 return IV_FAIL;
2233 }
2234
2235 if(ps_handle->u4_size != sizeof(iv_obj_t))
2236 {
2237 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2238 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
2239 return IV_FAIL;
2240 }
2241 if(ps_handle->pv_fxns != impeg2d_api_function)
2242 {
2243 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2244 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
2245 return IV_FAIL;
2246 }
2247
2248 if(ps_handle->pv_codec_handle == NULL)
2249 {
2250 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2251 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
2252 return IV_FAIL;
2253 }
2254 }
2255 break;
2256 default:
2257 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2258 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
2259 return IV_FAIL;
2260 }
2261
2262 switch(i4_cmd)
2263 {
2264 case IV_CMD_GET_NUM_MEM_REC:
2265 {
2266 impeg2d_num_mem_rec_ip_t *ps_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip;
2267 impeg2d_num_mem_rec_op_t *ps_op = (impeg2d_num_mem_rec_op_t *)pv_api_op;
2268 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code = 0;
2269
2270 if(ps_ip->s_ivd_num_mem_rec_ip_t.u4_size != sizeof(impeg2d_num_mem_rec_ip_t))
2271 {
2272 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2273 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2274 return(IV_FAIL);
2275 }
2276
2277 if(ps_op->s_ivd_num_mem_rec_op_t.u4_size != sizeof(impeg2d_num_mem_rec_op_t))
2278 {
2279 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2280 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2281 return(IV_FAIL);
2282 }
2283 }
2284 break;
2285 case IV_CMD_FILL_NUM_MEM_REC:
2286 {
2287 impeg2d_fill_mem_rec_ip_t *ps_ip = (impeg2d_fill_mem_rec_ip_t *)pv_api_ip;
2288 impeg2d_fill_mem_rec_op_t *ps_op = (impeg2d_fill_mem_rec_op_t *)pv_api_op;
2289 iv_mem_rec_t *ps_mem_rec;
2290
2291 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
2292
2293 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size != sizeof(impeg2d_fill_mem_rec_ip_t))
2294 {
2295 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2296 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2297 return(IV_FAIL);
2298 }
2299
2300 if(ps_op->s_ivd_fill_mem_rec_op_t.u4_size != sizeof(impeg2d_fill_mem_rec_op_t))
2301 {
2302 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2303 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2304 return(IV_FAIL);
2305 }
2306
2307 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd < MIN_WIDTH)
2308 {
2309 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2310 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
2311 return(IV_FAIL);
2312 }
2313
2314 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd > MAX_WIDTH)
2315 {
2316 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2317 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
2318 return(IV_FAIL);
2319 }
2320
2321 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht < MIN_HEIGHT)
2322 {
2323 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2324 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
2325 return(IV_FAIL);
2326 }
2327
2328 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht > MAX_HEIGHT)
2329 {
2330 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2331 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
2332 return(IV_FAIL);
2333 }
2334
2335 if(NULL == ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location)
2336 {
2337 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2338 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT;
2339 return(IV_FAIL);
2340 }
2341
2342 /* check memrecords sizes are correct */
2343 ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
2344 for(i=0;i<NUM_MEM_RECORDS;i++)
2345 {
2346 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2347 {
2348 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2349 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2350 return IV_FAIL;
2351 }
2352 }
2353 }
2354 break;
2355
2356 case IV_CMD_INIT:
2357 {
2358 impeg2d_init_ip_t *ps_ip = (impeg2d_init_ip_t *)pv_api_ip;
2359 impeg2d_init_op_t *ps_op = (impeg2d_init_op_t *)pv_api_op;
2360 iv_mem_rec_t *ps_mem_rec;
2361 UWORD32 u4_tot_num_mem_recs;
2362
2363 ps_op->s_ivd_init_op_t.u4_error_code = 0;
2364
2365 if(ps_ip->s_ivd_init_ip_t.u4_size != sizeof(impeg2d_init_ip_t))
2366 {
2367 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2368 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2369 return(IV_FAIL);
2370 }
2371
2372 if(ps_op->s_ivd_init_op_t.u4_size != sizeof(impeg2d_init_op_t))
2373 {
2374 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2375 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2376 return(IV_FAIL);
2377 }
2378
2379 u4_tot_num_mem_recs = NUM_MEM_RECORDS;
2380
2381
2382
2383
2384 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec > u4_tot_num_mem_recs)
2385 {
2386 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2387 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_NOT_SUFFICIENT;
2388 return(IV_FAIL);
2389 }
2390
2391 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd < MIN_WIDTH)
2392 {
2393 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2394 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
2395 return(IV_FAIL);
2396 }
2397
2398 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd > MAX_WIDTH)
2399 {
2400 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2401 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
2402 return(IV_FAIL);
2403 }
2404
2405 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht < MIN_HEIGHT)
2406 {
2407 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2408 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
2409 return(IV_FAIL);
2410 }
2411
2412 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht > MAX_HEIGHT)
2413 {
2414 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2415 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
2416 return(IV_FAIL);
2417 }
2418
2419 if(NULL == ps_ip->s_ivd_init_ip_t.pv_mem_rec_location)
2420 {
2421 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2422 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT;
2423 return(IV_FAIL);
2424 }
2425
2426 if((ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P) &&
2427 (ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_422ILE)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_UV)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_VU))
2428 {
2429 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2430 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
2431 return(IV_FAIL);
2432 }
2433
2434 /* verify number of mem records */
2435 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec < NUM_MEM_RECORDS)
2436 {
2437 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2438 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_NOT_SUFFICIENT;
2439 return IV_FAIL;
2440 }
2441
2442 ps_mem_rec = ps_ip->s_ivd_init_ip_t.pv_mem_rec_location;
2443 /* verify wether first memrecord is handle or not */
2444 /*
2445 if(ps_mem_rec->pv_base != ps_handle)
2446 {
2447 // indicate the incorrect handle error
2448 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2449 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INVALID_HANDLE;
2450 return IV_FAIL;
2451 }
2452 */
2453 /* check memrecords sizes are correct */
2454 for(i=0;i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec ; i++)
2455 {
2456 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2457 {
2458 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2459 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2460 return IV_FAIL;
2461 }
2462 }
2463
2464 /* verify memtabs for overlapping regions */
2465 {
2466 UWORD8 *pau1_start[NUM_MEM_RECORDS];
2467 UWORD8 *pau1_end[NUM_MEM_RECORDS];
2468
2469
2470 pau1_start[0] = (UWORD8 *)(ps_mem_rec[0].pv_base);
2471 pau1_end[0] = (UWORD8 *)(ps_mem_rec[0].pv_base) + ps_mem_rec[0].u4_mem_size - 1;
2472 for(i = 1; i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
2473 {
2474 /* This array is populated to check memtab overlapp */
2475 pau1_start[i] = (UWORD8 *)(ps_mem_rec[i].pv_base);
2476 pau1_end[i] = (UWORD8 *)(ps_mem_rec[i].pv_base) + ps_mem_rec[i].u4_mem_size - 1;
2477
2478 for(j = 0; j < i; j++)
2479 {
2480 if((pau1_start[i] >= pau1_start[j]) && (pau1_start[i] <= pau1_end[j]))
2481 {
2482 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2483 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2484 return IV_FAIL;
2485 }
2486
2487 if((pau1_end[i] >= pau1_start[j]) && (pau1_end[i] <= pau1_end[j]))
2488 {
2489 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2490 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2491 return IV_FAIL;
2492 }
2493
2494 if((pau1_start[i] < pau1_start[j]) && (pau1_end[i] > pau1_end[j]))
2495 {
2496 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2497 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2498 return IV_FAIL;
2499 }
2500 }
2501 }
2502 }
2503
2504
2505
2506
2507 {
2508 iv_mem_rec_t as_mem_rec_ittiam_api[NUM_MEM_RECORDS];
2509
2510 impeg2d_fill_mem_rec_ip_t s_fill_mem_rec_ip;
2511 impeg2d_fill_mem_rec_op_t s_fill_mem_rec_op;
2512 IV_API_CALL_STATUS_T e_status;
2513 WORD32 i4_num_memrec;
2514 {
2515
2516 iv_num_mem_rec_ip_t s_no_of_mem_rec_query_ip;
2517 iv_num_mem_rec_op_t s_no_of_mem_rec_query_op;
2518
2519
2520 s_no_of_mem_rec_query_ip.u4_size = sizeof(iv_num_mem_rec_ip_t);
2521 s_no_of_mem_rec_query_op.u4_size = sizeof(iv_num_mem_rec_op_t);
2522
2523 s_no_of_mem_rec_query_ip.e_cmd = IV_CMD_GET_NUM_MEM_REC;
2524 impeg2d_api_function(NULL,
2525 (void *)&s_no_of_mem_rec_query_ip,
2526 (void *)&s_no_of_mem_rec_query_op);
2527
2528 i4_num_memrec = s_no_of_mem_rec_query_op.u4_num_mem_rec;
2529
2530
2531
2532 }
2533
2534
2535 /* initialize mem records array with sizes */
2536 for(i = 0; i < i4_num_memrec; i++)
2537 {
2538 as_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
2539 }
2540
2541 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_size = sizeof(impeg2d_fill_mem_rec_ip_t);
2542 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.e_cmd = IV_CMD_FILL_NUM_MEM_REC;
2543 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd = ps_ip->s_ivd_init_ip_t.u4_frm_max_wd;
2544 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht = ps_ip->s_ivd_init_ip_t.u4_frm_max_ht;
2545 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location = as_mem_rec_ittiam_api;
2546 s_fill_mem_rec_ip.u4_share_disp_buf = ps_ip->u4_share_disp_buf;
2547 s_fill_mem_rec_ip.e_output_format = ps_ip->s_ivd_init_ip_t.e_output_format;
2548 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_size = sizeof(impeg2d_fill_mem_rec_op_t);
2549
2550
2551 e_status = impeg2d_api_function(NULL,
2552 (void *)&s_fill_mem_rec_ip,
2553 (void *)&s_fill_mem_rec_op);
2554 if(IV_FAIL == e_status)
2555 {
2556 ps_op->s_ivd_init_op_t.u4_error_code = s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_error_code;
2557 return(IV_FAIL);
2558 }
2559
2560
2561
2562 for(i = 0; i < i4_num_memrec; i ++)
2563 {
2564 if(ps_mem_rec[i].pv_base == NULL)
2565 {
2566 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2567 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_BASE_NULL;
2568 return IV_FAIL;
2569 }
2570 #ifdef CHECK_ALIGN
2571
2572 if((UWORD32)(ps_mem_rec[i].pv_base) & (ps_mem_rec[i].u4_mem_alignment - 1))
2573 {
2574 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2575 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
2576 return IV_FAIL;
2577 }
2578 #endif //CHECK_ALIGN
2579 if(ps_mem_rec[i].u4_mem_alignment != as_mem_rec_ittiam_api[i].u4_mem_alignment)
2580 {
2581 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2582 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
2583 return IV_FAIL;
2584 }
2585
2586 if(ps_mem_rec[i].u4_mem_size < as_mem_rec_ittiam_api[i].u4_mem_size)
2587 {
2588 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2589 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INSUFFICIENT_SIZE;
2590 return IV_FAIL;
2591 }
2592
2593 if(ps_mem_rec[i].e_mem_type != as_mem_rec_ittiam_api[i].e_mem_type)
2594 {
2595 if (IV_EXTERNAL_CACHEABLE_SCRATCH_MEM == as_mem_rec_ittiam_api[i].e_mem_type)
2596 {
2597 if (IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM == ps_mem_rec[i].e_mem_type)
2598 {
2599 continue;
2600 }
2601 }
2602 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2603 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INCORRECT_TYPE;
2604 return IV_FAIL;
2605 }
2606 }
2607 }
2608
2609
2610 }
2611 break;
2612
2613 case IVD_CMD_GET_DISPLAY_FRAME:
2614 {
2615 impeg2d_get_display_frame_ip_t *ps_ip = (impeg2d_get_display_frame_ip_t *)pv_api_ip;
2616 impeg2d_get_display_frame_op_t *ps_op = (impeg2d_get_display_frame_op_t *)pv_api_op;
2617
2618 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
2619
2620 if(ps_ip->s_ivd_get_display_frame_ip_t.u4_size != sizeof(impeg2d_get_display_frame_ip_t))
2621 {
2622 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2623 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2624 return(IV_FAIL);
2625 }
2626
2627 if(ps_op->s_ivd_get_display_frame_op_t.u4_size != sizeof(impeg2d_get_display_frame_op_t))
2628 {
2629 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2630 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2631 return(IV_FAIL);
2632 }
2633
2634 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs == 0)
2635 {
2636 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2637 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2638 return IV_FAIL;
2639 }
2640
2641 for(i = 0; i< (WORD32)ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs;i++)
2642 {
2643 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.pu1_bufs[i] == NULL)
2644 {
2645 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2646 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2647 return IV_FAIL;
2648 }
2649
2650 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0)
2651 {
2652 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2653 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2654 return IV_FAIL;
2655 }
2656 /*
2657 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0)
2658 {
2659 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2660 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2661 return IV_FAIL;
2662 }
2663 */
2664 }
2665 }
2666 break;
2667 case IVD_CMD_REL_DISPLAY_FRAME:
2668 {
2669 impeg2d_rel_display_frame_ip_t *ps_ip = (impeg2d_rel_display_frame_ip_t *)pv_api_ip;
2670 impeg2d_rel_display_frame_op_t *ps_op = (impeg2d_rel_display_frame_op_t *)pv_api_op;
2671
2672 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
2673
2674 if ((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(impeg2d_rel_display_frame_ip_t))
2675 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(ivd_rel_display_frame_ip_t)))
2676 {
2677 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2678 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2679 return(IV_FAIL);
2680 }
2681
2682 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(impeg2d_rel_display_frame_op_t)) &&
2683 (ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(ivd_rel_display_frame_op_t)))
2684 {
2685 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2686 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2687 return(IV_FAIL);
2688 }
2689
2690 }
2691 break;
2692
2693
2694 case IVD_CMD_SET_DISPLAY_FRAME:
2695 {
2696 impeg2d_set_display_frame_ip_t *ps_ip = (impeg2d_set_display_frame_ip_t *)pv_api_ip;
2697 impeg2d_set_display_frame_op_t *ps_op = (impeg2d_set_display_frame_op_t *)pv_api_op;
2698 UWORD32 j, i;
2699
2700 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
2701
2702 if ((ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(impeg2d_set_display_frame_ip_t))
2703 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(ivd_set_display_frame_ip_t)))
2704 {
2705 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2706 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2707 return(IV_FAIL);
2708 }
2709
2710 if((ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(impeg2d_set_display_frame_op_t)) &&
2711 (ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(ivd_set_display_frame_op_t)))
2712 {
2713 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2714 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2715 return(IV_FAIL);
2716 }
2717
2718 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
2719 {
2720 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2721 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2722 return IV_FAIL;
2723 }
2724
2725 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs; j++)
2726 {
2727 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs == 0)
2728 {
2729 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2730 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2731 return IV_FAIL;
2732 }
2733
2734 for(i=0;i< ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;i++)
2735 {
2736 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i] == NULL)
2737 {
2738 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2739 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2740 return IV_FAIL;
2741 }
2742
2743 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i] == 0)
2744 {
2745 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2746 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2747 return IV_FAIL;
2748 }
2749 }
2750 }
2751 }
2752 break;
2753
2754 case IVD_CMD_VIDEO_DECODE:
2755 {
2756 impeg2d_video_decode_ip_t *ps_ip = (impeg2d_video_decode_ip_t *)pv_api_ip;
2757 impeg2d_video_decode_op_t *ps_op = (impeg2d_video_decode_op_t *)pv_api_op;
2758
2759 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
2760
2761 if(ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(impeg2d_video_decode_ip_t))
2762 {
2763 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2764 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2765 return(IV_FAIL);
2766 }
2767
2768 if(ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(impeg2d_video_decode_op_t))
2769 {
2770 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2771 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2772 return(IV_FAIL);
2773 }
2774
2775 }
2776 break;
2777
2778 case IV_CMD_RETRIEVE_MEMREC:
2779 {
2780 impeg2d_retrieve_mem_rec_ip_t *ps_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip;
2781 impeg2d_retrieve_mem_rec_op_t *ps_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op;
2782 iv_mem_rec_t *ps_mem_rec;
2783
2784 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = 0;
2785
2786 if(ps_ip->s_ivd_retrieve_mem_rec_ip_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_ip_t))
2787 {
2788 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2789 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2790 return(IV_FAIL);
2791 }
2792
2793 if(ps_op->s_ivd_retrieve_mem_rec_op_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_op_t))
2794 {
2795 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2796 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2797 return(IV_FAIL);
2798 }
2799
2800 ps_mem_rec = ps_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
2801 /* check memrecords sizes are correct */
2802 for(i=0;i < NUM_MEM_RECORDS ; i++)
2803 {
2804 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2805 {
2806 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2807 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2808 return IV_FAIL;
2809 }
2810 }
2811 }
2812 break;
2813
2814 case IVD_CMD_VIDEO_CTL:
2815 {
2816 UWORD32 *pu4_ptr_cmd;
2817 UWORD32 u4_sub_command;
2818
2819 pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
2820 pu4_ptr_cmd += 2;
2821 u4_sub_command = *pu4_ptr_cmd;
2822
2823 switch(u4_sub_command)
2824 {
2825 case IVD_CMD_CTL_SETPARAMS:
2826 {
2827 impeg2d_ctl_set_config_ip_t *ps_ip;
2828 impeg2d_ctl_set_config_op_t *ps_op;
2829 ps_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip;
2830 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
2831
2832 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0;
2833
2834 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size != sizeof(impeg2d_ctl_set_config_ip_t))
2835 {
2836 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2837 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2838 return IV_FAIL;
2839 }
2840 }
2841 case IVD_CMD_CTL_SETDEFAULT:
2842 {
2843 impeg2d_ctl_set_config_op_t *ps_op;
2844 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
2845 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0;
2846
2847 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size != sizeof(impeg2d_ctl_set_config_op_t))
2848 {
2849 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2850 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2851 return IV_FAIL;
2852 }
2853 }
2854 break;
2855
2856 case IVD_CMD_CTL_GETPARAMS:
2857 {
2858 impeg2d_ctl_getstatus_ip_t *ps_ip;
2859 impeg2d_ctl_getstatus_op_t *ps_op;
2860
2861 ps_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip;
2862 ps_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op;
2863
2864 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code = 0;
2865
2866 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size != sizeof(impeg2d_ctl_getstatus_ip_t))
2867 {
2868 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2869 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2870 return IV_FAIL;
2871 }
2872 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size != sizeof(impeg2d_ctl_getstatus_op_t))
2873 {
2874 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2875 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2876 return IV_FAIL;
2877 }
2878 }
2879 break;
2880
2881 case IVD_CMD_CTL_GETBUFINFO:
2882 {
2883 impeg2d_ctl_getbufinfo_ip_t *ps_ip;
2884 impeg2d_ctl_getbufinfo_op_t *ps_op;
2885 ps_ip = (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip;
2886 ps_op = (impeg2d_ctl_getbufinfo_op_t *)pv_api_op;
2887
2888 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = 0;
2889
2890 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_ip_t))
2891 {
2892 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2893 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2894 return IV_FAIL;
2895 }
2896 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_op_t))
2897 {
2898 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2899 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2900 return IV_FAIL;
2901 }
2902 }
2903 break;
2904
2905 case IVD_CMD_CTL_GETVERSION:
2906 {
2907 impeg2d_ctl_getversioninfo_ip_t *ps_ip;
2908 impeg2d_ctl_getversioninfo_op_t *ps_op;
2909 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip;
2910 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op;
2911
2912 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = 0;
2913
2914 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_ip_t))
2915 {
2916 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2917 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2918 return IV_FAIL;
2919 }
2920 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_op_t))
2921 {
2922 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2923 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2924 return IV_FAIL;
2925 }
2926 }
2927 break;
2928
2929 case IVD_CMD_CTL_FLUSH:
2930 {
2931 impeg2d_ctl_flush_ip_t *ps_ip;
2932 impeg2d_ctl_flush_op_t *ps_op;
2933 ps_ip = (impeg2d_ctl_flush_ip_t *)pv_api_ip;
2934 ps_op = (impeg2d_ctl_flush_op_t *)pv_api_op;
2935
2936 ps_op->s_ivd_ctl_flush_op_t.u4_error_code = 0;
2937
2938 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size != sizeof(impeg2d_ctl_flush_ip_t))
2939 {
2940 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2941 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2942 return IV_FAIL;
2943 }
2944 if(ps_op->s_ivd_ctl_flush_op_t.u4_size != sizeof(impeg2d_ctl_flush_op_t))
2945 {
2946 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2947 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2948 return IV_FAIL;
2949 }
2950 }
2951 break;
2952
2953 case IVD_CMD_CTL_RESET:
2954 {
2955 impeg2d_ctl_reset_ip_t *ps_ip;
2956 impeg2d_ctl_reset_op_t *ps_op;
2957 ps_ip = (impeg2d_ctl_reset_ip_t *)pv_api_ip;
2958 ps_op = (impeg2d_ctl_reset_op_t *)pv_api_op;
2959
2960 ps_op->s_ivd_ctl_reset_op_t.u4_error_code = 0;
2961
2962 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size != sizeof(impeg2d_ctl_reset_ip_t))
2963 {
2964 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2965 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2966 return IV_FAIL;
2967 }
2968 if(ps_op->s_ivd_ctl_reset_op_t.u4_size != sizeof(impeg2d_ctl_reset_op_t))
2969 {
2970 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2971 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2972 return IV_FAIL;
2973 }
2974 }
2975 break;
2976
2977 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS:
2978 {
2979 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip;
2980 impeg2d_ctl_get_frame_dimensions_op_t *ps_op;
2981
2982 ps_ip =
2983 (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
2984 ps_op =
2985 (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op;
2986
2987 if(ps_ip->u4_size
2988 != sizeof(impeg2d_ctl_get_frame_dimensions_ip_t))
2989 {
2990 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2991 ps_op->u4_error_code |=
2992 IVD_IP_API_STRUCT_SIZE_INCORRECT;
2993 return IV_FAIL;
2994 }
2995
2996 if(ps_op->u4_size
2997 != sizeof(impeg2d_ctl_get_frame_dimensions_op_t))
2998 {
2999 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3000 ps_op->u4_error_code |=
3001 IVD_OP_API_STRUCT_SIZE_INCORRECT;
3002 return IV_FAIL;
3003 }
3004
3005 break;
3006 }
3007 case IMPEG2D_CMD_CTL_GET_SEQ_INFO:
3008 {
3009 impeg2d_ctl_get_seq_info_ip_t *ps_ip;
3010 impeg2d_ctl_get_seq_info_op_t *ps_op;
3011
3012 ps_ip =
3013 (impeg2d_ctl_get_seq_info_ip_t *)pv_api_ip;
3014 ps_op =
3015 (impeg2d_ctl_get_seq_info_op_t *)pv_api_op;
3016
3017 if(ps_ip->u4_size
3018 != sizeof(impeg2d_ctl_get_seq_info_ip_t))
3019 {
3020 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3021 ps_op->u4_error_code |=
3022 IVD_IP_API_STRUCT_SIZE_INCORRECT;
3023 return IV_FAIL;
3024 }
3025
3026 if(ps_op->u4_size
3027 != sizeof(impeg2d_ctl_get_seq_info_op_t))
3028 {
3029 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3030 ps_op->u4_error_code |=
3031 IVD_OP_API_STRUCT_SIZE_INCORRECT;
3032 return IV_FAIL;
3033 }
3034
3035 break;
3036 }
3037 case IMPEG2D_CMD_CTL_SET_NUM_CORES:
3038 {
3039 impeg2d_ctl_set_num_cores_ip_t *ps_ip;
3040 impeg2d_ctl_set_num_cores_op_t *ps_op;
3041
3042 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip;
3043 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op;
3044
3045 if(ps_ip->u4_size
3046 != sizeof(impeg2d_ctl_set_num_cores_ip_t))
3047 {
3048 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3049 ps_op->u4_error_code |=
3050 IVD_IP_API_STRUCT_SIZE_INCORRECT;
3051 return IV_FAIL;
3052 }
3053
3054 if(ps_op->u4_size
3055 != sizeof(impeg2d_ctl_set_num_cores_op_t))
3056 {
3057 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3058 ps_op->u4_error_code |=
3059 IVD_OP_API_STRUCT_SIZE_INCORRECT;
3060 return IV_FAIL;
3061 }
3062
3063 #ifdef MULTICORE
3064 if((ps_ip->u4_num_cores < 1) || (ps_ip->u4_num_cores > MAX_THREADS))
3065 #else
3066 if(ps_ip->u4_num_cores != 1)
3067 #endif
3068 {
3069 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3070 return IV_FAIL;
3071 }
3072 break;
3073 }
3074 case IMPEG2D_CMD_CTL_SET_PROCESSOR:
3075 {
3076 impeg2d_ctl_set_processor_ip_t *ps_ip;
3077 impeg2d_ctl_set_processor_op_t *ps_op;
3078
3079 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip;
3080 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op;
3081
3082 if(ps_ip->u4_size
3083 != sizeof(impeg2d_ctl_set_processor_ip_t))
3084 {
3085 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3086 ps_op->u4_error_code |=
3087 IVD_IP_API_STRUCT_SIZE_INCORRECT;
3088 return IV_FAIL;
3089 }
3090
3091 if(ps_op->u4_size
3092 != sizeof(impeg2d_ctl_set_processor_op_t))
3093 {
3094 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3095 ps_op->u4_error_code |=
3096 IVD_OP_API_STRUCT_SIZE_INCORRECT;
3097 return IV_FAIL;
3098 }
3099
3100 break;
3101 }
3102 default:
3103 break;
3104
3105 }
3106 }
3107 break;
3108
3109 default:
3110 { *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
3111 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
3112 return IV_FAIL;
3113 }
3114
3115
3116 }
3117
3118 return IV_SUCCESS;
3119 }
3120
3121 /*****************************************************************************/
3122 /* */
3123 /* Function Name : impeg2d_api_entity */
3124 /* */
3125 /* Description : */
3126 /* */
3127 /* Inputs : */
3128 /* Globals : <Does it use any global variables?> */
3129 /* Outputs : */
3130 /* Returns : void */
3131 /* */
3132 /* Issues : none */
3133 /* */
3134 /* Revision History: */
3135 /* */
3136 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3137 /* 22 10 2008 100356 Draft */
3138 /* */
3139 /*****************************************************************************/
3140
3141
impeg2d_api_entity(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)3142 IV_API_CALL_STATUS_T impeg2d_api_entity(iv_obj_t *ps_dechdl,
3143 void *pv_api_ip,
3144 void *pv_api_op)
3145 {
3146 iv_obj_t *ps_dec_handle;
3147 dec_state_t *ps_dec_state;
3148 dec_state_multi_core_t *ps_dec_state_multi_core;
3149
3150 impeg2d_video_decode_ip_t *ps_dec_ip;
3151
3152 impeg2d_video_decode_op_t *ps_dec_op;
3153 WORD32 bytes_remaining;
3154 pic_buf_t *ps_disp_pic;
3155
3156
3157
3158 ps_dec_ip = (impeg2d_video_decode_ip_t *)pv_api_ip;
3159 ps_dec_op = (impeg2d_video_decode_op_t *)pv_api_op;
3160
3161 memset(ps_dec_op,0,sizeof(impeg2d_video_decode_op_t));
3162
3163 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3164 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3165 bytes_remaining = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes;
3166
3167 ps_dec_handle = (iv_obj_t *)ps_dechdl;
3168
3169 if(ps_dechdl == NULL)
3170 {
3171 return(IV_FAIL);
3172 }
3173
3174
3175
3176 ps_dec_state_multi_core = ps_dec_handle->pv_codec_handle;
3177 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
3178
3179 ps_dec_state->ps_disp_frm_buf = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3180 if(0 == ps_dec_state->u4_share_disp_buf)
3181 {
3182 ps_dec_state->ps_disp_frm_buf->pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0];
3183 ps_dec_state->ps_disp_frm_buf->pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1];
3184 ps_dec_state->ps_disp_frm_buf->pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2];
3185 }
3186
3187 ps_dec_state->ps_disp_pic = NULL;
3188 ps_dec_state->i4_frame_decoded = 0;
3189 /*rest bytes consumed */
3190 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = 0;
3191
3192 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IV_SUCCESS;
3193
3194 if((ps_dec_ip->s_ivd_video_decode_ip_t.pv_stream_buffer == NULL)&&(ps_dec_state->u1_flushfrm==0))
3195 {
3196 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3197 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
3198 return IV_FAIL;
3199 }
3200
3201
3202 if (ps_dec_state->u4_num_frames_decoded > NUM_FRAMES_LIMIT)
3203 {
3204 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IMPEG2D_SAMPLE_VERSION_LIMIT_ERR;
3205 return(IV_FAIL);
3206 }
3207
3208 if(((0 == ps_dec_state->u2_header_done) || (ps_dec_state->u2_decode_header == 1)) && (ps_dec_state->u1_flushfrm == 0))
3209 {
3210 impeg2d_dec_hdr(ps_dec_state,ps_dec_ip ,ps_dec_op);
3211 bytes_remaining -= ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed;
3212 }
3213
3214 if((1 != ps_dec_state->u2_decode_header) &&
3215 (((bytes_remaining > 0) && (1 == ps_dec_state->u2_header_done)) || ps_dec_state->u1_flushfrm))
3216 {
3217 if(ps_dec_state->u1_flushfrm)
3218 {
3219 if(ps_dec_state->aps_ref_pics[1] != NULL)
3220 {
3221 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[1], ps_dec_state->aps_ref_pics[1]->i4_buf_id);
3222 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[1]->i4_buf_id, BUF_MGR_REF);
3223 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
3224
3225 ps_dec_state->aps_ref_pics[1] = NULL;
3226 ps_dec_state->aps_ref_pics[0] = NULL;
3227
3228 }
3229 else if(ps_dec_state->aps_ref_pics[0] != NULL)
3230 {
3231 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[0], ps_dec_state->aps_ref_pics[0]->i4_buf_id);
3232 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
3233
3234 ps_dec_state->aps_ref_pics[0] = NULL;
3235 }
3236 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t);
3237 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3238
3239 ps_disp_pic = impeg2_disp_mgr_get(&ps_dec_state->s_disp_mgr, &ps_dec_state->i4_disp_buf_id);
3240
3241 ps_dec_state->ps_disp_pic = ps_disp_pic;
3242 if(ps_disp_pic == NULL)
3243 {
3244 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3245 }
3246 else
3247 {
3248 WORD32 fmt_conv;
3249 if(0 == ps_dec_state->u4_share_disp_buf)
3250 {
3251 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0];
3252 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1];
3253 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2];
3254 fmt_conv = 1;
3255 }
3256 else
3257 {
3258 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_disp_pic->pu1_y;
3259 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat)
3260 {
3261 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_disp_pic->pu1_u;
3262 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_disp_pic->pu1_v;
3263 fmt_conv = 0;
3264 }
3265 else
3266 {
3267 UWORD8 *pu1_buf;
3268
3269 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[1];
3270 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = pu1_buf;
3271
3272 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[2];
3273 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = pu1_buf;
3274 fmt_conv = 1;
3275 }
3276 }
3277
3278 if(fmt_conv == 1)
3279 {
3280 iv_yuv_buf_t *ps_dst;
3281
3282
3283 ps_dst = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3284 if(ps_dec_state->u4_deinterlace && (0 == ps_dec_state->u2_progressive_frame))
3285 {
3286 impeg2d_deinterlace(ps_dec_state,
3287 ps_disp_pic,
3288 ps_dst,
3289 0,
3290 ps_dec_state->u2_vertical_size);
3291
3292 }
3293 else
3294 {
3295 impeg2d_format_convert(ps_dec_state,
3296 ps_disp_pic,
3297 ps_dst,
3298 0,
3299 ps_dec_state->u2_vertical_size);
3300 }
3301 }
3302
3303 if(ps_dec_state->u4_deinterlace)
3304 {
3305 if(ps_dec_state->ps_deint_pic)
3306 {
3307 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg,
3308 ps_dec_state->ps_deint_pic->i4_buf_id,
3309 MPEG2_BUF_MGR_DEINT);
3310 }
3311 ps_dec_state->ps_deint_pic = ps_disp_pic;
3312 }
3313 if(0 == ps_dec_state->u4_share_disp_buf)
3314 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
3315
3316 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_ht = ps_dec_state->u2_vertical_size;
3317 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_wd = ps_dec_state->u2_horizontal_size;
3318 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1;
3319
3320 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_disp_pic->i4_buf_id;
3321 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_disp_pic->u4_ts;
3322
3323 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
3324
3325 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type);
3326
3327 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE;
3328
3329 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size;
3330 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride;
3331 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size;
3332
3333 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size >> 1;
3334 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3335 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = ps_dec_state->u2_vertical_size >> 1;
3336
3337 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = ps_dec_state->u2_horizontal_size >> 1;
3338 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3339 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = ps_dec_state->u2_vertical_size >> 1;
3340 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3341
3342 switch(ps_dec_state->i4_chromaFormat)
3343 {
3344 case IV_YUV_420SP_UV:
3345 case IV_YUV_420SP_VU:
3346 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size;
3347 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride;
3348 break;
3349 case IV_YUV_422ILE:
3350 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0;
3351 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0;
3352 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0;
3353 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0;
3354 break;
3355 default:
3356 break;
3357 }
3358
3359
3360 }
3361 if(ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3362 {
3363 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3364 {
3365 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0],
3366 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1],
3367 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2],
3368 ps_dec_state->u4_frm_buf_stride,
3369 ps_dec_state->u2_horizontal_size,
3370 ps_dec_state->u2_vertical_size,
3371 ps_dec_state->i4_chromaFormat,
3372 ps_dec_state->u2_horizontal_size,
3373 ps_dec_state->u2_vertical_size);
3374 }
3375 return(IV_SUCCESS);
3376 }
3377 else
3378 {
3379 ps_dec_state->u1_flushfrm = 0;
3380
3381 return(IV_FAIL);
3382 }
3383
3384 }
3385 else if(ps_dec_state->u1_flushfrm==0)
3386 {
3387 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t);
3388 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3389 if(ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes < 4)
3390 {
3391 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes;
3392 return(IV_FAIL);
3393 }
3394
3395 if(1 == ps_dec_state->u4_share_disp_buf)
3396 {
3397 if(0 == impeg2_buf_mgr_check_free(ps_dec_state->pv_pic_buf_mg))
3398 {
3399 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code =
3400 (IMPEG2D_ERROR_CODES_T)IVD_DEC_REF_BUF_NULL;
3401 return IV_FAIL;
3402 }
3403 }
3404
3405
3406 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
3407
3408 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type);
3409
3410 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE;
3411
3412 if (0 == ps_dec_state->u4_frm_buf_stride)
3413 {
3414 ps_dec_state->u4_frm_buf_stride = (ps_dec_state->u2_horizontal_size);
3415 }
3416
3417 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size;
3418 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride;
3419 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size;
3420
3421 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size >> 1;
3422 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3423 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = ps_dec_state->u2_vertical_size >> 1;
3424
3425 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = ps_dec_state->u2_horizontal_size >> 1;
3426 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3427 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = ps_dec_state->u2_vertical_size >> 1;
3428 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3429
3430 switch(ps_dec_state->i4_chromaFormat)
3431 {
3432 case IV_YUV_420SP_UV:
3433 case IV_YUV_420SP_VU:
3434 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size;
3435 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride;
3436 break;
3437 case IV_YUV_422ILE:
3438 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0;
3439 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0;
3440 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0;
3441 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0;
3442 break;
3443 default:
3444 break;
3445 }
3446
3447 if( ps_dec_state->u1_flushfrm == 0)
3448 {
3449 ps_dec_state->u1_flushcnt = 0;
3450
3451 ps_dec_state->ps_out_buf = &ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer;
3452 if (IV_SUCCESS != check_app_out_buf_size(ps_dec_state))
3453 {
3454 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
3455 return IV_FAIL;
3456 }
3457
3458 /*************************************************************************/
3459 /* Frame Decode */
3460 /*************************************************************************/
3461 ps_dec_state->u4_inp_ts = ps_dec_ip->s_ivd_video_decode_ip_t.u4_ts;
3462
3463 impeg2d_dec_frm(ps_dec_state,ps_dec_ip,ps_dec_op);
3464
3465 if (IVD_ERROR_NONE ==
3466 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code)
3467 {
3468 if(ps_dec_state->u1_first_frame_done == 0)
3469 {
3470 ps_dec_state->u1_first_frame_done = 1;
3471 }
3472
3473 if(ps_dec_state->ps_disp_pic)
3474 {
3475 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1;
3476 switch(ps_dec_state->ps_disp_pic->e_pic_type)
3477 {
3478 case I_PIC :
3479 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME;
3480 break;
3481
3482 case P_PIC:
3483 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_P_FRAME;
3484 break;
3485
3486 case B_PIC:
3487 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_B_FRAME;
3488 break;
3489
3490 case D_PIC:
3491 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME;
3492 break;
3493
3494 default :
3495 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_FRAMETYPE_DEFAULT;
3496 break;
3497 }
3498 }
3499 else
3500 {
3501 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3502 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_NA_FRAME;
3503 }
3504
3505 ps_dec_state->u4_num_frames_decoded++;
3506 }
3507 }
3508 else
3509 {
3510 ps_dec_state->u1_flushcnt++;
3511 }
3512 }
3513 if(ps_dec_state->ps_disp_pic)
3514 {
3515 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_dec_state->ps_disp_pic->i4_buf_id;
3516 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_dec_state->ps_disp_pic->u4_ts;
3517
3518 if(0 == ps_dec_state->u4_share_disp_buf)
3519 {
3520 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
3521 }
3522 }
3523
3524 if(ps_dec_state->u4_deinterlace)
3525 {
3526 if(ps_dec_state->ps_deint_pic)
3527 {
3528 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg,
3529 ps_dec_state->ps_deint_pic->i4_buf_id,
3530 MPEG2_BUF_MGR_DEINT);
3531 }
3532 ps_dec_state->ps_deint_pic = ps_dec_state->ps_disp_pic;
3533 }
3534
3535 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3536 {
3537 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0],
3538 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1],
3539 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2],
3540 ps_dec_state->u4_frm_buf_stride,
3541 ps_dec_state->u2_horizontal_size,
3542 ps_dec_state->u2_vertical_size,
3543 ps_dec_state->i4_chromaFormat,
3544 ps_dec_state->u2_horizontal_size,
3545 ps_dec_state->u2_vertical_size);
3546 }
3547
3548 }
3549
3550 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = 1;
3551 ps_dec_op->s_ivd_video_decode_op_t.e4_fld_type = ps_dec_state->s_disp_op.e4_fld_type;
3552
3553
3554 if(ps_dec_op->s_ivd_video_decode_op_t.u4_error_code)
3555 return IV_FAIL;
3556 else
3557 return IV_SUCCESS;
3558 }
3559