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1 //===- AMDGPURegisterBankInfo.cpp -------------------------------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the RegisterBankInfo class for
11 /// AMDGPU.
12 /// \todo This should be generated by TableGen.
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPURegisterBankInfo.h"
16 #include "AMDGPUInstrInfo.h"
17 #include "SIMachineFunctionInfo.h"
18 #include "SIRegisterInfo.h"
19 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
20 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
21 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
22 #include "llvm/CodeGen/TargetRegisterInfo.h"
23 #include "llvm/CodeGen/TargetSubtargetInfo.h"
24 #include "llvm/IR/Constants.h"
25 
26 #define GET_TARGET_REGBANK_IMPL
27 #include "AMDGPUGenRegisterBank.inc"
28 
29 // This file will be TableGen'ed at some point.
30 #include "AMDGPUGenRegisterBankInfo.def"
31 
32 using namespace llvm;
33 
AMDGPURegisterBankInfo(const TargetRegisterInfo & TRI)34 AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI)
35     : AMDGPUGenRegisterBankInfo(),
36       TRI(static_cast<const SIRegisterInfo*>(&TRI)) {
37 
38   // HACK: Until this is fully tablegen'd
39   static bool AlreadyInit = false;
40   if (AlreadyInit)
41     return;
42 
43   AlreadyInit = true;
44 
45   const RegisterBank &RBSGPR = getRegBank(AMDGPU::SGPRRegBankID);
46   (void)RBSGPR;
47   assert(&RBSGPR == &AMDGPU::SGPRRegBank);
48 
49   const RegisterBank &RBVGPR = getRegBank(AMDGPU::VGPRRegBankID);
50   (void)RBVGPR;
51   assert(&RBVGPR == &AMDGPU::VGPRRegBank);
52 
53 }
54 
isConstant(const MachineOperand & MO,int64_t & C)55 static bool isConstant(const MachineOperand &MO, int64_t &C) {
56   const MachineFunction *MF = MO.getParent()->getParent()->getParent();
57   const MachineRegisterInfo &MRI = MF->getRegInfo();
58   const MachineInstr *Def = MRI.getVRegDef(MO.getReg());
59   if (!Def)
60     return false;
61 
62   if (Def->getOpcode() == AMDGPU::G_CONSTANT) {
63     C = Def->getOperand(1).getCImm()->getSExtValue();
64     return true;
65   }
66 
67   if (Def->getOpcode() == AMDGPU::COPY)
68     return isConstant(Def->getOperand(1), C);
69 
70   return false;
71 }
72 
copyCost(const RegisterBank & Dst,const RegisterBank & Src,unsigned Size) const73 unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,
74                                           const RegisterBank &Src,
75                                           unsigned Size) const {
76   if (Dst.getID() == AMDGPU::SGPRRegBankID &&
77       Src.getID() == AMDGPU::VGPRRegBankID)
78     return std::numeric_limits<unsigned>::max();
79 
80   // SGPRRegBank with size 1 is actually vcc or another 64-bit sgpr written by
81   // the valu.
82   if (Size == 1 && Dst.getID() == AMDGPU::SCCRegBankID &&
83       Src.getID() == AMDGPU::SGPRRegBankID)
84     return std::numeric_limits<unsigned>::max();
85 
86   return RegisterBankInfo::copyCost(Dst, Src, Size);
87 }
88 
getRegBankFromRegClass(const TargetRegisterClass & RC) const89 const RegisterBank &AMDGPURegisterBankInfo::getRegBankFromRegClass(
90     const TargetRegisterClass &RC) const {
91 
92   if (TRI->isSGPRClass(&RC))
93     return getRegBank(AMDGPU::SGPRRegBankID);
94 
95   return getRegBank(AMDGPU::VGPRRegBankID);
96 }
97 
98 RegisterBankInfo::InstructionMappings
getInstrAlternativeMappings(const MachineInstr & MI) const99 AMDGPURegisterBankInfo::getInstrAlternativeMappings(
100     const MachineInstr &MI) const {
101 
102   const MachineFunction &MF = *MI.getParent()->getParent();
103   const MachineRegisterInfo &MRI = MF.getRegInfo();
104 
105 
106   InstructionMappings AltMappings;
107   switch (MI.getOpcode()) {
108   case TargetOpcode::G_LOAD: {
109     unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
110     // FIXME: Should we be hard coding the size for these mappings?
111     const InstructionMapping &SSMapping = getInstructionMapping(
112         1, 1, getOperandsMapping(
113                   {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
114                    AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 64)}),
115         2); // Num Operands
116     AltMappings.push_back(&SSMapping);
117 
118     const InstructionMapping &VVMapping = getInstructionMapping(
119         2, 1, getOperandsMapping(
120                   {AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
121                    AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 64)}),
122         2); // Num Operands
123     AltMappings.push_back(&VVMapping);
124 
125     // FIXME: Should this be the pointer-size (64-bits) or the size of the
126     // register that will hold the bufffer resourc (128-bits).
127     const InstructionMapping &VSMapping = getInstructionMapping(
128         3, 1, getOperandsMapping(
129                   {AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
130                    AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 64)}),
131         2); // Num Operands
132     AltMappings.push_back(&VSMapping);
133 
134     return AltMappings;
135 
136   }
137   case TargetOpcode::G_ICMP: {
138     unsigned Size = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI);
139     const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
140       getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1),
141                           nullptr, // Predicate operand.
142                           AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
143                           AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
144       4); // Num Operands
145     AltMappings.push_back(&SSMapping);
146 
147     const InstructionMapping &SVMapping = getInstructionMapping(2, 1,
148       getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
149                           nullptr, // Predicate operand.
150                           AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
151                           AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
152       4); // Num Operands
153     AltMappings.push_back(&SVMapping);
154 
155     const InstructionMapping &VSMapping = getInstructionMapping(3, 1,
156       getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
157                           nullptr, // Predicate operand.
158                           AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
159                           AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
160       4); // Num Operands
161     AltMappings.push_back(&VSMapping);
162 
163     const InstructionMapping &VVMapping = getInstructionMapping(4, 1,
164       getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
165                           nullptr, // Predicate operand.
166                           AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
167                           AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
168       4); // Num Operands
169     AltMappings.push_back(&VVMapping);
170 
171     return AltMappings;
172   }
173   default:
174     break;
175   }
176   return RegisterBankInfo::getInstrAlternativeMappings(MI);
177 }
178 
applyMappingImpl(const OperandsMapper & OpdMapper) const179 void AMDGPURegisterBankInfo::applyMappingImpl(
180     const OperandsMapper &OpdMapper) const {
181   return applyDefaultMapping(OpdMapper);
182 }
183 
isInstrUniform(const MachineInstr & MI)184 static bool isInstrUniform(const MachineInstr &MI) {
185   if (!MI.hasOneMemOperand())
186     return false;
187 
188   const MachineMemOperand *MMO = *MI.memoperands_begin();
189   return AMDGPUInstrInfo::isUniformMMO(MMO);
190 }
191 
isSALUMapping(const MachineInstr & MI) const192 bool AMDGPURegisterBankInfo::isSALUMapping(const MachineInstr &MI) const {
193   const MachineFunction &MF = *MI.getParent()->getParent();
194   const MachineRegisterInfo &MRI = MF.getRegInfo();
195   for (unsigned i = 0, e = MI.getNumOperands();i != e; ++i) {
196     unsigned Reg = MI.getOperand(i).getReg();
197     const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI);
198     if (Bank && Bank->getID() != AMDGPU::SGPRRegBankID)
199       return false;
200   }
201   return true;
202 }
203 
204 const RegisterBankInfo::InstructionMapping &
getDefaultMappingSOP(const MachineInstr & MI) const205 AMDGPURegisterBankInfo::getDefaultMappingSOP(const MachineInstr &MI) const {
206   const MachineFunction &MF = *MI.getParent()->getParent();
207   const MachineRegisterInfo &MRI = MF.getRegInfo();
208   SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
209 
210   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
211     unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
212     OpdsMapping[i] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
213   }
214   return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
215                                MI.getNumOperands());
216 }
217 
218 const RegisterBankInfo::InstructionMapping &
getDefaultMappingVOP(const MachineInstr & MI) const219 AMDGPURegisterBankInfo::getDefaultMappingVOP(const MachineInstr &MI) const {
220   const MachineFunction &MF = *MI.getParent()->getParent();
221   const MachineRegisterInfo &MRI = MF.getRegInfo();
222   SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
223   unsigned OpdIdx = 0;
224 
225   unsigned Size0 = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
226   OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size0);
227 
228   if (MI.getOperand(OpdIdx).isIntrinsicID())
229     OpdsMapping[OpdIdx++] = nullptr;
230 
231   unsigned Reg1 = MI.getOperand(OpdIdx).getReg();
232   unsigned Size1 = getSizeInBits(Reg1, MRI, *TRI);
233   unsigned Bank1 = getRegBankID(Reg1, MRI, *TRI);
234   OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(Bank1, Size1);
235 
236   for (unsigned e = MI.getNumOperands(); OpdIdx != e; ++OpdIdx) {
237     unsigned Size = getSizeInBits(MI.getOperand(OpdIdx).getReg(), MRI, *TRI);
238     OpdsMapping[OpdIdx] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
239   }
240 
241   return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
242                                MI.getNumOperands());
243 }
244 
245 const RegisterBankInfo::InstructionMapping &
getInstrMappingForLoad(const MachineInstr & MI) const246 AMDGPURegisterBankInfo::getInstrMappingForLoad(const MachineInstr &MI) const {
247 
248   const MachineFunction &MF = *MI.getParent()->getParent();
249   const MachineRegisterInfo &MRI = MF.getRegInfo();
250   SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
251   unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
252   unsigned PtrSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
253 
254   const ValueMapping *ValMapping;
255   const ValueMapping *PtrMapping;
256 
257   if (isInstrUniform(MI)) {
258     // We have a uniform instruction so we want to use an SMRD load
259     ValMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
260     PtrMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, PtrSize);
261   } else {
262     ValMapping = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
263     // FIXME: What would happen if we used SGPRRegBankID here?
264     PtrMapping = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, PtrSize);
265   }
266 
267   OpdsMapping[0] = ValMapping;
268   OpdsMapping[1] = PtrMapping;
269   const RegisterBankInfo::InstructionMapping &Mapping = getInstructionMapping(
270       1, 1, getOperandsMapping(OpdsMapping), MI.getNumOperands());
271   return Mapping;
272 
273   // FIXME: Do we want to add a mapping for FLAT load, or should we just
274   // handle that during instruction selection?
275 }
276 
277 unsigned
getRegBankID(unsigned Reg,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,unsigned Default) const278 AMDGPURegisterBankInfo::getRegBankID(unsigned Reg,
279                                      const MachineRegisterInfo &MRI,
280                                      const TargetRegisterInfo &TRI,
281                                      unsigned Default) const {
282 
283   const RegisterBank *Bank = getRegBank(Reg, MRI, TRI);
284   return Bank ? Bank->getID() : Default;
285 }
286 
287 ///
288 /// This function must return a legal mapping, because
289 /// AMDGPURegisterBankInfo::getInstrAlternativeMappings() is not called
290 /// in RegBankSelect::Mode::Fast.  Any mapping that would cause a
291 /// VGPR to SGPR generated is illegal.
292 ///
293 const RegisterBankInfo::InstructionMapping &
getInstrMapping(const MachineInstr & MI) const294 AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
295   const RegisterBankInfo::InstructionMapping &Mapping = getInstrMappingImpl(MI);
296 
297   if (Mapping.isValid())
298     return Mapping;
299 
300   const MachineFunction &MF = *MI.getParent()->getParent();
301   const MachineRegisterInfo &MRI = MF.getRegInfo();
302   SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
303 
304   switch (MI.getOpcode()) {
305   default:
306     return getInvalidInstructionMapping();
307   case AMDGPU::G_ADD:
308   case AMDGPU::G_SUB:
309   case AMDGPU::G_MUL:
310   case AMDGPU::G_AND:
311   case AMDGPU::G_OR:
312   case AMDGPU::G_XOR:
313   case AMDGPU::G_SHL:
314     if (isSALUMapping(MI))
315       return getDefaultMappingSOP(MI);
316     LLVM_FALLTHROUGH;
317 
318   case AMDGPU::G_FADD:
319   case AMDGPU::G_FPTOSI:
320   case AMDGPU::G_FPTOUI:
321   case AMDGPU::G_FMUL:
322     return getDefaultMappingVOP(MI);
323   case AMDGPU::G_IMPLICIT_DEF: {
324     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
325     OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
326     break;
327   }
328   case AMDGPU::G_FCONSTANT:
329   case AMDGPU::G_CONSTANT: {
330     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
331     OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
332     break;
333   }
334   case AMDGPU::G_EXTRACT: {
335     unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
336     unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
337     unsigned SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
338     OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize);
339     OpdsMapping[1] = AMDGPU::getValueMapping(BankID, SrcSize);
340     OpdsMapping[2] = nullptr;
341     break;
342   }
343   case AMDGPU::G_MERGE_VALUES: {
344     unsigned Bank = isSALUMapping(MI) ?
345       AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
346     unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
347     unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
348 
349     OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize);
350     // Op1 and Dst should use the same register bank.
351     for (unsigned i = 1, e = MI.getNumOperands(); i != e; ++i)
352       OpdsMapping[i] = AMDGPU::getValueMapping(Bank, SrcSize);
353     break;
354   }
355   case AMDGPU::G_BITCAST: {
356     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
357     unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
358     OpdsMapping[0] = OpdsMapping[1] = AMDGPU::getValueMapping(BankID, Size);
359     break;
360   }
361   case AMDGPU::G_TRUNC: {
362     unsigned Dst = MI.getOperand(0).getReg();
363     unsigned Src = MI.getOperand(1).getReg();
364     unsigned Bank = getRegBankID(Src, MRI, *TRI);
365     unsigned DstSize = getSizeInBits(Dst, MRI, *TRI);
366     unsigned SrcSize = getSizeInBits(Src, MRI, *TRI);
367     OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize);
368     OpdsMapping[1] = AMDGPU::getValueMapping(Bank, SrcSize);
369     break;
370   }
371   case AMDGPU::G_ZEXT: {
372     unsigned Dst = MI.getOperand(0).getReg();
373     unsigned Src = MI.getOperand(1).getReg();
374     unsigned DstSize = getSizeInBits(Dst, MRI, *TRI);
375     unsigned SrcSize = getSizeInBits(Src, MRI, *TRI);
376     unsigned SrcBank = getRegBankID(Src, MRI, *TRI,
377                                     SrcSize == 1 ? AMDGPU::SGPRRegBankID :
378                                     AMDGPU::VGPRRegBankID);
379     unsigned DstBank = SrcBank;
380     if (SrcSize == 1) {
381       if (SrcBank == AMDGPU::SGPRRegBankID)
382         DstBank = AMDGPU::VGPRRegBankID;
383       else
384         DstBank = AMDGPU::SGPRRegBankID;
385     }
386 
387     OpdsMapping[0] = AMDGPU::getValueMapping(DstBank, DstSize);
388     OpdsMapping[1] = AMDGPU::getValueMapping(SrcBank, SrcSize);
389     break;
390   }
391   case AMDGPU::G_FCMP: {
392     unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
393     unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
394     OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 1);
395     OpdsMapping[1] = nullptr; // Predicate Operand.
396     OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
397     OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
398     break;
399   }
400   case AMDGPU::G_GEP: {
401     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
402       if (!MI.getOperand(i).isReg())
403         continue;
404 
405       unsigned Size = MRI.getType(MI.getOperand(i).getReg()).getSizeInBits();
406       OpdsMapping[i] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
407     }
408     break;
409   }
410   case AMDGPU::G_STORE: {
411     assert(MI.getOperand(0).isReg());
412     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
413     // FIXME: We need to specify a different reg bank once scalar stores
414     // are supported.
415     const ValueMapping *ValMapping =
416         AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
417     // FIXME: Depending on the type of store, the pointer could be in
418     // the SGPR Reg bank.
419     // FIXME: Pointer size should be based on the address space.
420     const ValueMapping *PtrMapping =
421         AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 64);
422 
423     OpdsMapping[0] = ValMapping;
424     OpdsMapping[1] = PtrMapping;
425     break;
426   }
427 
428   case AMDGPU::G_ICMP: {
429     unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
430     unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
431     unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
432     unsigned Op0Bank = Op2Bank == AMDGPU::SGPRRegBankID &&
433                        Op3Bank == AMDGPU::SGPRRegBankID ?
434                        AMDGPU::SCCRegBankID : AMDGPU::VGPRRegBankID;
435     OpdsMapping[0] = AMDGPU::getValueMapping(Op0Bank, 1);
436     OpdsMapping[1] = nullptr; // Predicate Operand.
437     OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
438     OpdsMapping[3] = AMDGPU::getValueMapping(Op3Bank, Size);
439     break;
440   }
441 
442 
443   case AMDGPU::G_EXTRACT_VECTOR_ELT: {
444     unsigned IdxOp = 2;
445     int64_t Imm;
446     // XXX - Do we really need to fully handle these? The constant case should
447     // be legalized away before RegBankSelect?
448 
449     unsigned OutputBankID = isSALUMapping(MI) && isConstant(MI.getOperand(IdxOp), Imm) ?
450                             AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
451 
452     unsigned IdxBank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
453     OpdsMapping[0] = AMDGPU::getValueMapping(OutputBankID, MRI.getType(MI.getOperand(0).getReg()).getSizeInBits());
454     OpdsMapping[1] = AMDGPU::getValueMapping(OutputBankID, MRI.getType(MI.getOperand(1).getReg()).getSizeInBits());
455 
456     // The index can be either if the source vector is VGPR.
457     OpdsMapping[2] = AMDGPU::getValueMapping(IdxBank, MRI.getType(MI.getOperand(2).getReg()).getSizeInBits());
458     break;
459   }
460   case AMDGPU::G_INSERT_VECTOR_ELT: {
461     // XXX - Do we really need to fully handle these? The constant case should
462     // be legalized away before RegBankSelect?
463 
464     int64_t Imm;
465 
466     unsigned IdxOp = MI.getOpcode() == AMDGPU::G_EXTRACT_VECTOR_ELT ? 2 : 3;
467     unsigned BankID = isSALUMapping(MI) && isConstant(MI.getOperand(IdxOp), Imm) ?
468                       AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
469 
470 
471 
472     // TODO: Can do SGPR indexing, which would obviate the need for the
473     // isConstant check.
474     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
475       unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
476       OpdsMapping[i] = AMDGPU::getValueMapping(BankID, Size);
477     }
478 
479 
480     break;
481   }
482   case AMDGPU::G_INTRINSIC: {
483     switch (MI.getOperand(1).getIntrinsicID()) {
484     default:
485       return getInvalidInstructionMapping();
486     case Intrinsic::maxnum:
487     case Intrinsic::minnum:
488     case Intrinsic::amdgcn_cvt_pkrtz:
489       return getDefaultMappingVOP(MI);
490     case Intrinsic::amdgcn_kernarg_segment_ptr: {
491       unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
492       OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
493       break;
494     }
495     }
496     break;
497   }
498   case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
499     switch (MI.getOperand(0).getIntrinsicID()) {
500     default:
501       return getInvalidInstructionMapping();
502     case Intrinsic::amdgcn_exp_compr:
503       OpdsMapping[0] = nullptr; // IntrinsicID
504       // FIXME: These are immediate values which can't be read from registers.
505       OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
506       OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
507       // FIXME: Could we support packed types here?
508       OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
509       OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
510       // FIXME: These are immediate values which can't be read from registers.
511       OpdsMapping[5] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
512       OpdsMapping[6] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
513       break;
514     case Intrinsic::amdgcn_exp:
515       OpdsMapping[0] = nullptr; // IntrinsicID
516       // FIXME: These are immediate values which can't be read from registers.
517       OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
518       OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
519       // FIXME: Could we support packed types here?
520       OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
521       OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
522       OpdsMapping[5] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
523       OpdsMapping[6] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
524       // FIXME: These are immediate values which can't be read from registers.
525       OpdsMapping[7] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
526       OpdsMapping[8] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
527       break;
528     }
529     break;
530   }
531   case AMDGPU::G_LOAD:
532     return getInstrMappingForLoad(MI);
533   }
534 
535   return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
536                                MI.getNumOperands());
537 }
538