1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2008
4 * Texas Instruments, <www.ti.com>
5 *
6 * Author :
7 * Manikandan Pillai <mani.pillai@ti.com>
8 *
9 * Derived from Beagle Board and 3430 SDP code by
10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Syed Mohammed Khasim <khasim@ti.com>
12 */
13
14 #include <common.h>
15 #include <asm/io.h>
16 #include <asm/arch/mem.h> /* get mem tables */
17 #include <asm/arch/sys_proto.h>
18 #include <asm/bootm.h>
19 #include <asm/omap_common.h>
20
21 #include <i2c.h>
22 #include <linux/compiler.h>
23
24 extern omap3_sysinfo sysinfo;
25 static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
26
27 #ifdef CONFIG_DISPLAY_CPUINFO
28 static char *rev_s[CPU_3XX_MAX_REV] = {
29 "1.0",
30 "2.0",
31 "2.1",
32 "3.0",
33 "3.1",
34 "UNKNOWN",
35 "UNKNOWN",
36 "3.1.2"};
37
38 /* this is the revision table for 37xx CPUs */
39 static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
40 "1.0",
41 "1.1",
42 "1.2"};
43 #endif /* CONFIG_DISPLAY_CPUINFO */
44
omap_die_id(unsigned int * die_id)45 void omap_die_id(unsigned int *die_id)
46 {
47 struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
48
49 die_id[0] = readl(&id_base->die_id_0);
50 die_id[1] = readl(&id_base->die_id_1);
51 die_id[2] = readl(&id_base->die_id_2);
52 die_id[3] = readl(&id_base->die_id_3);
53 }
54
55 /******************************************
56 * get_cpu_type(void) - extract cpu info
57 ******************************************/
get_cpu_type(void)58 u32 get_cpu_type(void)
59 {
60 return readl(&ctrl_base->ctrl_omap_stat);
61 }
62
63 /******************************************
64 * get_cpu_id(void) - extract cpu id
65 * returns 0 for ES1.0, cpuid otherwise
66 ******************************************/
get_cpu_id(void)67 u32 get_cpu_id(void)
68 {
69 struct ctrl_id *id_base;
70 u32 cpuid = 0;
71
72 /*
73 * On ES1.0 the IDCODE register is not exposed on L4
74 * so using CPU ID to differentiate between ES1.0 and > ES1.0.
75 */
76 __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
77 if ((cpuid & 0xf) == 0x0) {
78 return 0;
79 } else {
80 /* Decode the IDs on > ES1.0 */
81 id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
82
83 cpuid = readl(&id_base->idcode);
84 }
85
86 return cpuid;
87 }
88
89 /******************************************
90 * get_cpu_family(void) - extract cpu info
91 ******************************************/
get_cpu_family(void)92 u32 get_cpu_family(void)
93 {
94 u16 hawkeye;
95 u32 cpu_family;
96 u32 cpuid = get_cpu_id();
97
98 if (cpuid == 0)
99 return CPU_OMAP34XX;
100
101 hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
102 switch (hawkeye) {
103 case HAWKEYE_OMAP34XX:
104 cpu_family = CPU_OMAP34XX;
105 break;
106 case HAWKEYE_AM35XX:
107 cpu_family = CPU_AM35XX;
108 break;
109 case HAWKEYE_OMAP36XX:
110 cpu_family = CPU_OMAP36XX;
111 break;
112 default:
113 cpu_family = CPU_OMAP34XX;
114 }
115
116 return cpu_family;
117 }
118
119 /******************************************
120 * get_cpu_rev(void) - extract version info
121 ******************************************/
get_cpu_rev(void)122 u32 get_cpu_rev(void)
123 {
124 u32 cpuid = get_cpu_id();
125
126 if (cpuid == 0)
127 return CPU_3XX_ES10;
128 else
129 return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
130 }
131
132 /*****************************************************************
133 * get_sku_id(void) - read sku_id to get info on max clock rate
134 *****************************************************************/
get_sku_id(void)135 u32 get_sku_id(void)
136 {
137 struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
138 return readl(&id_base->sku_id) & SKUID_CLK_MASK;
139 }
140
141 /***************************************************************************
142 * get_gpmc0_base() - Return current address hardware will be
143 * fetching from. The below effectively gives what is correct, its a bit
144 * mis-leading compared to the TRM. For the most general case the mask
145 * needs to be also taken into account this does work in practice.
146 * - for u-boot we currently map:
147 * -- 0 to nothing,
148 * -- 4 to flash
149 * -- 8 to enent
150 * -- c to wifi
151 ****************************************************************************/
get_gpmc0_base(void)152 u32 get_gpmc0_base(void)
153 {
154 u32 b;
155
156 b = readl(&gpmc_cfg->cs[0].config7);
157 b &= 0x1F; /* keep base [5:0] */
158 b = b << 24; /* ret 0x0b000000 */
159 return b;
160 }
161
162 /*******************************************************************
163 * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
164 *******************************************************************/
get_gpmc0_width(void)165 u32 get_gpmc0_width(void)
166 {
167 return WIDTH_16BIT;
168 }
169
170 /*************************************************************************
171 * get_board_rev() - setup to pass kernel board revision information
172 * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
173 *************************************************************************/
174 #ifdef CONFIG_REVISION_TAG
get_board_rev(void)175 u32 __weak get_board_rev(void)
176 {
177 return 0x20;
178 }
179 #endif
180
181 /********************************************************
182 * get_base(); get upper addr of current execution
183 *******************************************************/
get_base(void)184 static u32 get_base(void)
185 {
186 u32 val;
187
188 __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
189 val &= 0xF0000000;
190 val >>= 28;
191 return val;
192 }
193
194 /********************************************************
195 * is_running_in_flash() - tell if currently running in
196 * FLASH.
197 *******************************************************/
is_running_in_flash(void)198 u32 is_running_in_flash(void)
199 {
200 if (get_base() < 4)
201 return 1; /* in FLASH */
202
203 return 0; /* running in SRAM or SDRAM */
204 }
205
206 /********************************************************
207 * is_running_in_sram() - tell if currently running in
208 * SRAM.
209 *******************************************************/
is_running_in_sram(void)210 u32 is_running_in_sram(void)
211 {
212 if (get_base() == 4)
213 return 1; /* in SRAM */
214
215 return 0; /* running in FLASH or SDRAM */
216 }
217
218 /********************************************************
219 * is_running_in_sdram() - tell if currently running in
220 * SDRAM.
221 *******************************************************/
is_running_in_sdram(void)222 u32 is_running_in_sdram(void)
223 {
224 if (get_base() > 4)
225 return 1; /* in SDRAM */
226
227 return 0; /* running in SRAM or FLASH */
228 }
229
230 /***************************************************************
231 * get_boot_type() - Is this an XIP type device or a stream one
232 * bits 4-0 specify type. Bit 5 says mem/perif
233 ***************************************************************/
get_boot_type(void)234 u32 get_boot_type(void)
235 {
236 return (readl(&ctrl_base->status) & SYSBOOT_MASK);
237 }
238
239 #ifdef CONFIG_DISPLAY_CPUINFO
240 /**
241 * Print CPU information
242 */
print_cpuinfo(void)243 int print_cpuinfo (void)
244 {
245 char *cpu_family_s, *cpu_s, *sec_s, *max_clk;
246
247 switch (get_cpu_family()) {
248 case CPU_OMAP34XX:
249 cpu_family_s = "OMAP";
250 switch (get_cpu_type()) {
251 case OMAP3503:
252 cpu_s = "3503";
253 break;
254 case OMAP3515:
255 cpu_s = "3515";
256 break;
257 case OMAP3525:
258 cpu_s = "3525";
259 break;
260 case OMAP3530:
261 cpu_s = "3530";
262 break;
263 default:
264 cpu_s = "35XX";
265 break;
266 }
267 if ((get_cpu_rev() >= CPU_3XX_ES31) &&
268 (get_sku_id() == SKUID_CLK_720MHZ))
269 max_clk = "720 MHz";
270 else
271 max_clk = "600 MHz";
272
273 break;
274 case CPU_AM35XX:
275 cpu_family_s = "AM";
276 switch (get_cpu_type()) {
277 case AM3505:
278 cpu_s = "3505";
279 break;
280 case AM3517:
281 cpu_s = "3517";
282 break;
283 default:
284 cpu_s = "35XX";
285 break;
286 }
287 max_clk = "600 MHz";
288 break;
289 case CPU_OMAP36XX:
290 switch (get_cpu_type()) {
291 case AM3703:
292 cpu_family_s = "AM";
293 cpu_s = "3703";
294 max_clk = "800 MHz";
295 break;
296 case AM3703_1GHZ:
297 cpu_family_s = "AM";
298 cpu_s = "3703";
299 max_clk = "1 GHz";
300 break;
301 case AM3715:
302 cpu_family_s = "AM";
303 cpu_s = "3715";
304 max_clk = "800 MHz";
305 break;
306 case AM3715_1GHZ:
307 cpu_family_s = "AM";
308 cpu_s = "3715";
309 max_clk = "1 GHz";
310 break;
311 case OMAP3725:
312 cpu_family_s = "OMAP";
313 cpu_s = "3625/3725";
314 max_clk = "800 MHz";
315 break;
316 case OMAP3725_1GHZ:
317 cpu_family_s = "OMAP";
318 cpu_s = "3625/3725";
319 max_clk = "1 GHz";
320 break;
321 case OMAP3730:
322 cpu_family_s = "OMAP";
323 cpu_s = "3630/3730";
324 max_clk = "800 MHz";
325 break;
326 case OMAP3730_1GHZ:
327 cpu_family_s = "OMAP";
328 cpu_s = "3630/3730";
329 max_clk = "1 GHz";
330 break;
331 default:
332 cpu_family_s = "OMAP/AM";
333 cpu_s = "36XX/37XX";
334 max_clk = "1 GHz";
335 break;
336 }
337
338 break;
339 default:
340 cpu_family_s = "OMAP";
341 cpu_s = "35XX";
342 max_clk = "600 MHz";
343 }
344
345 switch (get_device_type()) {
346 case TST_DEVICE:
347 sec_s = "TST";
348 break;
349 case EMU_DEVICE:
350 sec_s = "EMU";
351 break;
352 case HS_DEVICE:
353 sec_s = "HS";
354 break;
355 case GP_DEVICE:
356 sec_s = "GP";
357 break;
358 default:
359 sec_s = "?";
360 }
361
362 if (CPU_OMAP36XX == get_cpu_family())
363 printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n",
364 cpu_family_s, cpu_s, sec_s,
365 rev_s_37xx[get_cpu_rev()], max_clk);
366 else
367 printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
368 cpu_family_s, cpu_s, sec_s,
369 rev_s[get_cpu_rev()], max_clk);
370
371 return 0;
372 }
373 #endif /* CONFIG_DISPLAY_CPUINFO */
374