1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "isl_gen8.h"
25 #include "isl_priv.h"
26
27 bool
isl_gen8_choose_msaa_layout(const struct isl_device * dev,const struct isl_surf_init_info * info,enum isl_tiling tiling,enum isl_msaa_layout * msaa_layout)28 isl_gen8_choose_msaa_layout(const struct isl_device *dev,
29 const struct isl_surf_init_info *info,
30 enum isl_tiling tiling,
31 enum isl_msaa_layout *msaa_layout)
32 {
33 bool require_array = false;
34 bool require_interleaved = false;
35
36 assert(info->samples >= 1);
37
38 if (info->samples == 1) {
39 *msaa_layout = ISL_MSAA_LAYOUT_NONE;
40 return true;
41 }
42
43 /* From the Broadwell PRM >> Volume2d: Command Structures >>
44 * RENDER_SURFACE_STATE Multisampled Surface Storage Format:
45 *
46 * All multisampled render target surfaces must have this field set to
47 * MSFMT_MSS
48 */
49 if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
50 require_array = true;
51
52 /* From the Broadwell PRM >> Volume2d: Command Structures >>
53 * RENDER_SURFACE_STATE Number of Multisamples:
54 *
55 * - If this field is any value other than MULTISAMPLECOUNT_1, the
56 * Surface Type must be SURFTYPE_2D This field must be set to
57 * MULTISAMPLECOUNT_1 unless the surface is a Sampling Engine surface
58 * or Render Target surface.
59 *
60 * - If this field is any value other than MULTISAMPLECOUNT_1, Surface
61 * Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero.
62 */
63 if (info->dim != ISL_SURF_DIM_2D)
64 return false;
65 if (info->levels > 1)
66 return false;
67
68 /* More obvious restrictions */
69 if (isl_surf_usage_is_display(info->usage))
70 return false;
71 if (!isl_format_supports_multisampling(dev->info, info->format))
72 return false;
73
74 if (isl_surf_usage_is_depth_or_stencil(info->usage) ||
75 (info->usage & ISL_SURF_USAGE_HIZ_BIT))
76 require_interleaved = true;
77
78 if (require_array && require_interleaved)
79 return false;
80
81 if (require_interleaved) {
82 *msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED;
83 return true;
84 }
85
86 *msaa_layout = ISL_MSAA_LAYOUT_ARRAY;
87 return true;
88 }
89
90 void
isl_gen8_choose_image_alignment_el(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,enum isl_tiling tiling,enum isl_dim_layout dim_layout,enum isl_msaa_layout msaa_layout,struct isl_extent3d * image_align_el)91 isl_gen8_choose_image_alignment_el(const struct isl_device *dev,
92 const struct isl_surf_init_info *restrict info,
93 enum isl_tiling tiling,
94 enum isl_dim_layout dim_layout,
95 enum isl_msaa_layout msaa_layout,
96 struct isl_extent3d *image_align_el)
97 {
98 /* Handled by isl_choose_image_alignment_el */
99 assert(info->format != ISL_FORMAT_HIZ);
100
101 assert(!isl_tiling_is_std_y(tiling));
102
103 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
104 if (fmtl->txc == ISL_TXC_CCS) {
105 /*
106 * Broadwell PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 676):
107 *
108 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
109 * layout with these alignments in the RT space: Horizontal
110 * Alignment = 256 and Vertical Alignment = 128.
111 */
112 *image_align_el = isl_extent3d(256 / fmtl->bw, 128 / fmtl->bh, 1);
113 return;
114 }
115
116 /* From the Broadwell PRM, Volume 4, "Memory Views" p. 186, the alignment
117 * parameters are summarized in the following table:
118 *
119 * Surface Defined By | Surface Format | Align Width | Align Height
120 * --------------------+-----------------+-------------+--------------
121 * DEPTH_BUFFER | D16_UNORM | 8 | 4
122 * | other | 4 | 4
123 * --------------------+-----------------+-------------+--------------
124 * STENCIL_BUFFER | N/A | 8 | 8
125 * --------------------+-----------------+-------------+--------------
126 * SURFACE_STATE | BC*, ETC*, EAC* | 4 | 4
127 * | FXT1 | 8 | 4
128 * | all others | HALIGN | VALIGN
129 * -------------------------------------------------------------------
130 */
131 if (isl_surf_usage_is_depth(info->usage)) {
132 *image_align_el = info->format == ISL_FORMAT_R16_UNORM ?
133 isl_extent3d(8, 4, 1) : isl_extent3d(4, 4, 1);
134 return;
135 } else if (isl_surf_usage_is_stencil(info->usage)) {
136 *image_align_el = isl_extent3d(8, 8, 1);
137 return;
138 } else if (isl_format_is_compressed(info->format)) {
139 /* Compressed formats all have alignment equal to block size. */
140 *image_align_el = isl_extent3d(1, 1, 1);
141 return;
142 }
143
144 /* For all other formats, the alignment is determined by the horizontal and
145 * vertical alignment fields of RENDER_SURFACE_STATE. There are a few
146 * restrictions, but we generally have a choice.
147 */
148
149 /* Vertical alignment is unrestricted so we choose the smallest allowed
150 * alignment because that will use the least memory
151 */
152 const uint32_t valign = 4;
153
154 bool needs_halign16 = false;
155 if (!(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) {
156 /* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
157 * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
158 *
159 * - When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
160 * HALIGN 16 must be used.
161 *
162 * This case handles color surfaces that may own an auxiliary MCS, CCS_D,
163 * or CCS_E. Depth buffers, including those that own an auxiliary HiZ
164 * surface, are handled above and do not require HALIGN_16.
165 */
166 needs_halign16 = true;
167 }
168
169 /* XXX(chadv): I believe the hardware requires each image to be
170 * cache-aligned. If that's true, then defaulting to halign=4 is wrong for
171 * many formats. Depending on the format's block size, we may need to
172 * increase halign to 8.
173 */
174 const uint32_t halign = needs_halign16 ? 16 : 4;
175
176 *image_align_el = isl_extent3d(halign, valign, 1);
177 }
178