1 // Copyright 2017, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 #ifndef VIXL_AARCH32_ASSEMBLER_AARCH32_H_ 28 #define VIXL_AARCH32_ASSEMBLER_AARCH32_H_ 29 30 #include "assembler-base-vixl.h" 31 32 #include "aarch32/instructions-aarch32.h" 33 #include "aarch32/location-aarch32.h" 34 35 namespace vixl { 36 namespace aarch32 { 37 38 class Assembler : public internal::AssemblerBase { 39 InstructionSet isa_; 40 Condition first_condition_; 41 uint16_t it_mask_; 42 bool has_32_dregs_; 43 bool allow_unpredictable_; 44 bool allow_strongly_discouraged_; 45 46 protected: 47 void EmitT32_16(uint16_t instr); 48 void EmitT32_32(uint32_t instr); 49 void EmitA32(uint32_t instr); 50 // Check that the condition of the current instruction is consistent with the 51 // IT state. CheckIT(Condition condition)52 void CheckIT(Condition condition) { 53 #ifdef VIXL_DEBUG 54 PerformCheckIT(condition); 55 #else 56 USE(condition); 57 #endif 58 } 59 #ifdef VIXL_DEBUG 60 void PerformCheckIT(Condition condition); 61 #endif AdvanceIT()62 void AdvanceIT() { 63 first_condition_ = 64 Condition((first_condition_.GetCondition() & 0xe) | (it_mask_ >> 3)); 65 it_mask_ = (it_mask_ << 1) & 0xf; 66 } 67 // Virtual, in order to be overridden by the MacroAssembler, which needs to 68 // notify the pool manager. 69 virtual void BindHelper(Label* label); 70 71 uint32_t Link(uint32_t instr, 72 Location* location, 73 const Location::EmitOperator& op, 74 const ReferenceInfo* info); 75 76 public: 77 class AllowUnpredictableScope { 78 Assembler* assembler_; 79 bool old_; 80 81 public: AllowUnpredictableScope(Assembler * assembler)82 explicit AllowUnpredictableScope(Assembler* assembler) 83 : assembler_(assembler), old_(assembler->allow_unpredictable_) { 84 assembler_->allow_unpredictable_ = true; 85 } ~AllowUnpredictableScope()86 ~AllowUnpredictableScope() { assembler_->allow_unpredictable_ = old_; } 87 }; 88 class AllowStronglyDiscouragedScope { 89 Assembler* assembler_; 90 bool old_; 91 92 public: AllowStronglyDiscouragedScope(Assembler * assembler)93 explicit AllowStronglyDiscouragedScope(Assembler* assembler) 94 : assembler_(assembler), old_(assembler->allow_strongly_discouraged_) { 95 assembler_->allow_strongly_discouraged_ = true; 96 } ~AllowStronglyDiscouragedScope()97 ~AllowStronglyDiscouragedScope() { 98 assembler_->allow_strongly_discouraged_ = old_; 99 } 100 }; 101 102 explicit Assembler(InstructionSet isa = kDefaultISA) isa_(isa)103 : isa_(isa), 104 first_condition_(al), 105 it_mask_(0), 106 has_32_dregs_(true), 107 allow_unpredictable_(false), 108 allow_strongly_discouraged_(false) { 109 #if defined(VIXL_INCLUDE_TARGET_A32_ONLY) 110 // Avoid compiler warning. 111 USE(isa_); 112 VIXL_ASSERT(isa == A32); 113 #elif defined(VIXL_INCLUDE_TARGET_T32_ONLY) 114 USE(isa_); 115 VIXL_ASSERT(isa == T32); 116 #endif 117 } 118 explicit Assembler(size_t capacity, InstructionSet isa = kDefaultISA) AssemblerBase(capacity)119 : AssemblerBase(capacity), 120 isa_(isa), 121 first_condition_(al), 122 it_mask_(0), 123 has_32_dregs_(true), 124 allow_unpredictable_(false), 125 allow_strongly_discouraged_(false) { 126 #if defined(VIXL_INCLUDE_TARGET_A32_ONLY) 127 VIXL_ASSERT(isa == A32); 128 #elif defined(VIXL_INCLUDE_TARGET_T32_ONLY) 129 VIXL_ASSERT(isa == T32); 130 #endif 131 } 132 Assembler(byte* buffer, size_t capacity, InstructionSet isa = kDefaultISA) AssemblerBase(buffer,capacity)133 : AssemblerBase(buffer, capacity), 134 isa_(isa), 135 first_condition_(al), 136 it_mask_(0), 137 has_32_dregs_(true), 138 allow_unpredictable_(false), 139 allow_strongly_discouraged_(false) { 140 #if defined(VIXL_INCLUDE_TARGET_A32_ONLY) 141 VIXL_ASSERT(isa == A32); 142 #elif defined(VIXL_INCLUDE_TARGET_T32_ONLY) 143 VIXL_ASSERT(isa == T32); 144 #endif 145 } ~Assembler()146 virtual ~Assembler() {} 147 UseInstructionSet(InstructionSet isa)148 void UseInstructionSet(InstructionSet isa) { 149 #if defined(VIXL_INCLUDE_TARGET_A32_ONLY) 150 USE(isa); 151 VIXL_ASSERT(isa == A32); 152 #elif defined(VIXL_INCLUDE_TARGET_T32_ONLY) 153 USE(isa); 154 VIXL_ASSERT(isa == T32); 155 #else 156 VIXL_ASSERT((isa_ == isa) || (GetCursorOffset() == 0)); 157 isa_ = isa; 158 #endif 159 } 160 161 #if defined(VIXL_INCLUDE_TARGET_A32_ONLY) GetInstructionSetInUse()162 InstructionSet GetInstructionSetInUse() const { return A32; } 163 #elif defined(VIXL_INCLUDE_TARGET_T32_ONLY) GetInstructionSetInUse()164 InstructionSet GetInstructionSetInUse() const { return T32; } 165 #else GetInstructionSetInUse()166 InstructionSet GetInstructionSetInUse() const { return isa_; } 167 #endif 168 UseT32()169 void UseT32() { UseInstructionSet(T32); } UseA32()170 void UseA32() { UseInstructionSet(A32); } IsUsingT32()171 bool IsUsingT32() const { return GetInstructionSetInUse() == T32; } IsUsingA32()172 bool IsUsingA32() const { return GetInstructionSetInUse() == A32; } 173 SetIT(Condition first_condition,uint16_t it_mask)174 void SetIT(Condition first_condition, uint16_t it_mask) { 175 VIXL_ASSERT(it_mask_ == 0); 176 first_condition_ = first_condition; 177 it_mask_ = it_mask; 178 } InITBlock()179 bool InITBlock() { return it_mask_ != 0; } OutsideITBlock()180 bool OutsideITBlock() { return it_mask_ == 0; } OutsideITBlockOrLast()181 bool OutsideITBlockOrLast() { return (it_mask_ == 0) || (it_mask_ == 0x8); } OutsideITBlockAndAlOrLast(Condition cond)182 bool OutsideITBlockAndAlOrLast(Condition cond) { 183 return ((it_mask_ == 0) && cond.Is(al)) || (it_mask_ == 0x8); 184 } CheckNotIT()185 void CheckNotIT() { VIXL_ASSERT(it_mask_ == 0); } Has32DRegs()186 bool Has32DRegs() const { return has_32_dregs_; } SetHas32DRegs(bool has_32_dregs)187 void SetHas32DRegs(bool has_32_dregs) { has_32_dregs_ = has_32_dregs; } 188 GetCursorOffset()189 int32_t GetCursorOffset() const { 190 ptrdiff_t offset = buffer_.GetCursorOffset(); 191 VIXL_ASSERT(IsInt32(offset)); 192 return static_cast<int32_t>(offset); 193 } 194 GetArchitectureStatePCOffset()195 uint32_t GetArchitectureStatePCOffset() const { return IsUsingT32() ? 4 : 8; } 196 197 // Bind a raw Location that will never be tracked by the pool manager. bind(Location * location)198 void bind(Location* location) { 199 VIXL_ASSERT(AllowAssembler()); 200 VIXL_ASSERT(!location->IsBound()); 201 location->SetLocation(this, GetCursorOffset()); 202 location->MarkBound(); 203 } 204 205 // Bind a Label, which may be tracked by the pool manager in the presence of a 206 // MacroAssembler. bind(Label * label)207 void bind(Label* label) { 208 VIXL_ASSERT(AllowAssembler()); 209 BindHelper(label); 210 } 211 place(RawLiteral * literal)212 void place(RawLiteral* literal) { 213 VIXL_ASSERT(AllowAssembler()); 214 VIXL_ASSERT(literal->IsManuallyPlaced()); 215 literal->SetLocation(this, GetCursorOffset()); 216 literal->MarkBound(); 217 GetBuffer()->EnsureSpaceFor(literal->GetSize()); 218 GetBuffer()->EmitData(literal->GetDataAddress(), literal->GetSize()); 219 } 220 GetSizeOfCodeGeneratedSince(Label * label)221 size_t GetSizeOfCodeGeneratedSince(Label* label) const { 222 VIXL_ASSERT(label->IsBound()); 223 return buffer_.GetOffsetFrom(label->GetLocation()); 224 } 225 226 // Helpers for it instruction. it(Condition cond)227 void it(Condition cond) { it(cond, 0x8); } itt(Condition cond)228 void itt(Condition cond) { it(cond, 0x4); } ite(Condition cond)229 void ite(Condition cond) { it(cond, 0xc); } ittt(Condition cond)230 void ittt(Condition cond) { it(cond, 0x2); } itet(Condition cond)231 void itet(Condition cond) { it(cond, 0xa); } itte(Condition cond)232 void itte(Condition cond) { it(cond, 0x6); } itee(Condition cond)233 void itee(Condition cond) { it(cond, 0xe); } itttt(Condition cond)234 void itttt(Condition cond) { it(cond, 0x1); } itett(Condition cond)235 void itett(Condition cond) { it(cond, 0x9); } ittet(Condition cond)236 void ittet(Condition cond) { it(cond, 0x5); } iteet(Condition cond)237 void iteet(Condition cond) { it(cond, 0xd); } ittte(Condition cond)238 void ittte(Condition cond) { it(cond, 0x3); } itete(Condition cond)239 void itete(Condition cond) { it(cond, 0xb); } ittee(Condition cond)240 void ittee(Condition cond) { it(cond, 0x7); } iteee(Condition cond)241 void iteee(Condition cond) { it(cond, 0xf); } 242 243 // Start of generated code. 244 typedef void (Assembler::*InstructionCondSizeRROp)(Condition cond, 245 EncodingSize size, 246 Register rd, 247 Register rn, 248 const Operand& operand); 249 typedef void (Assembler::*InstructionCondROp)(Condition cond, 250 Register rd, 251 const Operand& operand); 252 typedef void (Assembler::*InstructionROp)(Register rd, 253 const Operand& operand); 254 typedef void (Assembler::*InstructionCondRROp)(Condition cond, 255 Register rd, 256 Register rn, 257 const Operand& operand); 258 typedef void (Assembler::*InstructionCondSizeRL)(Condition cond, 259 EncodingSize size, 260 Register rd, 261 Location* location); 262 typedef void (Assembler::*InstructionDtQQ)(DataType dt, 263 QRegister rd, 264 QRegister rm); 265 typedef void (Assembler::*InstructionCondSizeL)(Condition cond, 266 EncodingSize size, 267 Location* location); 268 typedef void (Assembler::*InstructionCondRII)(Condition cond, 269 Register rd, 270 uint32_t lsb, 271 uint32_t width); 272 typedef void (Assembler::*InstructionCondRRII)( 273 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width); 274 typedef void (Assembler::*InstructionCondI)(Condition cond, uint32_t imm); 275 typedef void (Assembler::*InstructionCondL)(Condition cond, 276 Location* location); 277 typedef void (Assembler::*InstructionCondR)(Condition cond, Register rm); 278 typedef void (Assembler::*InstructionRL)(Register rn, Location* location); 279 typedef void (Assembler::*InstructionCond)(Condition cond); 280 typedef void (Assembler::*InstructionCondRR)(Condition cond, 281 Register rd, 282 Register rm); 283 typedef void (Assembler::*InstructionCondSizeROp)(Condition cond, 284 EncodingSize size, 285 Register rn, 286 const Operand& operand); 287 typedef void (Assembler::*InstructionCondRRR)(Condition cond, 288 Register rd, 289 Register rn, 290 Register rm); 291 typedef void (Assembler::*InstructionCondBa)(Condition cond, 292 MemoryBarrier option); 293 typedef void (Assembler::*InstructionCondRwbDrl)(Condition cond, 294 Register rn, 295 WriteBack write_back, 296 DRegisterList dreglist); 297 typedef void (Assembler::*InstructionCondRMop)(Condition cond, 298 Register rt, 299 const MemOperand& operand); 300 typedef void (Assembler::*InstructionCondRRMop)(Condition cond, 301 Register rt, 302 Register rt2, 303 const MemOperand& operand); 304 typedef void (Assembler::*InstructionCondSizeRwbRl)(Condition cond, 305 EncodingSize size, 306 Register rn, 307 WriteBack write_back, 308 RegisterList registers); 309 typedef void (Assembler::*InstructionCondRwbRl)(Condition cond, 310 Register rn, 311 WriteBack write_back, 312 RegisterList registers); 313 typedef void (Assembler::*InstructionCondSizeRMop)(Condition cond, 314 EncodingSize size, 315 Register rt, 316 const MemOperand& operand); 317 typedef void (Assembler::*InstructionCondRL)(Condition cond, 318 Register rt, 319 Location* location); 320 typedef void (Assembler::*InstructionCondRRL)(Condition cond, 321 Register rt, 322 Register rt2, 323 Location* location); 324 typedef void (Assembler::*InstructionCondRRRR)( 325 Condition cond, Register rd, Register rn, Register rm, Register ra); 326 typedef void (Assembler::*InstructionCondRSr)(Condition cond, 327 Register rd, 328 SpecialRegister spec_reg); 329 typedef void (Assembler::*InstructionCondMsrOp)( 330 Condition cond, MaskedSpecialRegister spec_reg, const Operand& operand); 331 typedef void (Assembler::*InstructionCondSizeRRR)( 332 Condition cond, EncodingSize size, Register rd, Register rn, Register rm); 333 typedef void (Assembler::*InstructionCondSize)(Condition cond, 334 EncodingSize size); 335 typedef void (Assembler::*InstructionCondMop)(Condition cond, 336 const MemOperand& operand); 337 typedef void (Assembler::*InstructionCondSizeRl)(Condition cond, 338 EncodingSize size, 339 RegisterList registers); 340 typedef void (Assembler::*InstructionCondSizeOrl)(Condition cond, 341 EncodingSize size, 342 Register rt); 343 typedef void (Assembler::*InstructionCondSizeRR)(Condition cond, 344 EncodingSize size, 345 Register rd, 346 Register rm); 347 typedef void (Assembler::*InstructionDtQQQ)(DataType dt, 348 QRegister rd, 349 QRegister rn, 350 QRegister rm); 351 typedef void (Assembler::*InstructionCondRIOp)(Condition cond, 352 Register rd, 353 uint32_t imm, 354 const Operand& operand); 355 typedef void (Assembler::*InstructionCondRIR)(Condition cond, 356 Register rd, 357 uint32_t imm, 358 Register rn); 359 typedef void (Assembler::*InstructionCondRRRMop)(Condition cond, 360 Register rd, 361 Register rt, 362 Register rt2, 363 const MemOperand& operand); 364 typedef void (Assembler::*InstructionCondSizeI)(Condition cond, 365 EncodingSize size, 366 uint32_t imm); 367 typedef void (Assembler::*InstructionCondDtDDD)( 368 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 369 typedef void (Assembler::*InstructionCondDtQQQ)( 370 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 371 typedef void (Assembler::*InstructionCondDtQDD)( 372 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 373 typedef void (Assembler::*InstructionCondDtDD)(Condition cond, 374 DataType dt, 375 DRegister rd, 376 DRegister rm); 377 typedef void (Assembler::*InstructionCondDtQQ)(Condition cond, 378 DataType dt, 379 QRegister rd, 380 QRegister rm); 381 typedef void (Assembler::*InstructionCondDtSS)(Condition cond, 382 DataType dt, 383 SRegister rd, 384 SRegister rm); 385 typedef void (Assembler::*InstructionCondDtSSS)( 386 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 387 typedef void (Assembler::*InstructionCondDtDQQ)( 388 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 389 typedef void (Assembler::*InstructionCondDtQQD)( 390 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm); 391 typedef void (Assembler::*InstructionCondDtDDDop)(Condition cond, 392 DataType dt, 393 DRegister rd, 394 DRegister rn, 395 const DOperand& operand); 396 typedef void (Assembler::*InstructionCondDtQQQop)(Condition cond, 397 DataType dt, 398 QRegister rd, 399 QRegister rn, 400 const QOperand& operand); 401 typedef void (Assembler::*InstructionCondDtSSop)(Condition cond, 402 DataType dt, 403 SRegister rd, 404 const SOperand& operand); 405 typedef void (Assembler::*InstructionCondDtDDop)(Condition cond, 406 DataType dt, 407 DRegister rd, 408 const DOperand& operand); 409 typedef void (Assembler::*InstructionCondDtDtDS)( 410 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm); 411 typedef void (Assembler::*InstructionCondDtDtSD)( 412 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 413 typedef void (Assembler::*InstructionCondDtDtDDSi)(Condition cond, 414 DataType dt1, 415 DataType dt2, 416 DRegister rd, 417 DRegister rm, 418 int32_t fbits); 419 typedef void (Assembler::*InstructionCondDtDtQQSi)(Condition cond, 420 DataType dt1, 421 DataType dt2, 422 QRegister rd, 423 QRegister rm, 424 int32_t fbits); 425 typedef void (Assembler::*InstructionCondDtDtSSSi)(Condition cond, 426 DataType dt1, 427 DataType dt2, 428 SRegister rd, 429 SRegister rm, 430 int32_t fbits); 431 typedef void (Assembler::*InstructionCondDtDtDD)( 432 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm); 433 typedef void (Assembler::*InstructionCondDtDtQQ)( 434 Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm); 435 typedef void (Assembler::*InstructionCondDtDtDQ)( 436 Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm); 437 typedef void (Assembler::*InstructionCondDtDtQD)( 438 Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm); 439 typedef void (Assembler::*InstructionCondDtDtSS)( 440 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 441 typedef void (Assembler::*InstructionDtDtDD)(DataType dt1, 442 DataType dt2, 443 DRegister rd, 444 DRegister rm); 445 typedef void (Assembler::*InstructionDtDtQQ)(DataType dt1, 446 DataType dt2, 447 QRegister rd, 448 QRegister rm); 449 typedef void (Assembler::*InstructionDtDtSS)(DataType dt1, 450 DataType dt2, 451 SRegister rd, 452 SRegister rm); 453 typedef void (Assembler::*InstructionDtDtSD)(DataType dt1, 454 DataType dt2, 455 SRegister rd, 456 DRegister rm); 457 typedef void (Assembler::*InstructionCondDtQR)(Condition cond, 458 DataType dt, 459 QRegister rd, 460 Register rt); 461 typedef void (Assembler::*InstructionCondDtDR)(Condition cond, 462 DataType dt, 463 DRegister rd, 464 Register rt); 465 typedef void (Assembler::*InstructionCondDtDDx)(Condition cond, 466 DataType dt, 467 DRegister rd, 468 DRegisterLane rm); 469 typedef void (Assembler::*InstructionCondDtQDx)(Condition cond, 470 DataType dt, 471 QRegister rd, 472 DRegisterLane rm); 473 typedef void (Assembler::*InstructionCondDtDDDDop)(Condition cond, 474 DataType dt, 475 DRegister rd, 476 DRegister rn, 477 DRegister rm, 478 const DOperand& operand); 479 typedef void (Assembler::*InstructionCondDtQQQQop)(Condition cond, 480 DataType dt, 481 QRegister rd, 482 QRegister rn, 483 QRegister rm, 484 const QOperand& operand); 485 typedef void (Assembler::*InstructionCondDtNrlAmop)( 486 Condition cond, 487 DataType dt, 488 const NeonRegisterList& nreglist, 489 const AlignedMemOperand& operand); 490 typedef void (Assembler::*InstructionCondDtNrlMop)( 491 Condition cond, 492 DataType dt, 493 const NeonRegisterList& nreglist, 494 const MemOperand& operand); 495 typedef void (Assembler::*InstructionCondDtRwbDrl)(Condition cond, 496 DataType dt, 497 Register rn, 498 WriteBack write_back, 499 DRegisterList dreglist); 500 typedef void (Assembler::*InstructionCondDtRwbSrl)(Condition cond, 501 DataType dt, 502 Register rn, 503 WriteBack write_back, 504 SRegisterList sreglist); 505 typedef void (Assembler::*InstructionCondDtDL)(Condition cond, 506 DataType dt, 507 DRegister rd, 508 Location* location); 509 typedef void (Assembler::*InstructionCondDtDMop)(Condition cond, 510 DataType dt, 511 DRegister rd, 512 const MemOperand& operand); 513 typedef void (Assembler::*InstructionCondDtSL)(Condition cond, 514 DataType dt, 515 SRegister rd, 516 Location* location); 517 typedef void (Assembler::*InstructionCondDtSMop)(Condition cond, 518 DataType dt, 519 SRegister rd, 520 const MemOperand& operand); 521 typedef void (Assembler::*InstructionDtDDD)(DataType dt, 522 DRegister rd, 523 DRegister rn, 524 DRegister rm); 525 typedef void (Assembler::*InstructionDtSSS)(DataType dt, 526 SRegister rd, 527 SRegister rn, 528 SRegister rm); 529 typedef void (Assembler::*InstructionCondDtDDDx)(Condition cond, 530 DataType dt, 531 DRegister rd, 532 DRegister rn, 533 DRegisterLane rm); 534 typedef void (Assembler::*InstructionCondDtQQDx)(Condition cond, 535 DataType dt, 536 QRegister rd, 537 QRegister rn, 538 DRegisterLane rm); 539 typedef void (Assembler::*InstructionCondDtQDDx)(Condition cond, 540 DataType dt, 541 QRegister rd, 542 DRegister rn, 543 DRegisterLane rm); 544 typedef void (Assembler::*InstructionCondRS)(Condition cond, 545 Register rt, 546 SRegister rn); 547 typedef void (Assembler::*InstructionCondSR)(Condition cond, 548 SRegister rn, 549 Register rt); 550 typedef void (Assembler::*InstructionCondRRD)(Condition cond, 551 Register rt, 552 Register rt2, 553 DRegister rm); 554 typedef void (Assembler::*InstructionCondDRR)(Condition cond, 555 DRegister rm, 556 Register rt, 557 Register rt2); 558 typedef void (Assembler::*InstructionCondRRSS)( 559 Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1); 560 typedef void (Assembler::*InstructionCondSSRR)( 561 Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2); 562 typedef void (Assembler::*InstructionCondDtDxR)(Condition cond, 563 DataType dt, 564 DRegisterLane rd, 565 Register rt); 566 typedef void (Assembler::*InstructionCondDtQQop)(Condition cond, 567 DataType dt, 568 QRegister rd, 569 const QOperand& operand); 570 typedef void (Assembler::*InstructionCondDtRDx)(Condition cond, 571 DataType dt, 572 Register rt, 573 DRegisterLane rn); 574 typedef void (Assembler::*InstructionCondDtQD)(Condition cond, 575 DataType dt, 576 QRegister rd, 577 DRegister rm); 578 typedef void (Assembler::*InstructionCondDtDQ)(Condition cond, 579 DataType dt, 580 DRegister rd, 581 QRegister rm); 582 typedef void (Assembler::*InstructionCondRoaSfp)(Condition cond, 583 RegisterOrAPSR_nzcv rt, 584 SpecialFPRegister spec_reg); 585 typedef void (Assembler::*InstructionCondSfpR)(Condition cond, 586 SpecialFPRegister spec_reg, 587 Register rt); 588 typedef void (Assembler::*InstructionCondDtDDIr)(Condition cond, 589 DataType dt, 590 DRegister rd, 591 DRegister rn, 592 DRegister dm, 593 unsigned index); 594 typedef void (Assembler::*InstructionCondDtQQIr)(Condition cond, 595 DataType dt, 596 QRegister rd, 597 QRegister rn, 598 DRegister dm, 599 unsigned index); 600 typedef void (Assembler::*InstructionCondDtQDIr)(Condition cond, 601 DataType dt, 602 QRegister rd, 603 DRegister rn, 604 DRegister dm, 605 unsigned index); 606 typedef void (Assembler::*InstructionCondDtDrl)(Condition cond, 607 DataType dt, 608 DRegisterList dreglist); 609 typedef void (Assembler::*InstructionCondDtSrl)(Condition cond, 610 DataType dt, 611 SRegisterList sreglist); 612 typedef void (Assembler::*InstructionCondDtDQQop)(Condition cond, 613 DataType dt, 614 DRegister rd, 615 QRegister rm, 616 const QOperand& operand); 617 typedef void (Assembler::*InstructionDtDD)(DataType dt, 618 DRegister rd, 619 DRegister rm); 620 typedef void (Assembler::*InstructionDtSS)(DataType dt, 621 SRegister rd, 622 SRegister rm); 623 typedef void (Assembler::*InstructionCondDtQDDop)(Condition cond, 624 DataType dt, 625 QRegister rd, 626 DRegister rm, 627 const DOperand& operand); 628 typedef void (Assembler::*InstructionCondDtDNrlD)( 629 Condition cond, 630 DataType dt, 631 DRegister rd, 632 const NeonRegisterList& nreglist, 633 DRegister rm); Delegate(InstructionType type,InstructionCondSizeRROp,Condition,EncodingSize,Register,Register,const Operand &)634 virtual void Delegate(InstructionType type, 635 InstructionCondSizeRROp /*instruction*/, 636 Condition /*cond*/, 637 EncodingSize /*size*/, 638 Register /*rd*/, 639 Register /*rn*/, 640 const Operand& /*operand*/) { 641 USE(type); 642 VIXL_ASSERT((type == kAdc) || (type == kAdcs) || (type == kAdd) || 643 (type == kAdds) || (type == kAnd) || (type == kAnds) || 644 (type == kAsr) || (type == kAsrs) || (type == kBic) || 645 (type == kBics) || (type == kEor) || (type == kEors) || 646 (type == kLsl) || (type == kLsls) || (type == kLsr) || 647 (type == kLsrs) || (type == kOrr) || (type == kOrrs) || 648 (type == kRor) || (type == kRors) || (type == kRsb) || 649 (type == kRsbs) || (type == kSbc) || (type == kSbcs) || 650 (type == kSub) || (type == kSubs)); 651 UnimplementedDelegate(type); 652 } Delegate(InstructionType type,InstructionCondROp,Condition,Register,const Operand &)653 virtual void Delegate(InstructionType type, 654 InstructionCondROp /*instruction*/, 655 Condition /*cond*/, 656 Register /*rd*/, 657 const Operand& /*operand*/) { 658 USE(type); 659 VIXL_ASSERT((type == kAdd) || (type == kMovt) || (type == kMovw) || 660 (type == kSub) || (type == kSxtb16) || (type == kTeq) || 661 (type == kUxtb16)); 662 UnimplementedDelegate(type); 663 } Delegate(InstructionType type,InstructionROp,Register,const Operand &)664 virtual void Delegate(InstructionType type, 665 InstructionROp /*instruction*/, 666 Register /*rd*/, 667 const Operand& /*operand*/) { 668 USE(type); 669 VIXL_ASSERT((type == kAdds) || (type == kSubs)); 670 UnimplementedDelegate(type); 671 } Delegate(InstructionType type,InstructionCondRROp,Condition,Register,Register,const Operand &)672 virtual void Delegate(InstructionType type, 673 InstructionCondRROp /*instruction*/, 674 Condition /*cond*/, 675 Register /*rd*/, 676 Register /*rn*/, 677 const Operand& /*operand*/) { 678 USE(type); 679 VIXL_ASSERT((type == kAddw) || (type == kOrn) || (type == kOrns) || 680 (type == kPkhbt) || (type == kPkhtb) || (type == kRsc) || 681 (type == kRscs) || (type == kSubw) || (type == kSxtab) || 682 (type == kSxtab16) || (type == kSxtah) || (type == kUxtab) || 683 (type == kUxtab16) || (type == kUxtah)); 684 UnimplementedDelegate(type); 685 } Delegate(InstructionType type,InstructionCondSizeRL,Condition,EncodingSize,Register,Location *)686 virtual void Delegate(InstructionType type, 687 InstructionCondSizeRL /*instruction*/, 688 Condition /*cond*/, 689 EncodingSize /*size*/, 690 Register /*rd*/, 691 Location* /*location*/) { 692 USE(type); 693 VIXL_ASSERT((type == kAdr) || (type == kLdr)); 694 UnimplementedDelegate(type); 695 } Delegate(InstructionType type,InstructionDtQQ,DataType,QRegister,QRegister)696 virtual void Delegate(InstructionType type, 697 InstructionDtQQ /*instruction*/, 698 DataType /*dt*/, 699 QRegister /*rd*/, 700 QRegister /*rm*/) { 701 USE(type); 702 VIXL_ASSERT((type == kVrinta) || (type == kVrintm) || (type == kVrintn) || 703 (type == kVrintp) || (type == kVrintx) || (type == kVrintz)); 704 UnimplementedDelegate(type); 705 } Delegate(InstructionType type,InstructionCondSizeL,Condition,EncodingSize,Location *)706 virtual void Delegate(InstructionType type, 707 InstructionCondSizeL /*instruction*/, 708 Condition /*cond*/, 709 EncodingSize /*size*/, 710 Location* /*location*/) { 711 USE(type); 712 VIXL_ASSERT((type == kB)); 713 UnimplementedDelegate(type); 714 } Delegate(InstructionType type,InstructionCondRII,Condition,Register,uint32_t,uint32_t)715 virtual void Delegate(InstructionType type, 716 InstructionCondRII /*instruction*/, 717 Condition /*cond*/, 718 Register /*rd*/, 719 uint32_t /*lsb*/, 720 uint32_t /*width*/) { 721 USE(type); 722 VIXL_ASSERT((type == kBfc)); 723 UnimplementedDelegate(type); 724 } Delegate(InstructionType type,InstructionCondRRII,Condition,Register,Register,uint32_t,uint32_t)725 virtual void Delegate(InstructionType type, 726 InstructionCondRRII /*instruction*/, 727 Condition /*cond*/, 728 Register /*rd*/, 729 Register /*rn*/, 730 uint32_t /*lsb*/, 731 uint32_t /*width*/) { 732 USE(type); 733 VIXL_ASSERT((type == kBfi) || (type == kSbfx) || (type == kUbfx)); 734 UnimplementedDelegate(type); 735 } Delegate(InstructionType type,InstructionCondI,Condition,uint32_t)736 virtual void Delegate(InstructionType type, 737 InstructionCondI /*instruction*/, 738 Condition /*cond*/, 739 uint32_t /*imm*/) { 740 USE(type); 741 VIXL_ASSERT((type == kBkpt) || (type == kHlt) || (type == kHvc) || 742 (type == kSvc)); 743 UnimplementedDelegate(type); 744 } Delegate(InstructionType type,InstructionCondL,Condition,Location *)745 virtual void Delegate(InstructionType type, 746 InstructionCondL /*instruction*/, 747 Condition /*cond*/, 748 Location* /*location*/) { 749 USE(type); 750 VIXL_ASSERT((type == kBl) || (type == kBlx) || (type == kPld) || 751 (type == kPli)); 752 UnimplementedDelegate(type); 753 } Delegate(InstructionType type,InstructionCondR,Condition,Register)754 virtual void Delegate(InstructionType type, 755 InstructionCondR /*instruction*/, 756 Condition /*cond*/, 757 Register /*rm*/) { 758 USE(type); 759 VIXL_ASSERT((type == kBlx) || (type == kBx) || (type == kBxj)); 760 UnimplementedDelegate(type); 761 } Delegate(InstructionType type,InstructionRL,Register,Location *)762 virtual void Delegate(InstructionType type, 763 InstructionRL /*instruction*/, 764 Register /*rn*/, 765 Location* /*location*/) { 766 USE(type); 767 VIXL_ASSERT((type == kCbnz) || (type == kCbz)); 768 UnimplementedDelegate(type); 769 } Delegate(InstructionType type,InstructionCond,Condition)770 virtual void Delegate(InstructionType type, 771 InstructionCond /*instruction*/, 772 Condition /*cond*/) { 773 USE(type); 774 VIXL_ASSERT((type == kClrex)); 775 UnimplementedDelegate(type); 776 } Delegate(InstructionType type,InstructionCondRR,Condition,Register,Register)777 virtual void Delegate(InstructionType type, 778 InstructionCondRR /*instruction*/, 779 Condition /*cond*/, 780 Register /*rd*/, 781 Register /*rm*/) { 782 USE(type); 783 VIXL_ASSERT((type == kClz) || (type == kRbit) || (type == kRrx) || 784 (type == kRrxs)); 785 UnimplementedDelegate(type); 786 } Delegate(InstructionType type,InstructionCondSizeROp,Condition,EncodingSize,Register,const Operand &)787 virtual void Delegate(InstructionType type, 788 InstructionCondSizeROp /*instruction*/, 789 Condition /*cond*/, 790 EncodingSize /*size*/, 791 Register /*rn*/, 792 const Operand& /*operand*/) { 793 USE(type); 794 VIXL_ASSERT((type == kCmn) || (type == kCmp) || (type == kMov) || 795 (type == kMovs) || (type == kMvn) || (type == kMvns) || 796 (type == kSxtb) || (type == kSxth) || (type == kTst) || 797 (type == kUxtb) || (type == kUxth)); 798 UnimplementedDelegate(type); 799 } Delegate(InstructionType type,InstructionCondRRR,Condition,Register,Register,Register)800 virtual void Delegate(InstructionType type, 801 InstructionCondRRR /*instruction*/, 802 Condition /*cond*/, 803 Register /*rd*/, 804 Register /*rn*/, 805 Register /*rm*/) { 806 USE(type); 807 VIXL_ASSERT((type == kCrc32b) || (type == kCrc32cb) || (type == kCrc32ch) || 808 (type == kCrc32cw) || (type == kCrc32h) || (type == kCrc32w) || 809 (type == kMuls) || (type == kQadd) || (type == kQadd16) || 810 (type == kQadd8) || (type == kQasx) || (type == kQdadd) || 811 (type == kQdsub) || (type == kQsax) || (type == kQsub) || 812 (type == kQsub16) || (type == kQsub8) || (type == kSadd16) || 813 (type == kSadd8) || (type == kSasx) || (type == kSdiv) || 814 (type == kSel) || (type == kShadd16) || (type == kShadd8) || 815 (type == kShasx) || (type == kShsax) || (type == kShsub16) || 816 (type == kShsub8) || (type == kSmmul) || (type == kSmmulr) || 817 (type == kSmuad) || (type == kSmuadx) || (type == kSmulbb) || 818 (type == kSmulbt) || (type == kSmultb) || (type == kSmultt) || 819 (type == kSmulwb) || (type == kSmulwt) || (type == kSmusd) || 820 (type == kSmusdx) || (type == kSsax) || (type == kSsub16) || 821 (type == kSsub8) || (type == kUadd16) || (type == kUadd8) || 822 (type == kUasx) || (type == kUdiv) || (type == kUhadd16) || 823 (type == kUhadd8) || (type == kUhasx) || (type == kUhsax) || 824 (type == kUhsub16) || (type == kUhsub8) || (type == kUqadd16) || 825 (type == kUqadd8) || (type == kUqasx) || (type == kUqsax) || 826 (type == kUqsub16) || (type == kUqsub8) || (type == kUsad8) || 827 (type == kUsax) || (type == kUsub16) || (type == kUsub8)); 828 UnimplementedDelegate(type); 829 } Delegate(InstructionType type,InstructionCondBa,Condition,MemoryBarrier)830 virtual void Delegate(InstructionType type, 831 InstructionCondBa /*instruction*/, 832 Condition /*cond*/, 833 MemoryBarrier /*option*/) { 834 USE(type); 835 VIXL_ASSERT((type == kDmb) || (type == kDsb) || (type == kIsb)); 836 UnimplementedDelegate(type); 837 } Delegate(InstructionType type,InstructionCondRwbDrl,Condition,Register,WriteBack,DRegisterList)838 virtual void Delegate(InstructionType type, 839 InstructionCondRwbDrl /*instruction*/, 840 Condition /*cond*/, 841 Register /*rn*/, 842 WriteBack /*write_back*/, 843 DRegisterList /*dreglist*/) { 844 USE(type); 845 VIXL_ASSERT((type == kFldmdbx) || (type == kFldmiax) || 846 (type == kFstmdbx) || (type == kFstmiax)); 847 UnimplementedDelegate(type); 848 } DelegateIt(Condition,uint16_t)849 virtual void DelegateIt(Condition /*cond*/, uint16_t /*mask*/) { 850 UnimplementedDelegate(kIt); 851 } Delegate(InstructionType type,InstructionCondRMop,Condition,Register,const MemOperand &)852 virtual void Delegate(InstructionType type, 853 InstructionCondRMop /*instruction*/, 854 Condition /*cond*/, 855 Register /*rt*/, 856 const MemOperand& /*operand*/) { 857 USE(type); 858 VIXL_ASSERT((type == kLda) || (type == kLdab) || (type == kLdaex) || 859 (type == kLdaexb) || (type == kLdaexh) || (type == kLdah) || 860 (type == kLdrex) || (type == kLdrexb) || (type == kLdrexh) || 861 (type == kStl) || (type == kStlb) || (type == kStlh)); 862 UnimplementedDelegate(type); 863 } Delegate(InstructionType type,InstructionCondRRMop,Condition,Register,Register,const MemOperand &)864 virtual void Delegate(InstructionType type, 865 InstructionCondRRMop /*instruction*/, 866 Condition /*cond*/, 867 Register /*rt*/, 868 Register /*rt2*/, 869 const MemOperand& /*operand*/) { 870 USE(type); 871 VIXL_ASSERT((type == kLdaexd) || (type == kLdrd) || (type == kLdrexd) || 872 (type == kStlex) || (type == kStlexb) || (type == kStlexh) || 873 (type == kStrd) || (type == kStrex) || (type == kStrexb) || 874 (type == kStrexh)); 875 UnimplementedDelegate(type); 876 } Delegate(InstructionType type,InstructionCondSizeRwbRl,Condition,EncodingSize,Register,WriteBack,RegisterList)877 virtual void Delegate(InstructionType type, 878 InstructionCondSizeRwbRl /*instruction*/, 879 Condition /*cond*/, 880 EncodingSize /*size*/, 881 Register /*rn*/, 882 WriteBack /*write_back*/, 883 RegisterList /*registers*/) { 884 USE(type); 885 VIXL_ASSERT((type == kLdm) || (type == kLdmfd) || (type == kStm) || 886 (type == kStmdb) || (type == kStmea)); 887 UnimplementedDelegate(type); 888 } Delegate(InstructionType type,InstructionCondRwbRl,Condition,Register,WriteBack,RegisterList)889 virtual void Delegate(InstructionType type, 890 InstructionCondRwbRl /*instruction*/, 891 Condition /*cond*/, 892 Register /*rn*/, 893 WriteBack /*write_back*/, 894 RegisterList /*registers*/) { 895 USE(type); 896 VIXL_ASSERT((type == kLdmda) || (type == kLdmdb) || (type == kLdmea) || 897 (type == kLdmed) || (type == kLdmfa) || (type == kLdmib) || 898 (type == kStmda) || (type == kStmed) || (type == kStmfa) || 899 (type == kStmfd) || (type == kStmib)); 900 UnimplementedDelegate(type); 901 } Delegate(InstructionType type,InstructionCondSizeRMop,Condition,EncodingSize,Register,const MemOperand &)902 virtual void Delegate(InstructionType type, 903 InstructionCondSizeRMop /*instruction*/, 904 Condition /*cond*/, 905 EncodingSize /*size*/, 906 Register /*rt*/, 907 const MemOperand& /*operand*/) { 908 USE(type); 909 VIXL_ASSERT((type == kLdr) || (type == kLdrb) || (type == kLdrh) || 910 (type == kLdrsb) || (type == kLdrsh) || (type == kStr) || 911 (type == kStrb) || (type == kStrh)); 912 UnimplementedDelegate(type); 913 } Delegate(InstructionType type,InstructionCondRL,Condition,Register,Location *)914 virtual void Delegate(InstructionType type, 915 InstructionCondRL /*instruction*/, 916 Condition /*cond*/, 917 Register /*rt*/, 918 Location* /*location*/) { 919 USE(type); 920 VIXL_ASSERT((type == kLdrb) || (type == kLdrh) || (type == kLdrsb) || 921 (type == kLdrsh)); 922 UnimplementedDelegate(type); 923 } Delegate(InstructionType type,InstructionCondRRL,Condition,Register,Register,Location *)924 virtual void Delegate(InstructionType type, 925 InstructionCondRRL /*instruction*/, 926 Condition /*cond*/, 927 Register /*rt*/, 928 Register /*rt2*/, 929 Location* /*location*/) { 930 USE(type); 931 VIXL_ASSERT((type == kLdrd)); 932 UnimplementedDelegate(type); 933 } Delegate(InstructionType type,InstructionCondRRRR,Condition,Register,Register,Register,Register)934 virtual void Delegate(InstructionType type, 935 InstructionCondRRRR /*instruction*/, 936 Condition /*cond*/, 937 Register /*rd*/, 938 Register /*rn*/, 939 Register /*rm*/, 940 Register /*ra*/) { 941 USE(type); 942 VIXL_ASSERT((type == kMla) || (type == kMlas) || (type == kMls) || 943 (type == kSmlabb) || (type == kSmlabt) || (type == kSmlad) || 944 (type == kSmladx) || (type == kSmlal) || (type == kSmlalbb) || 945 (type == kSmlalbt) || (type == kSmlald) || (type == kSmlaldx) || 946 (type == kSmlals) || (type == kSmlaltb) || (type == kSmlaltt) || 947 (type == kSmlatb) || (type == kSmlatt) || (type == kSmlawb) || 948 (type == kSmlawt) || (type == kSmlsd) || (type == kSmlsdx) || 949 (type == kSmlsld) || (type == kSmlsldx) || (type == kSmmla) || 950 (type == kSmmlar) || (type == kSmmls) || (type == kSmmlsr) || 951 (type == kSmull) || (type == kSmulls) || (type == kUmaal) || 952 (type == kUmlal) || (type == kUmlals) || (type == kUmull) || 953 (type == kUmulls) || (type == kUsada8)); 954 UnimplementedDelegate(type); 955 } Delegate(InstructionType type,InstructionCondRSr,Condition,Register,SpecialRegister)956 virtual void Delegate(InstructionType type, 957 InstructionCondRSr /*instruction*/, 958 Condition /*cond*/, 959 Register /*rd*/, 960 SpecialRegister /*spec_reg*/) { 961 USE(type); 962 VIXL_ASSERT((type == kMrs)); 963 UnimplementedDelegate(type); 964 } Delegate(InstructionType type,InstructionCondMsrOp,Condition,MaskedSpecialRegister,const Operand &)965 virtual void Delegate(InstructionType type, 966 InstructionCondMsrOp /*instruction*/, 967 Condition /*cond*/, 968 MaskedSpecialRegister /*spec_reg*/, 969 const Operand& /*operand*/) { 970 USE(type); 971 VIXL_ASSERT((type == kMsr)); 972 UnimplementedDelegate(type); 973 } Delegate(InstructionType type,InstructionCondSizeRRR,Condition,EncodingSize,Register,Register,Register)974 virtual void Delegate(InstructionType type, 975 InstructionCondSizeRRR /*instruction*/, 976 Condition /*cond*/, 977 EncodingSize /*size*/, 978 Register /*rd*/, 979 Register /*rn*/, 980 Register /*rm*/) { 981 USE(type); 982 VIXL_ASSERT((type == kMul)); 983 UnimplementedDelegate(type); 984 } Delegate(InstructionType type,InstructionCondSize,Condition,EncodingSize)985 virtual void Delegate(InstructionType type, 986 InstructionCondSize /*instruction*/, 987 Condition /*cond*/, 988 EncodingSize /*size*/) { 989 USE(type); 990 VIXL_ASSERT((type == kNop) || (type == kYield)); 991 UnimplementedDelegate(type); 992 } Delegate(InstructionType type,InstructionCondMop,Condition,const MemOperand &)993 virtual void Delegate(InstructionType type, 994 InstructionCondMop /*instruction*/, 995 Condition /*cond*/, 996 const MemOperand& /*operand*/) { 997 USE(type); 998 VIXL_ASSERT((type == kPld) || (type == kPldw) || (type == kPli)); 999 UnimplementedDelegate(type); 1000 } Delegate(InstructionType type,InstructionCondSizeRl,Condition,EncodingSize,RegisterList)1001 virtual void Delegate(InstructionType type, 1002 InstructionCondSizeRl /*instruction*/, 1003 Condition /*cond*/, 1004 EncodingSize /*size*/, 1005 RegisterList /*registers*/) { 1006 USE(type); 1007 VIXL_ASSERT((type == kPop) || (type == kPush)); 1008 UnimplementedDelegate(type); 1009 } Delegate(InstructionType type,InstructionCondSizeOrl,Condition,EncodingSize,Register)1010 virtual void Delegate(InstructionType type, 1011 InstructionCondSizeOrl /*instruction*/, 1012 Condition /*cond*/, 1013 EncodingSize /*size*/, 1014 Register /*rt*/) { 1015 USE(type); 1016 VIXL_ASSERT((type == kPop) || (type == kPush)); 1017 UnimplementedDelegate(type); 1018 } Delegate(InstructionType type,InstructionCondSizeRR,Condition,EncodingSize,Register,Register)1019 virtual void Delegate(InstructionType type, 1020 InstructionCondSizeRR /*instruction*/, 1021 Condition /*cond*/, 1022 EncodingSize /*size*/, 1023 Register /*rd*/, 1024 Register /*rm*/) { 1025 USE(type); 1026 VIXL_ASSERT((type == kRev) || (type == kRev16) || (type == kRevsh)); 1027 UnimplementedDelegate(type); 1028 } Delegate(InstructionType type,InstructionDtQQQ,DataType,QRegister,QRegister,QRegister)1029 virtual void Delegate(InstructionType type, 1030 InstructionDtQQQ /*instruction*/, 1031 DataType /*dt*/, 1032 QRegister /*rd*/, 1033 QRegister /*rn*/, 1034 QRegister /*rm*/) { 1035 USE(type); 1036 VIXL_ASSERT((type == kVmaxnm) || (type == kVminnm)); 1037 UnimplementedDelegate(type); 1038 } Delegate(InstructionType type,InstructionCondRIOp,Condition,Register,uint32_t,const Operand &)1039 virtual void Delegate(InstructionType type, 1040 InstructionCondRIOp /*instruction*/, 1041 Condition /*cond*/, 1042 Register /*rd*/, 1043 uint32_t /*imm*/, 1044 const Operand& /*operand*/) { 1045 USE(type); 1046 VIXL_ASSERT((type == kSsat) || (type == kUsat)); 1047 UnimplementedDelegate(type); 1048 } Delegate(InstructionType type,InstructionCondRIR,Condition,Register,uint32_t,Register)1049 virtual void Delegate(InstructionType type, 1050 InstructionCondRIR /*instruction*/, 1051 Condition /*cond*/, 1052 Register /*rd*/, 1053 uint32_t /*imm*/, 1054 Register /*rn*/) { 1055 USE(type); 1056 VIXL_ASSERT((type == kSsat16) || (type == kUsat16)); 1057 UnimplementedDelegate(type); 1058 } Delegate(InstructionType type,InstructionCondRRRMop,Condition,Register,Register,Register,const MemOperand &)1059 virtual void Delegate(InstructionType type, 1060 InstructionCondRRRMop /*instruction*/, 1061 Condition /*cond*/, 1062 Register /*rd*/, 1063 Register /*rt*/, 1064 Register /*rt2*/, 1065 const MemOperand& /*operand*/) { 1066 USE(type); 1067 VIXL_ASSERT((type == kStlexd) || (type == kStrexd)); 1068 UnimplementedDelegate(type); 1069 } Delegate(InstructionType type,InstructionCondSizeI,Condition,EncodingSize,uint32_t)1070 virtual void Delegate(InstructionType type, 1071 InstructionCondSizeI /*instruction*/, 1072 Condition /*cond*/, 1073 EncodingSize /*size*/, 1074 uint32_t /*imm*/) { 1075 USE(type); 1076 VIXL_ASSERT((type == kUdf)); 1077 UnimplementedDelegate(type); 1078 } Delegate(InstructionType type,InstructionCondDtDDD,Condition,DataType,DRegister,DRegister,DRegister)1079 virtual void Delegate(InstructionType type, 1080 InstructionCondDtDDD /*instruction*/, 1081 Condition /*cond*/, 1082 DataType /*dt*/, 1083 DRegister /*rd*/, 1084 DRegister /*rn*/, 1085 DRegister /*rm*/) { 1086 USE(type); 1087 VIXL_ASSERT((type == kVaba) || (type == kVabd) || (type == kVacge) || 1088 (type == kVacgt) || (type == kVacle) || (type == kVaclt) || 1089 (type == kVadd) || (type == kVbif) || (type == kVbit) || 1090 (type == kVbsl) || (type == kVceq) || (type == kVcge) || 1091 (type == kVcgt) || (type == kVcle) || (type == kVclt) || 1092 (type == kVdiv) || (type == kVeor) || (type == kVfma) || 1093 (type == kVfms) || (type == kVfnma) || (type == kVfnms) || 1094 (type == kVhadd) || (type == kVhsub) || (type == kVmax) || 1095 (type == kVmin) || (type == kVmla) || (type == kVmls) || 1096 (type == kVmul) || (type == kVnmla) || (type == kVnmls) || 1097 (type == kVnmul) || (type == kVpadd) || (type == kVpmax) || 1098 (type == kVpmin) || (type == kVqadd) || (type == kVqdmulh) || 1099 (type == kVqrdmulh) || (type == kVqrshl) || (type == kVqsub) || 1100 (type == kVrecps) || (type == kVrhadd) || (type == kVrshl) || 1101 (type == kVrsqrts) || (type == kVsub) || (type == kVtst)); 1102 UnimplementedDelegate(type); 1103 } Delegate(InstructionType type,InstructionCondDtQQQ,Condition,DataType,QRegister,QRegister,QRegister)1104 virtual void Delegate(InstructionType type, 1105 InstructionCondDtQQQ /*instruction*/, 1106 Condition /*cond*/, 1107 DataType /*dt*/, 1108 QRegister /*rd*/, 1109 QRegister /*rn*/, 1110 QRegister /*rm*/) { 1111 USE(type); 1112 VIXL_ASSERT((type == kVaba) || (type == kVabd) || (type == kVacge) || 1113 (type == kVacgt) || (type == kVacle) || (type == kVaclt) || 1114 (type == kVadd) || (type == kVbif) || (type == kVbit) || 1115 (type == kVbsl) || (type == kVceq) || (type == kVcge) || 1116 (type == kVcgt) || (type == kVcle) || (type == kVclt) || 1117 (type == kVeor) || (type == kVfma) || (type == kVfms) || 1118 (type == kVhadd) || (type == kVhsub) || (type == kVmax) || 1119 (type == kVmin) || (type == kVmla) || (type == kVmls) || 1120 (type == kVmul) || (type == kVqadd) || (type == kVqdmulh) || 1121 (type == kVqrdmulh) || (type == kVqrshl) || (type == kVqsub) || 1122 (type == kVrecps) || (type == kVrhadd) || (type == kVrshl) || 1123 (type == kVrsqrts) || (type == kVsub) || (type == kVtst)); 1124 UnimplementedDelegate(type); 1125 } Delegate(InstructionType type,InstructionCondDtQDD,Condition,DataType,QRegister,DRegister,DRegister)1126 virtual void Delegate(InstructionType type, 1127 InstructionCondDtQDD /*instruction*/, 1128 Condition /*cond*/, 1129 DataType /*dt*/, 1130 QRegister /*rd*/, 1131 DRegister /*rn*/, 1132 DRegister /*rm*/) { 1133 USE(type); 1134 VIXL_ASSERT((type == kVabal) || (type == kVabdl) || (type == kVaddl) || 1135 (type == kVmlal) || (type == kVmlsl) || (type == kVmull) || 1136 (type == kVqdmlal) || (type == kVqdmlsl) || 1137 (type == kVqdmull) || (type == kVsubl)); 1138 UnimplementedDelegate(type); 1139 } Delegate(InstructionType type,InstructionCondDtDD,Condition,DataType,DRegister,DRegister)1140 virtual void Delegate(InstructionType type, 1141 InstructionCondDtDD /*instruction*/, 1142 Condition /*cond*/, 1143 DataType /*dt*/, 1144 DRegister /*rd*/, 1145 DRegister /*rm*/) { 1146 USE(type); 1147 VIXL_ASSERT((type == kVabs) || (type == kVcls) || (type == kVclz) || 1148 (type == kVcnt) || (type == kVneg) || (type == kVpadal) || 1149 (type == kVpaddl) || (type == kVqabs) || (type == kVqneg) || 1150 (type == kVrecpe) || (type == kVrev16) || (type == kVrev32) || 1151 (type == kVrev64) || (type == kVrintr) || (type == kVrintx) || 1152 (type == kVrintz) || (type == kVrsqrte) || (type == kVsqrt) || 1153 (type == kVswp) || (type == kVtrn) || (type == kVuzp) || 1154 (type == kVzip)); 1155 UnimplementedDelegate(type); 1156 } Delegate(InstructionType type,InstructionCondDtQQ,Condition,DataType,QRegister,QRegister)1157 virtual void Delegate(InstructionType type, 1158 InstructionCondDtQQ /*instruction*/, 1159 Condition /*cond*/, 1160 DataType /*dt*/, 1161 QRegister /*rd*/, 1162 QRegister /*rm*/) { 1163 USE(type); 1164 VIXL_ASSERT((type == kVabs) || (type == kVcls) || (type == kVclz) || 1165 (type == kVcnt) || (type == kVneg) || (type == kVpadal) || 1166 (type == kVpaddl) || (type == kVqabs) || (type == kVqneg) || 1167 (type == kVrecpe) || (type == kVrev16) || (type == kVrev32) || 1168 (type == kVrev64) || (type == kVrsqrte) || (type == kVswp) || 1169 (type == kVtrn) || (type == kVuzp) || (type == kVzip)); 1170 UnimplementedDelegate(type); 1171 } Delegate(InstructionType type,InstructionCondDtSS,Condition,DataType,SRegister,SRegister)1172 virtual void Delegate(InstructionType type, 1173 InstructionCondDtSS /*instruction*/, 1174 Condition /*cond*/, 1175 DataType /*dt*/, 1176 SRegister /*rd*/, 1177 SRegister /*rm*/) { 1178 USE(type); 1179 VIXL_ASSERT((type == kVabs) || (type == kVneg) || (type == kVrintr) || 1180 (type == kVrintx) || (type == kVrintz) || (type == kVsqrt)); 1181 UnimplementedDelegate(type); 1182 } Delegate(InstructionType type,InstructionCondDtSSS,Condition,DataType,SRegister,SRegister,SRegister)1183 virtual void Delegate(InstructionType type, 1184 InstructionCondDtSSS /*instruction*/, 1185 Condition /*cond*/, 1186 DataType /*dt*/, 1187 SRegister /*rd*/, 1188 SRegister /*rn*/, 1189 SRegister /*rm*/) { 1190 USE(type); 1191 VIXL_ASSERT((type == kVadd) || (type == kVdiv) || (type == kVfma) || 1192 (type == kVfms) || (type == kVfnma) || (type == kVfnms) || 1193 (type == kVmla) || (type == kVmls) || (type == kVmul) || 1194 (type == kVnmla) || (type == kVnmls) || (type == kVnmul) || 1195 (type == kVsub)); 1196 UnimplementedDelegate(type); 1197 } Delegate(InstructionType type,InstructionCondDtDQQ,Condition,DataType,DRegister,QRegister,QRegister)1198 virtual void Delegate(InstructionType type, 1199 InstructionCondDtDQQ /*instruction*/, 1200 Condition /*cond*/, 1201 DataType /*dt*/, 1202 DRegister /*rd*/, 1203 QRegister /*rn*/, 1204 QRegister /*rm*/) { 1205 USE(type); 1206 VIXL_ASSERT((type == kVaddhn) || (type == kVraddhn) || (type == kVrsubhn) || 1207 (type == kVsubhn)); 1208 UnimplementedDelegate(type); 1209 } Delegate(InstructionType type,InstructionCondDtQQD,Condition,DataType,QRegister,QRegister,DRegister)1210 virtual void Delegate(InstructionType type, 1211 InstructionCondDtQQD /*instruction*/, 1212 Condition /*cond*/, 1213 DataType /*dt*/, 1214 QRegister /*rd*/, 1215 QRegister /*rn*/, 1216 DRegister /*rm*/) { 1217 USE(type); 1218 VIXL_ASSERT((type == kVaddw) || (type == kVsubw)); 1219 UnimplementedDelegate(type); 1220 } Delegate(InstructionType type,InstructionCondDtDDDop,Condition,DataType,DRegister,DRegister,const DOperand &)1221 virtual void Delegate(InstructionType type, 1222 InstructionCondDtDDDop /*instruction*/, 1223 Condition /*cond*/, 1224 DataType /*dt*/, 1225 DRegister /*rd*/, 1226 DRegister /*rn*/, 1227 const DOperand& /*operand*/) { 1228 USE(type); 1229 VIXL_ASSERT((type == kVand) || (type == kVbic) || (type == kVceq) || 1230 (type == kVcge) || (type == kVcgt) || (type == kVcle) || 1231 (type == kVclt) || (type == kVorn) || (type == kVorr) || 1232 (type == kVqshl) || (type == kVqshlu) || (type == kVrshr) || 1233 (type == kVrsra) || (type == kVshl) || (type == kVshr) || 1234 (type == kVsli) || (type == kVsra) || (type == kVsri)); 1235 UnimplementedDelegate(type); 1236 } Delegate(InstructionType type,InstructionCondDtQQQop,Condition,DataType,QRegister,QRegister,const QOperand &)1237 virtual void Delegate(InstructionType type, 1238 InstructionCondDtQQQop /*instruction*/, 1239 Condition /*cond*/, 1240 DataType /*dt*/, 1241 QRegister /*rd*/, 1242 QRegister /*rn*/, 1243 const QOperand& /*operand*/) { 1244 USE(type); 1245 VIXL_ASSERT((type == kVand) || (type == kVbic) || (type == kVceq) || 1246 (type == kVcge) || (type == kVcgt) || (type == kVcle) || 1247 (type == kVclt) || (type == kVorn) || (type == kVorr) || 1248 (type == kVqshl) || (type == kVqshlu) || (type == kVrshr) || 1249 (type == kVrsra) || (type == kVshl) || (type == kVshr) || 1250 (type == kVsli) || (type == kVsra) || (type == kVsri)); 1251 UnimplementedDelegate(type); 1252 } Delegate(InstructionType type,InstructionCondDtSSop,Condition,DataType,SRegister,const SOperand &)1253 virtual void Delegate(InstructionType type, 1254 InstructionCondDtSSop /*instruction*/, 1255 Condition /*cond*/, 1256 DataType /*dt*/, 1257 SRegister /*rd*/, 1258 const SOperand& /*operand*/) { 1259 USE(type); 1260 VIXL_ASSERT((type == kVcmp) || (type == kVcmpe) || (type == kVmov)); 1261 UnimplementedDelegate(type); 1262 } Delegate(InstructionType type,InstructionCondDtDDop,Condition,DataType,DRegister,const DOperand &)1263 virtual void Delegate(InstructionType type, 1264 InstructionCondDtDDop /*instruction*/, 1265 Condition /*cond*/, 1266 DataType /*dt*/, 1267 DRegister /*rd*/, 1268 const DOperand& /*operand*/) { 1269 USE(type); 1270 VIXL_ASSERT((type == kVcmp) || (type == kVcmpe) || (type == kVmov) || 1271 (type == kVmvn)); 1272 UnimplementedDelegate(type); 1273 } Delegate(InstructionType type,InstructionCondDtDtDS,Condition,DataType,DataType,DRegister,SRegister)1274 virtual void Delegate(InstructionType type, 1275 InstructionCondDtDtDS /*instruction*/, 1276 Condition /*cond*/, 1277 DataType /*dt1*/, 1278 DataType /*dt2*/, 1279 DRegister /*rd*/, 1280 SRegister /*rm*/) { 1281 USE(type); 1282 VIXL_ASSERT((type == kVcvt) || (type == kVcvtb) || (type == kVcvtt)); 1283 UnimplementedDelegate(type); 1284 } Delegate(InstructionType type,InstructionCondDtDtSD,Condition,DataType,DataType,SRegister,DRegister)1285 virtual void Delegate(InstructionType type, 1286 InstructionCondDtDtSD /*instruction*/, 1287 Condition /*cond*/, 1288 DataType /*dt1*/, 1289 DataType /*dt2*/, 1290 SRegister /*rd*/, 1291 DRegister /*rm*/) { 1292 USE(type); 1293 VIXL_ASSERT((type == kVcvt) || (type == kVcvtb) || (type == kVcvtr) || 1294 (type == kVcvtt)); 1295 UnimplementedDelegate(type); 1296 } Delegate(InstructionType type,InstructionCondDtDtDDSi,Condition,DataType,DataType,DRegister,DRegister,int32_t)1297 virtual void Delegate(InstructionType type, 1298 InstructionCondDtDtDDSi /*instruction*/, 1299 Condition /*cond*/, 1300 DataType /*dt1*/, 1301 DataType /*dt2*/, 1302 DRegister /*rd*/, 1303 DRegister /*rm*/, 1304 int32_t /*fbits*/) { 1305 USE(type); 1306 VIXL_ASSERT((type == kVcvt)); 1307 UnimplementedDelegate(type); 1308 } Delegate(InstructionType type,InstructionCondDtDtQQSi,Condition,DataType,DataType,QRegister,QRegister,int32_t)1309 virtual void Delegate(InstructionType type, 1310 InstructionCondDtDtQQSi /*instruction*/, 1311 Condition /*cond*/, 1312 DataType /*dt1*/, 1313 DataType /*dt2*/, 1314 QRegister /*rd*/, 1315 QRegister /*rm*/, 1316 int32_t /*fbits*/) { 1317 USE(type); 1318 VIXL_ASSERT((type == kVcvt)); 1319 UnimplementedDelegate(type); 1320 } Delegate(InstructionType type,InstructionCondDtDtSSSi,Condition,DataType,DataType,SRegister,SRegister,int32_t)1321 virtual void Delegate(InstructionType type, 1322 InstructionCondDtDtSSSi /*instruction*/, 1323 Condition /*cond*/, 1324 DataType /*dt1*/, 1325 DataType /*dt2*/, 1326 SRegister /*rd*/, 1327 SRegister /*rm*/, 1328 int32_t /*fbits*/) { 1329 USE(type); 1330 VIXL_ASSERT((type == kVcvt)); 1331 UnimplementedDelegate(type); 1332 } Delegate(InstructionType type,InstructionCondDtDtDD,Condition,DataType,DataType,DRegister,DRegister)1333 virtual void Delegate(InstructionType type, 1334 InstructionCondDtDtDD /*instruction*/, 1335 Condition /*cond*/, 1336 DataType /*dt1*/, 1337 DataType /*dt2*/, 1338 DRegister /*rd*/, 1339 DRegister /*rm*/) { 1340 USE(type); 1341 VIXL_ASSERT((type == kVcvt)); 1342 UnimplementedDelegate(type); 1343 } Delegate(InstructionType type,InstructionCondDtDtQQ,Condition,DataType,DataType,QRegister,QRegister)1344 virtual void Delegate(InstructionType type, 1345 InstructionCondDtDtQQ /*instruction*/, 1346 Condition /*cond*/, 1347 DataType /*dt1*/, 1348 DataType /*dt2*/, 1349 QRegister /*rd*/, 1350 QRegister /*rm*/) { 1351 USE(type); 1352 VIXL_ASSERT((type == kVcvt)); 1353 UnimplementedDelegate(type); 1354 } Delegate(InstructionType type,InstructionCondDtDtDQ,Condition,DataType,DataType,DRegister,QRegister)1355 virtual void Delegate(InstructionType type, 1356 InstructionCondDtDtDQ /*instruction*/, 1357 Condition /*cond*/, 1358 DataType /*dt1*/, 1359 DataType /*dt2*/, 1360 DRegister /*rd*/, 1361 QRegister /*rm*/) { 1362 USE(type); 1363 VIXL_ASSERT((type == kVcvt)); 1364 UnimplementedDelegate(type); 1365 } Delegate(InstructionType type,InstructionCondDtDtQD,Condition,DataType,DataType,QRegister,DRegister)1366 virtual void Delegate(InstructionType type, 1367 InstructionCondDtDtQD /*instruction*/, 1368 Condition /*cond*/, 1369 DataType /*dt1*/, 1370 DataType /*dt2*/, 1371 QRegister /*rd*/, 1372 DRegister /*rm*/) { 1373 USE(type); 1374 VIXL_ASSERT((type == kVcvt)); 1375 UnimplementedDelegate(type); 1376 } Delegate(InstructionType type,InstructionCondDtDtSS,Condition,DataType,DataType,SRegister,SRegister)1377 virtual void Delegate(InstructionType type, 1378 InstructionCondDtDtSS /*instruction*/, 1379 Condition /*cond*/, 1380 DataType /*dt1*/, 1381 DataType /*dt2*/, 1382 SRegister /*rd*/, 1383 SRegister /*rm*/) { 1384 USE(type); 1385 VIXL_ASSERT((type == kVcvt) || (type == kVcvtb) || (type == kVcvtr) || 1386 (type == kVcvtt)); 1387 UnimplementedDelegate(type); 1388 } Delegate(InstructionType type,InstructionDtDtDD,DataType,DataType,DRegister,DRegister)1389 virtual void Delegate(InstructionType type, 1390 InstructionDtDtDD /*instruction*/, 1391 DataType /*dt1*/, 1392 DataType /*dt2*/, 1393 DRegister /*rd*/, 1394 DRegister /*rm*/) { 1395 USE(type); 1396 VIXL_ASSERT((type == kVcvta) || (type == kVcvtm) || (type == kVcvtn) || 1397 (type == kVcvtp)); 1398 UnimplementedDelegate(type); 1399 } Delegate(InstructionType type,InstructionDtDtQQ,DataType,DataType,QRegister,QRegister)1400 virtual void Delegate(InstructionType type, 1401 InstructionDtDtQQ /*instruction*/, 1402 DataType /*dt1*/, 1403 DataType /*dt2*/, 1404 QRegister /*rd*/, 1405 QRegister /*rm*/) { 1406 USE(type); 1407 VIXL_ASSERT((type == kVcvta) || (type == kVcvtm) || (type == kVcvtn) || 1408 (type == kVcvtp)); 1409 UnimplementedDelegate(type); 1410 } Delegate(InstructionType type,InstructionDtDtSS,DataType,DataType,SRegister,SRegister)1411 virtual void Delegate(InstructionType type, 1412 InstructionDtDtSS /*instruction*/, 1413 DataType /*dt1*/, 1414 DataType /*dt2*/, 1415 SRegister /*rd*/, 1416 SRegister /*rm*/) { 1417 USE(type); 1418 VIXL_ASSERT((type == kVcvta) || (type == kVcvtm) || (type == kVcvtn) || 1419 (type == kVcvtp)); 1420 UnimplementedDelegate(type); 1421 } Delegate(InstructionType type,InstructionDtDtSD,DataType,DataType,SRegister,DRegister)1422 virtual void Delegate(InstructionType type, 1423 InstructionDtDtSD /*instruction*/, 1424 DataType /*dt1*/, 1425 DataType /*dt2*/, 1426 SRegister /*rd*/, 1427 DRegister /*rm*/) { 1428 USE(type); 1429 VIXL_ASSERT((type == kVcvta) || (type == kVcvtm) || (type == kVcvtn) || 1430 (type == kVcvtp)); 1431 UnimplementedDelegate(type); 1432 } Delegate(InstructionType type,InstructionCondDtQR,Condition,DataType,QRegister,Register)1433 virtual void Delegate(InstructionType type, 1434 InstructionCondDtQR /*instruction*/, 1435 Condition /*cond*/, 1436 DataType /*dt*/, 1437 QRegister /*rd*/, 1438 Register /*rt*/) { 1439 USE(type); 1440 VIXL_ASSERT((type == kVdup)); 1441 UnimplementedDelegate(type); 1442 } Delegate(InstructionType type,InstructionCondDtDR,Condition,DataType,DRegister,Register)1443 virtual void Delegate(InstructionType type, 1444 InstructionCondDtDR /*instruction*/, 1445 Condition /*cond*/, 1446 DataType /*dt*/, 1447 DRegister /*rd*/, 1448 Register /*rt*/) { 1449 USE(type); 1450 VIXL_ASSERT((type == kVdup)); 1451 UnimplementedDelegate(type); 1452 } Delegate(InstructionType type,InstructionCondDtDDx,Condition,DataType,DRegister,DRegisterLane)1453 virtual void Delegate(InstructionType type, 1454 InstructionCondDtDDx /*instruction*/, 1455 Condition /*cond*/, 1456 DataType /*dt*/, 1457 DRegister /*rd*/, 1458 DRegisterLane /*rm*/) { 1459 USE(type); 1460 VIXL_ASSERT((type == kVdup)); 1461 UnimplementedDelegate(type); 1462 } Delegate(InstructionType type,InstructionCondDtQDx,Condition,DataType,QRegister,DRegisterLane)1463 virtual void Delegate(InstructionType type, 1464 InstructionCondDtQDx /*instruction*/, 1465 Condition /*cond*/, 1466 DataType /*dt*/, 1467 QRegister /*rd*/, 1468 DRegisterLane /*rm*/) { 1469 USE(type); 1470 VIXL_ASSERT((type == kVdup)); 1471 UnimplementedDelegate(type); 1472 } Delegate(InstructionType type,InstructionCondDtDDDDop,Condition,DataType,DRegister,DRegister,DRegister,const DOperand &)1473 virtual void Delegate(InstructionType type, 1474 InstructionCondDtDDDDop /*instruction*/, 1475 Condition /*cond*/, 1476 DataType /*dt*/, 1477 DRegister /*rd*/, 1478 DRegister /*rn*/, 1479 DRegister /*rm*/, 1480 const DOperand& /*operand*/) { 1481 USE(type); 1482 VIXL_ASSERT((type == kVext)); 1483 UnimplementedDelegate(type); 1484 } Delegate(InstructionType type,InstructionCondDtQQQQop,Condition,DataType,QRegister,QRegister,QRegister,const QOperand &)1485 virtual void Delegate(InstructionType type, 1486 InstructionCondDtQQQQop /*instruction*/, 1487 Condition /*cond*/, 1488 DataType /*dt*/, 1489 QRegister /*rd*/, 1490 QRegister /*rn*/, 1491 QRegister /*rm*/, 1492 const QOperand& /*operand*/) { 1493 USE(type); 1494 VIXL_ASSERT((type == kVext)); 1495 UnimplementedDelegate(type); 1496 } Delegate(InstructionType type,InstructionCondDtNrlAmop,Condition,DataType,const NeonRegisterList &,const AlignedMemOperand &)1497 virtual void Delegate(InstructionType type, 1498 InstructionCondDtNrlAmop /*instruction*/, 1499 Condition /*cond*/, 1500 DataType /*dt*/, 1501 const NeonRegisterList& /*nreglist*/, 1502 const AlignedMemOperand& /*operand*/) { 1503 USE(type); 1504 VIXL_ASSERT((type == kVld1) || (type == kVld2) || (type == kVld3) || 1505 (type == kVld4) || (type == kVst1) || (type == kVst2) || 1506 (type == kVst3) || (type == kVst4)); 1507 UnimplementedDelegate(type); 1508 } Delegate(InstructionType type,InstructionCondDtNrlMop,Condition,DataType,const NeonRegisterList &,const MemOperand &)1509 virtual void Delegate(InstructionType type, 1510 InstructionCondDtNrlMop /*instruction*/, 1511 Condition /*cond*/, 1512 DataType /*dt*/, 1513 const NeonRegisterList& /*nreglist*/, 1514 const MemOperand& /*operand*/) { 1515 USE(type); 1516 VIXL_ASSERT((type == kVld3) || (type == kVst3)); 1517 UnimplementedDelegate(type); 1518 } Delegate(InstructionType type,InstructionCondDtRwbDrl,Condition,DataType,Register,WriteBack,DRegisterList)1519 virtual void Delegate(InstructionType type, 1520 InstructionCondDtRwbDrl /*instruction*/, 1521 Condition /*cond*/, 1522 DataType /*dt*/, 1523 Register /*rn*/, 1524 WriteBack /*write_back*/, 1525 DRegisterList /*dreglist*/) { 1526 USE(type); 1527 VIXL_ASSERT((type == kVldm) || (type == kVldmdb) || (type == kVldmia) || 1528 (type == kVstm) || (type == kVstmdb) || (type == kVstmia)); 1529 UnimplementedDelegate(type); 1530 } Delegate(InstructionType type,InstructionCondDtRwbSrl,Condition,DataType,Register,WriteBack,SRegisterList)1531 virtual void Delegate(InstructionType type, 1532 InstructionCondDtRwbSrl /*instruction*/, 1533 Condition /*cond*/, 1534 DataType /*dt*/, 1535 Register /*rn*/, 1536 WriteBack /*write_back*/, 1537 SRegisterList /*sreglist*/) { 1538 USE(type); 1539 VIXL_ASSERT((type == kVldm) || (type == kVldmdb) || (type == kVldmia) || 1540 (type == kVstm) || (type == kVstmdb) || (type == kVstmia)); 1541 UnimplementedDelegate(type); 1542 } Delegate(InstructionType type,InstructionCondDtDL,Condition,DataType,DRegister,Location *)1543 virtual void Delegate(InstructionType type, 1544 InstructionCondDtDL /*instruction*/, 1545 Condition /*cond*/, 1546 DataType /*dt*/, 1547 DRegister /*rd*/, 1548 Location* /*location*/) { 1549 USE(type); 1550 VIXL_ASSERT((type == kVldr)); 1551 UnimplementedDelegate(type); 1552 } Delegate(InstructionType type,InstructionCondDtDMop,Condition,DataType,DRegister,const MemOperand &)1553 virtual void Delegate(InstructionType type, 1554 InstructionCondDtDMop /*instruction*/, 1555 Condition /*cond*/, 1556 DataType /*dt*/, 1557 DRegister /*rd*/, 1558 const MemOperand& /*operand*/) { 1559 USE(type); 1560 VIXL_ASSERT((type == kVldr) || (type == kVstr)); 1561 UnimplementedDelegate(type); 1562 } Delegate(InstructionType type,InstructionCondDtSL,Condition,DataType,SRegister,Location *)1563 virtual void Delegate(InstructionType type, 1564 InstructionCondDtSL /*instruction*/, 1565 Condition /*cond*/, 1566 DataType /*dt*/, 1567 SRegister /*rd*/, 1568 Location* /*location*/) { 1569 USE(type); 1570 VIXL_ASSERT((type == kVldr)); 1571 UnimplementedDelegate(type); 1572 } Delegate(InstructionType type,InstructionCondDtSMop,Condition,DataType,SRegister,const MemOperand &)1573 virtual void Delegate(InstructionType type, 1574 InstructionCondDtSMop /*instruction*/, 1575 Condition /*cond*/, 1576 DataType /*dt*/, 1577 SRegister /*rd*/, 1578 const MemOperand& /*operand*/) { 1579 USE(type); 1580 VIXL_ASSERT((type == kVldr) || (type == kVstr)); 1581 UnimplementedDelegate(type); 1582 } Delegate(InstructionType type,InstructionDtDDD,DataType,DRegister,DRegister,DRegister)1583 virtual void Delegate(InstructionType type, 1584 InstructionDtDDD /*instruction*/, 1585 DataType /*dt*/, 1586 DRegister /*rd*/, 1587 DRegister /*rn*/, 1588 DRegister /*rm*/) { 1589 USE(type); 1590 VIXL_ASSERT((type == kVmaxnm) || (type == kVminnm) || (type == kVseleq) || 1591 (type == kVselge) || (type == kVselgt) || (type == kVselvs)); 1592 UnimplementedDelegate(type); 1593 } Delegate(InstructionType type,InstructionDtSSS,DataType,SRegister,SRegister,SRegister)1594 virtual void Delegate(InstructionType type, 1595 InstructionDtSSS /*instruction*/, 1596 DataType /*dt*/, 1597 SRegister /*rd*/, 1598 SRegister /*rn*/, 1599 SRegister /*rm*/) { 1600 USE(type); 1601 VIXL_ASSERT((type == kVmaxnm) || (type == kVminnm) || (type == kVseleq) || 1602 (type == kVselge) || (type == kVselgt) || (type == kVselvs)); 1603 UnimplementedDelegate(type); 1604 } Delegate(InstructionType type,InstructionCondDtDDDx,Condition,DataType,DRegister,DRegister,DRegisterLane)1605 virtual void Delegate(InstructionType type, 1606 InstructionCondDtDDDx /*instruction*/, 1607 Condition /*cond*/, 1608 DataType /*dt*/, 1609 DRegister /*rd*/, 1610 DRegister /*rn*/, 1611 DRegisterLane /*rm*/) { 1612 USE(type); 1613 VIXL_ASSERT((type == kVmla) || (type == kVmls) || (type == kVqdmulh) || 1614 (type == kVqrdmulh)); 1615 UnimplementedDelegate(type); 1616 } Delegate(InstructionType type,InstructionCondDtQQDx,Condition,DataType,QRegister,QRegister,DRegisterLane)1617 virtual void Delegate(InstructionType type, 1618 InstructionCondDtQQDx /*instruction*/, 1619 Condition /*cond*/, 1620 DataType /*dt*/, 1621 QRegister /*rd*/, 1622 QRegister /*rn*/, 1623 DRegisterLane /*rm*/) { 1624 USE(type); 1625 VIXL_ASSERT((type == kVmla) || (type == kVmls) || (type == kVqdmulh) || 1626 (type == kVqrdmulh)); 1627 UnimplementedDelegate(type); 1628 } Delegate(InstructionType type,InstructionCondDtQDDx,Condition,DataType,QRegister,DRegister,DRegisterLane)1629 virtual void Delegate(InstructionType type, 1630 InstructionCondDtQDDx /*instruction*/, 1631 Condition /*cond*/, 1632 DataType /*dt*/, 1633 QRegister /*rd*/, 1634 DRegister /*rn*/, 1635 DRegisterLane /*rm*/) { 1636 USE(type); 1637 VIXL_ASSERT((type == kVmlal) || (type == kVmlsl) || (type == kVqdmull)); 1638 UnimplementedDelegate(type); 1639 } Delegate(InstructionType type,InstructionCondRS,Condition,Register,SRegister)1640 virtual void Delegate(InstructionType type, 1641 InstructionCondRS /*instruction*/, 1642 Condition /*cond*/, 1643 Register /*rt*/, 1644 SRegister /*rn*/) { 1645 USE(type); 1646 VIXL_ASSERT((type == kVmov)); 1647 UnimplementedDelegate(type); 1648 } Delegate(InstructionType type,InstructionCondSR,Condition,SRegister,Register)1649 virtual void Delegate(InstructionType type, 1650 InstructionCondSR /*instruction*/, 1651 Condition /*cond*/, 1652 SRegister /*rn*/, 1653 Register /*rt*/) { 1654 USE(type); 1655 VIXL_ASSERT((type == kVmov)); 1656 UnimplementedDelegate(type); 1657 } Delegate(InstructionType type,InstructionCondRRD,Condition,Register,Register,DRegister)1658 virtual void Delegate(InstructionType type, 1659 InstructionCondRRD /*instruction*/, 1660 Condition /*cond*/, 1661 Register /*rt*/, 1662 Register /*rt2*/, 1663 DRegister /*rm*/) { 1664 USE(type); 1665 VIXL_ASSERT((type == kVmov)); 1666 UnimplementedDelegate(type); 1667 } Delegate(InstructionType type,InstructionCondDRR,Condition,DRegister,Register,Register)1668 virtual void Delegate(InstructionType type, 1669 InstructionCondDRR /*instruction*/, 1670 Condition /*cond*/, 1671 DRegister /*rm*/, 1672 Register /*rt*/, 1673 Register /*rt2*/) { 1674 USE(type); 1675 VIXL_ASSERT((type == kVmov)); 1676 UnimplementedDelegate(type); 1677 } Delegate(InstructionType type,InstructionCondRRSS,Condition,Register,Register,SRegister,SRegister)1678 virtual void Delegate(InstructionType type, 1679 InstructionCondRRSS /*instruction*/, 1680 Condition /*cond*/, 1681 Register /*rt*/, 1682 Register /*rt2*/, 1683 SRegister /*rm*/, 1684 SRegister /*rm1*/) { 1685 USE(type); 1686 VIXL_ASSERT((type == kVmov)); 1687 UnimplementedDelegate(type); 1688 } Delegate(InstructionType type,InstructionCondSSRR,Condition,SRegister,SRegister,Register,Register)1689 virtual void Delegate(InstructionType type, 1690 InstructionCondSSRR /*instruction*/, 1691 Condition /*cond*/, 1692 SRegister /*rm*/, 1693 SRegister /*rm1*/, 1694 Register /*rt*/, 1695 Register /*rt2*/) { 1696 USE(type); 1697 VIXL_ASSERT((type == kVmov)); 1698 UnimplementedDelegate(type); 1699 } Delegate(InstructionType type,InstructionCondDtDxR,Condition,DataType,DRegisterLane,Register)1700 virtual void Delegate(InstructionType type, 1701 InstructionCondDtDxR /*instruction*/, 1702 Condition /*cond*/, 1703 DataType /*dt*/, 1704 DRegisterLane /*rd*/, 1705 Register /*rt*/) { 1706 USE(type); 1707 VIXL_ASSERT((type == kVmov)); 1708 UnimplementedDelegate(type); 1709 } Delegate(InstructionType type,InstructionCondDtQQop,Condition,DataType,QRegister,const QOperand &)1710 virtual void Delegate(InstructionType type, 1711 InstructionCondDtQQop /*instruction*/, 1712 Condition /*cond*/, 1713 DataType /*dt*/, 1714 QRegister /*rd*/, 1715 const QOperand& /*operand*/) { 1716 USE(type); 1717 VIXL_ASSERT((type == kVmov) || (type == kVmvn)); 1718 UnimplementedDelegate(type); 1719 } Delegate(InstructionType type,InstructionCondDtRDx,Condition,DataType,Register,DRegisterLane)1720 virtual void Delegate(InstructionType type, 1721 InstructionCondDtRDx /*instruction*/, 1722 Condition /*cond*/, 1723 DataType /*dt*/, 1724 Register /*rt*/, 1725 DRegisterLane /*rn*/) { 1726 USE(type); 1727 VIXL_ASSERT((type == kVmov)); 1728 UnimplementedDelegate(type); 1729 } Delegate(InstructionType type,InstructionCondDtQD,Condition,DataType,QRegister,DRegister)1730 virtual void Delegate(InstructionType type, 1731 InstructionCondDtQD /*instruction*/, 1732 Condition /*cond*/, 1733 DataType /*dt*/, 1734 QRegister /*rd*/, 1735 DRegister /*rm*/) { 1736 USE(type); 1737 VIXL_ASSERT((type == kVmovl)); 1738 UnimplementedDelegate(type); 1739 } Delegate(InstructionType type,InstructionCondDtDQ,Condition,DataType,DRegister,QRegister)1740 virtual void Delegate(InstructionType type, 1741 InstructionCondDtDQ /*instruction*/, 1742 Condition /*cond*/, 1743 DataType /*dt*/, 1744 DRegister /*rd*/, 1745 QRegister /*rm*/) { 1746 USE(type); 1747 VIXL_ASSERT((type == kVmovn) || (type == kVqmovn) || (type == kVqmovun)); 1748 UnimplementedDelegate(type); 1749 } Delegate(InstructionType type,InstructionCondRoaSfp,Condition,RegisterOrAPSR_nzcv,SpecialFPRegister)1750 virtual void Delegate(InstructionType type, 1751 InstructionCondRoaSfp /*instruction*/, 1752 Condition /*cond*/, 1753 RegisterOrAPSR_nzcv /*rt*/, 1754 SpecialFPRegister /*spec_reg*/) { 1755 USE(type); 1756 VIXL_ASSERT((type == kVmrs)); 1757 UnimplementedDelegate(type); 1758 } Delegate(InstructionType type,InstructionCondSfpR,Condition,SpecialFPRegister,Register)1759 virtual void Delegate(InstructionType type, 1760 InstructionCondSfpR /*instruction*/, 1761 Condition /*cond*/, 1762 SpecialFPRegister /*spec_reg*/, 1763 Register /*rt*/) { 1764 USE(type); 1765 VIXL_ASSERT((type == kVmsr)); 1766 UnimplementedDelegate(type); 1767 } Delegate(InstructionType type,InstructionCondDtDDIr,Condition,DataType,DRegister,DRegister,DRegister,unsigned)1768 virtual void Delegate(InstructionType type, 1769 InstructionCondDtDDIr /*instruction*/, 1770 Condition /*cond*/, 1771 DataType /*dt*/, 1772 DRegister /*rd*/, 1773 DRegister /*rn*/, 1774 DRegister /*dm*/, 1775 unsigned /*index*/) { 1776 USE(type); 1777 VIXL_ASSERT((type == kVmul)); 1778 UnimplementedDelegate(type); 1779 } Delegate(InstructionType type,InstructionCondDtQQIr,Condition,DataType,QRegister,QRegister,DRegister,unsigned)1780 virtual void Delegate(InstructionType type, 1781 InstructionCondDtQQIr /*instruction*/, 1782 Condition /*cond*/, 1783 DataType /*dt*/, 1784 QRegister /*rd*/, 1785 QRegister /*rn*/, 1786 DRegister /*dm*/, 1787 unsigned /*index*/) { 1788 USE(type); 1789 VIXL_ASSERT((type == kVmul)); 1790 UnimplementedDelegate(type); 1791 } Delegate(InstructionType type,InstructionCondDtQDIr,Condition,DataType,QRegister,DRegister,DRegister,unsigned)1792 virtual void Delegate(InstructionType type, 1793 InstructionCondDtQDIr /*instruction*/, 1794 Condition /*cond*/, 1795 DataType /*dt*/, 1796 QRegister /*rd*/, 1797 DRegister /*rn*/, 1798 DRegister /*dm*/, 1799 unsigned /*index*/) { 1800 USE(type); 1801 VIXL_ASSERT((type == kVmull) || (type == kVqdmlal) || (type == kVqdmlsl)); 1802 UnimplementedDelegate(type); 1803 } Delegate(InstructionType type,InstructionCondDtDrl,Condition,DataType,DRegisterList)1804 virtual void Delegate(InstructionType type, 1805 InstructionCondDtDrl /*instruction*/, 1806 Condition /*cond*/, 1807 DataType /*dt*/, 1808 DRegisterList /*dreglist*/) { 1809 USE(type); 1810 VIXL_ASSERT((type == kVpop) || (type == kVpush)); 1811 UnimplementedDelegate(type); 1812 } Delegate(InstructionType type,InstructionCondDtSrl,Condition,DataType,SRegisterList)1813 virtual void Delegate(InstructionType type, 1814 InstructionCondDtSrl /*instruction*/, 1815 Condition /*cond*/, 1816 DataType /*dt*/, 1817 SRegisterList /*sreglist*/) { 1818 USE(type); 1819 VIXL_ASSERT((type == kVpop) || (type == kVpush)); 1820 UnimplementedDelegate(type); 1821 } Delegate(InstructionType type,InstructionCondDtDQQop,Condition,DataType,DRegister,QRegister,const QOperand &)1822 virtual void Delegate(InstructionType type, 1823 InstructionCondDtDQQop /*instruction*/, 1824 Condition /*cond*/, 1825 DataType /*dt*/, 1826 DRegister /*rd*/, 1827 QRegister /*rm*/, 1828 const QOperand& /*operand*/) { 1829 USE(type); 1830 VIXL_ASSERT((type == kVqrshrn) || (type == kVqrshrun) || 1831 (type == kVqshrn) || (type == kVqshrun) || (type == kVrshrn) || 1832 (type == kVshrn)); 1833 UnimplementedDelegate(type); 1834 } Delegate(InstructionType type,InstructionDtDD,DataType,DRegister,DRegister)1835 virtual void Delegate(InstructionType type, 1836 InstructionDtDD /*instruction*/, 1837 DataType /*dt*/, 1838 DRegister /*rd*/, 1839 DRegister /*rm*/) { 1840 USE(type); 1841 VIXL_ASSERT((type == kVrinta) || (type == kVrintm) || (type == kVrintn) || 1842 (type == kVrintp)); 1843 UnimplementedDelegate(type); 1844 } Delegate(InstructionType type,InstructionDtSS,DataType,SRegister,SRegister)1845 virtual void Delegate(InstructionType type, 1846 InstructionDtSS /*instruction*/, 1847 DataType /*dt*/, 1848 SRegister /*rd*/, 1849 SRegister /*rm*/) { 1850 USE(type); 1851 VIXL_ASSERT((type == kVrinta) || (type == kVrintm) || (type == kVrintn) || 1852 (type == kVrintp)); 1853 UnimplementedDelegate(type); 1854 } Delegate(InstructionType type,InstructionCondDtQDDop,Condition,DataType,QRegister,DRegister,const DOperand &)1855 virtual void Delegate(InstructionType type, 1856 InstructionCondDtQDDop /*instruction*/, 1857 Condition /*cond*/, 1858 DataType /*dt*/, 1859 QRegister /*rd*/, 1860 DRegister /*rm*/, 1861 const DOperand& /*operand*/) { 1862 USE(type); 1863 VIXL_ASSERT((type == kVshll)); 1864 UnimplementedDelegate(type); 1865 } Delegate(InstructionType type,InstructionCondDtDNrlD,Condition,DataType,DRegister,const NeonRegisterList &,DRegister)1866 virtual void Delegate(InstructionType type, 1867 InstructionCondDtDNrlD /*instruction*/, 1868 Condition /*cond*/, 1869 DataType /*dt*/, 1870 DRegister /*rd*/, 1871 const NeonRegisterList& /*nreglist*/, 1872 DRegister /*rm*/) { 1873 USE(type); 1874 VIXL_ASSERT((type == kVtbl) || (type == kVtbx)); 1875 UnimplementedDelegate(type); 1876 } 1877 1878 void adc(Condition cond, 1879 EncodingSize size, 1880 Register rd, 1881 Register rn, 1882 const Operand& operand); adc(Register rd,Register rn,const Operand & operand)1883 void adc(Register rd, Register rn, const Operand& operand) { 1884 adc(al, Best, rd, rn, operand); 1885 } adc(Condition cond,Register rd,Register rn,const Operand & operand)1886 void adc(Condition cond, Register rd, Register rn, const Operand& operand) { 1887 adc(cond, Best, rd, rn, operand); 1888 } adc(EncodingSize size,Register rd,Register rn,const Operand & operand)1889 void adc(EncodingSize size, 1890 Register rd, 1891 Register rn, 1892 const Operand& operand) { 1893 adc(al, size, rd, rn, operand); 1894 } 1895 1896 void adcs(Condition cond, 1897 EncodingSize size, 1898 Register rd, 1899 Register rn, 1900 const Operand& operand); adcs(Register rd,Register rn,const Operand & operand)1901 void adcs(Register rd, Register rn, const Operand& operand) { 1902 adcs(al, Best, rd, rn, operand); 1903 } adcs(Condition cond,Register rd,Register rn,const Operand & operand)1904 void adcs(Condition cond, Register rd, Register rn, const Operand& operand) { 1905 adcs(cond, Best, rd, rn, operand); 1906 } adcs(EncodingSize size,Register rd,Register rn,const Operand & operand)1907 void adcs(EncodingSize size, 1908 Register rd, 1909 Register rn, 1910 const Operand& operand) { 1911 adcs(al, size, rd, rn, operand); 1912 } 1913 1914 void add(Condition cond, 1915 EncodingSize size, 1916 Register rd, 1917 Register rn, 1918 const Operand& operand); add(Register rd,Register rn,const Operand & operand)1919 void add(Register rd, Register rn, const Operand& operand) { 1920 add(al, Best, rd, rn, operand); 1921 } add(Condition cond,Register rd,Register rn,const Operand & operand)1922 void add(Condition cond, Register rd, Register rn, const Operand& operand) { 1923 add(cond, Best, rd, rn, operand); 1924 } add(EncodingSize size,Register rd,Register rn,const Operand & operand)1925 void add(EncodingSize size, 1926 Register rd, 1927 Register rn, 1928 const Operand& operand) { 1929 add(al, size, rd, rn, operand); 1930 } 1931 1932 void add(Condition cond, Register rd, const Operand& operand); add(Register rd,const Operand & operand)1933 void add(Register rd, const Operand& operand) { add(al, rd, operand); } 1934 1935 void adds(Condition cond, 1936 EncodingSize size, 1937 Register rd, 1938 Register rn, 1939 const Operand& operand); adds(Register rd,Register rn,const Operand & operand)1940 void adds(Register rd, Register rn, const Operand& operand) { 1941 adds(al, Best, rd, rn, operand); 1942 } adds(Condition cond,Register rd,Register rn,const Operand & operand)1943 void adds(Condition cond, Register rd, Register rn, const Operand& operand) { 1944 adds(cond, Best, rd, rn, operand); 1945 } adds(EncodingSize size,Register rd,Register rn,const Operand & operand)1946 void adds(EncodingSize size, 1947 Register rd, 1948 Register rn, 1949 const Operand& operand) { 1950 adds(al, size, rd, rn, operand); 1951 } 1952 1953 void adds(Register rd, const Operand& operand); 1954 1955 void addw(Condition cond, Register rd, Register rn, const Operand& operand); addw(Register rd,Register rn,const Operand & operand)1956 void addw(Register rd, Register rn, const Operand& operand) { 1957 addw(al, rd, rn, operand); 1958 } 1959 1960 void adr(Condition cond, EncodingSize size, Register rd, Location* location); 1961 bool adr_info(Condition cond, 1962 EncodingSize size, 1963 Register rd, 1964 Location* location, 1965 const struct ReferenceInfo** info); adr(Register rd,Location * location)1966 void adr(Register rd, Location* location) { adr(al, Best, rd, location); } adr(Condition cond,Register rd,Location * location)1967 void adr(Condition cond, Register rd, Location* location) { 1968 adr(cond, Best, rd, location); 1969 } adr(EncodingSize size,Register rd,Location * location)1970 void adr(EncodingSize size, Register rd, Location* location) { 1971 adr(al, size, rd, location); 1972 } 1973 1974 void and_(Condition cond, 1975 EncodingSize size, 1976 Register rd, 1977 Register rn, 1978 const Operand& operand); and_(Register rd,Register rn,const Operand & operand)1979 void and_(Register rd, Register rn, const Operand& operand) { 1980 and_(al, Best, rd, rn, operand); 1981 } and_(Condition cond,Register rd,Register rn,const Operand & operand)1982 void and_(Condition cond, Register rd, Register rn, const Operand& operand) { 1983 and_(cond, Best, rd, rn, operand); 1984 } and_(EncodingSize size,Register rd,Register rn,const Operand & operand)1985 void and_(EncodingSize size, 1986 Register rd, 1987 Register rn, 1988 const Operand& operand) { 1989 and_(al, size, rd, rn, operand); 1990 } 1991 1992 void ands(Condition cond, 1993 EncodingSize size, 1994 Register rd, 1995 Register rn, 1996 const Operand& operand); ands(Register rd,Register rn,const Operand & operand)1997 void ands(Register rd, Register rn, const Operand& operand) { 1998 ands(al, Best, rd, rn, operand); 1999 } ands(Condition cond,Register rd,Register rn,const Operand & operand)2000 void ands(Condition cond, Register rd, Register rn, const Operand& operand) { 2001 ands(cond, Best, rd, rn, operand); 2002 } ands(EncodingSize size,Register rd,Register rn,const Operand & operand)2003 void ands(EncodingSize size, 2004 Register rd, 2005 Register rn, 2006 const Operand& operand) { 2007 ands(al, size, rd, rn, operand); 2008 } 2009 2010 void asr(Condition cond, 2011 EncodingSize size, 2012 Register rd, 2013 Register rm, 2014 const Operand& operand); asr(Register rd,Register rm,const Operand & operand)2015 void asr(Register rd, Register rm, const Operand& operand) { 2016 asr(al, Best, rd, rm, operand); 2017 } asr(Condition cond,Register rd,Register rm,const Operand & operand)2018 void asr(Condition cond, Register rd, Register rm, const Operand& operand) { 2019 asr(cond, Best, rd, rm, operand); 2020 } asr(EncodingSize size,Register rd,Register rm,const Operand & operand)2021 void asr(EncodingSize size, 2022 Register rd, 2023 Register rm, 2024 const Operand& operand) { 2025 asr(al, size, rd, rm, operand); 2026 } 2027 2028 void asrs(Condition cond, 2029 EncodingSize size, 2030 Register rd, 2031 Register rm, 2032 const Operand& operand); asrs(Register rd,Register rm,const Operand & operand)2033 void asrs(Register rd, Register rm, const Operand& operand) { 2034 asrs(al, Best, rd, rm, operand); 2035 } asrs(Condition cond,Register rd,Register rm,const Operand & operand)2036 void asrs(Condition cond, Register rd, Register rm, const Operand& operand) { 2037 asrs(cond, Best, rd, rm, operand); 2038 } asrs(EncodingSize size,Register rd,Register rm,const Operand & operand)2039 void asrs(EncodingSize size, 2040 Register rd, 2041 Register rm, 2042 const Operand& operand) { 2043 asrs(al, size, rd, rm, operand); 2044 } 2045 2046 void b(Condition cond, EncodingSize size, Location* location); 2047 bool b_info(Condition cond, 2048 EncodingSize size, 2049 Location* location, 2050 const struct ReferenceInfo** info); b(Location * location)2051 void b(Location* location) { b(al, Best, location); } b(Condition cond,Location * location)2052 void b(Condition cond, Location* location) { b(cond, Best, location); } b(EncodingSize size,Location * location)2053 void b(EncodingSize size, Location* location) { b(al, size, location); } 2054 2055 void bfc(Condition cond, Register rd, uint32_t lsb, uint32_t width); bfc(Register rd,uint32_t lsb,uint32_t width)2056 void bfc(Register rd, uint32_t lsb, uint32_t width) { 2057 bfc(al, rd, lsb, width); 2058 } 2059 2060 void bfi( 2061 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width); bfi(Register rd,Register rn,uint32_t lsb,uint32_t width)2062 void bfi(Register rd, Register rn, uint32_t lsb, uint32_t width) { 2063 bfi(al, rd, rn, lsb, width); 2064 } 2065 2066 void bic(Condition cond, 2067 EncodingSize size, 2068 Register rd, 2069 Register rn, 2070 const Operand& operand); bic(Register rd,Register rn,const Operand & operand)2071 void bic(Register rd, Register rn, const Operand& operand) { 2072 bic(al, Best, rd, rn, operand); 2073 } bic(Condition cond,Register rd,Register rn,const Operand & operand)2074 void bic(Condition cond, Register rd, Register rn, const Operand& operand) { 2075 bic(cond, Best, rd, rn, operand); 2076 } bic(EncodingSize size,Register rd,Register rn,const Operand & operand)2077 void bic(EncodingSize size, 2078 Register rd, 2079 Register rn, 2080 const Operand& operand) { 2081 bic(al, size, rd, rn, operand); 2082 } 2083 2084 void bics(Condition cond, 2085 EncodingSize size, 2086 Register rd, 2087 Register rn, 2088 const Operand& operand); bics(Register rd,Register rn,const Operand & operand)2089 void bics(Register rd, Register rn, const Operand& operand) { 2090 bics(al, Best, rd, rn, operand); 2091 } bics(Condition cond,Register rd,Register rn,const Operand & operand)2092 void bics(Condition cond, Register rd, Register rn, const Operand& operand) { 2093 bics(cond, Best, rd, rn, operand); 2094 } bics(EncodingSize size,Register rd,Register rn,const Operand & operand)2095 void bics(EncodingSize size, 2096 Register rd, 2097 Register rn, 2098 const Operand& operand) { 2099 bics(al, size, rd, rn, operand); 2100 } 2101 2102 void bkpt(Condition cond, uint32_t imm); bkpt(uint32_t imm)2103 void bkpt(uint32_t imm) { bkpt(al, imm); } 2104 2105 void bl(Condition cond, Location* location); 2106 bool bl_info(Condition cond, 2107 Location* location, 2108 const struct ReferenceInfo** info); bl(Location * location)2109 void bl(Location* location) { bl(al, location); } 2110 2111 void blx(Condition cond, Location* location); 2112 bool blx_info(Condition cond, 2113 Location* location, 2114 const struct ReferenceInfo** info); blx(Location * location)2115 void blx(Location* location) { blx(al, location); } 2116 2117 void blx(Condition cond, Register rm); blx(Register rm)2118 void blx(Register rm) { blx(al, rm); } 2119 2120 void bx(Condition cond, Register rm); bx(Register rm)2121 void bx(Register rm) { bx(al, rm); } 2122 2123 void bxj(Condition cond, Register rm); bxj(Register rm)2124 void bxj(Register rm) { bxj(al, rm); } 2125 2126 void cbnz(Register rn, Location* location); 2127 bool cbnz_info(Register rn, 2128 Location* location, 2129 const struct ReferenceInfo** info); 2130 2131 void cbz(Register rn, Location* location); 2132 bool cbz_info(Register rn, 2133 Location* location, 2134 const struct ReferenceInfo** info); 2135 2136 void clrex(Condition cond); clrex()2137 void clrex() { clrex(al); } 2138 2139 void clz(Condition cond, Register rd, Register rm); clz(Register rd,Register rm)2140 void clz(Register rd, Register rm) { clz(al, rd, rm); } 2141 2142 void cmn(Condition cond, 2143 EncodingSize size, 2144 Register rn, 2145 const Operand& operand); cmn(Register rn,const Operand & operand)2146 void cmn(Register rn, const Operand& operand) { cmn(al, Best, rn, operand); } cmn(Condition cond,Register rn,const Operand & operand)2147 void cmn(Condition cond, Register rn, const Operand& operand) { 2148 cmn(cond, Best, rn, operand); 2149 } cmn(EncodingSize size,Register rn,const Operand & operand)2150 void cmn(EncodingSize size, Register rn, const Operand& operand) { 2151 cmn(al, size, rn, operand); 2152 } 2153 2154 void cmp(Condition cond, 2155 EncodingSize size, 2156 Register rn, 2157 const Operand& operand); cmp(Register rn,const Operand & operand)2158 void cmp(Register rn, const Operand& operand) { cmp(al, Best, rn, operand); } cmp(Condition cond,Register rn,const Operand & operand)2159 void cmp(Condition cond, Register rn, const Operand& operand) { 2160 cmp(cond, Best, rn, operand); 2161 } cmp(EncodingSize size,Register rn,const Operand & operand)2162 void cmp(EncodingSize size, Register rn, const Operand& operand) { 2163 cmp(al, size, rn, operand); 2164 } 2165 2166 void crc32b(Condition cond, Register rd, Register rn, Register rm); crc32b(Register rd,Register rn,Register rm)2167 void crc32b(Register rd, Register rn, Register rm) { crc32b(al, rd, rn, rm); } 2168 2169 void crc32cb(Condition cond, Register rd, Register rn, Register rm); crc32cb(Register rd,Register rn,Register rm)2170 void crc32cb(Register rd, Register rn, Register rm) { 2171 crc32cb(al, rd, rn, rm); 2172 } 2173 2174 void crc32ch(Condition cond, Register rd, Register rn, Register rm); crc32ch(Register rd,Register rn,Register rm)2175 void crc32ch(Register rd, Register rn, Register rm) { 2176 crc32ch(al, rd, rn, rm); 2177 } 2178 2179 void crc32cw(Condition cond, Register rd, Register rn, Register rm); crc32cw(Register rd,Register rn,Register rm)2180 void crc32cw(Register rd, Register rn, Register rm) { 2181 crc32cw(al, rd, rn, rm); 2182 } 2183 2184 void crc32h(Condition cond, Register rd, Register rn, Register rm); crc32h(Register rd,Register rn,Register rm)2185 void crc32h(Register rd, Register rn, Register rm) { crc32h(al, rd, rn, rm); } 2186 2187 void crc32w(Condition cond, Register rd, Register rn, Register rm); crc32w(Register rd,Register rn,Register rm)2188 void crc32w(Register rd, Register rn, Register rm) { crc32w(al, rd, rn, rm); } 2189 2190 void dmb(Condition cond, MemoryBarrier option); dmb(MemoryBarrier option)2191 void dmb(MemoryBarrier option) { dmb(al, option); } 2192 2193 void dsb(Condition cond, MemoryBarrier option); dsb(MemoryBarrier option)2194 void dsb(MemoryBarrier option) { dsb(al, option); } 2195 2196 void eor(Condition cond, 2197 EncodingSize size, 2198 Register rd, 2199 Register rn, 2200 const Operand& operand); eor(Register rd,Register rn,const Operand & operand)2201 void eor(Register rd, Register rn, const Operand& operand) { 2202 eor(al, Best, rd, rn, operand); 2203 } eor(Condition cond,Register rd,Register rn,const Operand & operand)2204 void eor(Condition cond, Register rd, Register rn, const Operand& operand) { 2205 eor(cond, Best, rd, rn, operand); 2206 } eor(EncodingSize size,Register rd,Register rn,const Operand & operand)2207 void eor(EncodingSize size, 2208 Register rd, 2209 Register rn, 2210 const Operand& operand) { 2211 eor(al, size, rd, rn, operand); 2212 } 2213 2214 void eors(Condition cond, 2215 EncodingSize size, 2216 Register rd, 2217 Register rn, 2218 const Operand& operand); eors(Register rd,Register rn,const Operand & operand)2219 void eors(Register rd, Register rn, const Operand& operand) { 2220 eors(al, Best, rd, rn, operand); 2221 } eors(Condition cond,Register rd,Register rn,const Operand & operand)2222 void eors(Condition cond, Register rd, Register rn, const Operand& operand) { 2223 eors(cond, Best, rd, rn, operand); 2224 } eors(EncodingSize size,Register rd,Register rn,const Operand & operand)2225 void eors(EncodingSize size, 2226 Register rd, 2227 Register rn, 2228 const Operand& operand) { 2229 eors(al, size, rd, rn, operand); 2230 } 2231 2232 void fldmdbx(Condition cond, 2233 Register rn, 2234 WriteBack write_back, 2235 DRegisterList dreglist); fldmdbx(Register rn,WriteBack write_back,DRegisterList dreglist)2236 void fldmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) { 2237 fldmdbx(al, rn, write_back, dreglist); 2238 } 2239 2240 void fldmiax(Condition cond, 2241 Register rn, 2242 WriteBack write_back, 2243 DRegisterList dreglist); fldmiax(Register rn,WriteBack write_back,DRegisterList dreglist)2244 void fldmiax(Register rn, WriteBack write_back, DRegisterList dreglist) { 2245 fldmiax(al, rn, write_back, dreglist); 2246 } 2247 2248 void fstmdbx(Condition cond, 2249 Register rn, 2250 WriteBack write_back, 2251 DRegisterList dreglist); fstmdbx(Register rn,WriteBack write_back,DRegisterList dreglist)2252 void fstmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) { 2253 fstmdbx(al, rn, write_back, dreglist); 2254 } 2255 2256 void fstmiax(Condition cond, 2257 Register rn, 2258 WriteBack write_back, 2259 DRegisterList dreglist); fstmiax(Register rn,WriteBack write_back,DRegisterList dreglist)2260 void fstmiax(Register rn, WriteBack write_back, DRegisterList dreglist) { 2261 fstmiax(al, rn, write_back, dreglist); 2262 } 2263 2264 void hlt(Condition cond, uint32_t imm); hlt(uint32_t imm)2265 void hlt(uint32_t imm) { hlt(al, imm); } 2266 2267 void hvc(Condition cond, uint32_t imm); hvc(uint32_t imm)2268 void hvc(uint32_t imm) { hvc(al, imm); } 2269 2270 void isb(Condition cond, MemoryBarrier option); isb(MemoryBarrier option)2271 void isb(MemoryBarrier option) { isb(al, option); } 2272 2273 void it(Condition cond, uint16_t mask); 2274 2275 void lda(Condition cond, Register rt, const MemOperand& operand); lda(Register rt,const MemOperand & operand)2276 void lda(Register rt, const MemOperand& operand) { lda(al, rt, operand); } 2277 2278 void ldab(Condition cond, Register rt, const MemOperand& operand); ldab(Register rt,const MemOperand & operand)2279 void ldab(Register rt, const MemOperand& operand) { ldab(al, rt, operand); } 2280 2281 void ldaex(Condition cond, Register rt, const MemOperand& operand); ldaex(Register rt,const MemOperand & operand)2282 void ldaex(Register rt, const MemOperand& operand) { ldaex(al, rt, operand); } 2283 2284 void ldaexb(Condition cond, Register rt, const MemOperand& operand); ldaexb(Register rt,const MemOperand & operand)2285 void ldaexb(Register rt, const MemOperand& operand) { 2286 ldaexb(al, rt, operand); 2287 } 2288 2289 void ldaexd(Condition cond, 2290 Register rt, 2291 Register rt2, 2292 const MemOperand& operand); ldaexd(Register rt,Register rt2,const MemOperand & operand)2293 void ldaexd(Register rt, Register rt2, const MemOperand& operand) { 2294 ldaexd(al, rt, rt2, operand); 2295 } 2296 2297 void ldaexh(Condition cond, Register rt, const MemOperand& operand); ldaexh(Register rt,const MemOperand & operand)2298 void ldaexh(Register rt, const MemOperand& operand) { 2299 ldaexh(al, rt, operand); 2300 } 2301 2302 void ldah(Condition cond, Register rt, const MemOperand& operand); ldah(Register rt,const MemOperand & operand)2303 void ldah(Register rt, const MemOperand& operand) { ldah(al, rt, operand); } 2304 2305 void ldm(Condition cond, 2306 EncodingSize size, 2307 Register rn, 2308 WriteBack write_back, 2309 RegisterList registers); ldm(Register rn,WriteBack write_back,RegisterList registers)2310 void ldm(Register rn, WriteBack write_back, RegisterList registers) { 2311 ldm(al, Best, rn, write_back, registers); 2312 } ldm(Condition cond,Register rn,WriteBack write_back,RegisterList registers)2313 void ldm(Condition cond, 2314 Register rn, 2315 WriteBack write_back, 2316 RegisterList registers) { 2317 ldm(cond, Best, rn, write_back, registers); 2318 } ldm(EncodingSize size,Register rn,WriteBack write_back,RegisterList registers)2319 void ldm(EncodingSize size, 2320 Register rn, 2321 WriteBack write_back, 2322 RegisterList registers) { 2323 ldm(al, size, rn, write_back, registers); 2324 } 2325 2326 void ldmda(Condition cond, 2327 Register rn, 2328 WriteBack write_back, 2329 RegisterList registers); ldmda(Register rn,WriteBack write_back,RegisterList registers)2330 void ldmda(Register rn, WriteBack write_back, RegisterList registers) { 2331 ldmda(al, rn, write_back, registers); 2332 } 2333 2334 void ldmdb(Condition cond, 2335 Register rn, 2336 WriteBack write_back, 2337 RegisterList registers); ldmdb(Register rn,WriteBack write_back,RegisterList registers)2338 void ldmdb(Register rn, WriteBack write_back, RegisterList registers) { 2339 ldmdb(al, rn, write_back, registers); 2340 } 2341 2342 void ldmea(Condition cond, 2343 Register rn, 2344 WriteBack write_back, 2345 RegisterList registers); ldmea(Register rn,WriteBack write_back,RegisterList registers)2346 void ldmea(Register rn, WriteBack write_back, RegisterList registers) { 2347 ldmea(al, rn, write_back, registers); 2348 } 2349 2350 void ldmed(Condition cond, 2351 Register rn, 2352 WriteBack write_back, 2353 RegisterList registers); ldmed(Register rn,WriteBack write_back,RegisterList registers)2354 void ldmed(Register rn, WriteBack write_back, RegisterList registers) { 2355 ldmed(al, rn, write_back, registers); 2356 } 2357 2358 void ldmfa(Condition cond, 2359 Register rn, 2360 WriteBack write_back, 2361 RegisterList registers); ldmfa(Register rn,WriteBack write_back,RegisterList registers)2362 void ldmfa(Register rn, WriteBack write_back, RegisterList registers) { 2363 ldmfa(al, rn, write_back, registers); 2364 } 2365 2366 void ldmfd(Condition cond, 2367 EncodingSize size, 2368 Register rn, 2369 WriteBack write_back, 2370 RegisterList registers); ldmfd(Register rn,WriteBack write_back,RegisterList registers)2371 void ldmfd(Register rn, WriteBack write_back, RegisterList registers) { 2372 ldmfd(al, Best, rn, write_back, registers); 2373 } ldmfd(Condition cond,Register rn,WriteBack write_back,RegisterList registers)2374 void ldmfd(Condition cond, 2375 Register rn, 2376 WriteBack write_back, 2377 RegisterList registers) { 2378 ldmfd(cond, Best, rn, write_back, registers); 2379 } ldmfd(EncodingSize size,Register rn,WriteBack write_back,RegisterList registers)2380 void ldmfd(EncodingSize size, 2381 Register rn, 2382 WriteBack write_back, 2383 RegisterList registers) { 2384 ldmfd(al, size, rn, write_back, registers); 2385 } 2386 2387 void ldmib(Condition cond, 2388 Register rn, 2389 WriteBack write_back, 2390 RegisterList registers); ldmib(Register rn,WriteBack write_back,RegisterList registers)2391 void ldmib(Register rn, WriteBack write_back, RegisterList registers) { 2392 ldmib(al, rn, write_back, registers); 2393 } 2394 2395 void ldr(Condition cond, 2396 EncodingSize size, 2397 Register rt, 2398 const MemOperand& operand); ldr(Register rt,const MemOperand & operand)2399 void ldr(Register rt, const MemOperand& operand) { 2400 ldr(al, Best, rt, operand); 2401 } ldr(Condition cond,Register rt,const MemOperand & operand)2402 void ldr(Condition cond, Register rt, const MemOperand& operand) { 2403 ldr(cond, Best, rt, operand); 2404 } ldr(EncodingSize size,Register rt,const MemOperand & operand)2405 void ldr(EncodingSize size, Register rt, const MemOperand& operand) { 2406 ldr(al, size, rt, operand); 2407 } 2408 2409 void ldr(Condition cond, EncodingSize size, Register rt, Location* location); 2410 bool ldr_info(Condition cond, 2411 EncodingSize size, 2412 Register rt, 2413 Location* location, 2414 const struct ReferenceInfo** info); ldr(Register rt,Location * location)2415 void ldr(Register rt, Location* location) { ldr(al, Best, rt, location); } ldr(Condition cond,Register rt,Location * location)2416 void ldr(Condition cond, Register rt, Location* location) { 2417 ldr(cond, Best, rt, location); 2418 } ldr(EncodingSize size,Register rt,Location * location)2419 void ldr(EncodingSize size, Register rt, Location* location) { 2420 ldr(al, size, rt, location); 2421 } 2422 2423 void ldrb(Condition cond, 2424 EncodingSize size, 2425 Register rt, 2426 const MemOperand& operand); ldrb(Register rt,const MemOperand & operand)2427 void ldrb(Register rt, const MemOperand& operand) { 2428 ldrb(al, Best, rt, operand); 2429 } ldrb(Condition cond,Register rt,const MemOperand & operand)2430 void ldrb(Condition cond, Register rt, const MemOperand& operand) { 2431 ldrb(cond, Best, rt, operand); 2432 } ldrb(EncodingSize size,Register rt,const MemOperand & operand)2433 void ldrb(EncodingSize size, Register rt, const MemOperand& operand) { 2434 ldrb(al, size, rt, operand); 2435 } 2436 2437 void ldrb(Condition cond, Register rt, Location* location); 2438 bool ldrb_info(Condition cond, 2439 Register rt, 2440 Location* location, 2441 const struct ReferenceInfo** info); ldrb(Register rt,Location * location)2442 void ldrb(Register rt, Location* location) { ldrb(al, rt, location); } 2443 2444 void ldrd(Condition cond, 2445 Register rt, 2446 Register rt2, 2447 const MemOperand& operand); ldrd(Register rt,Register rt2,const MemOperand & operand)2448 void ldrd(Register rt, Register rt2, const MemOperand& operand) { 2449 ldrd(al, rt, rt2, operand); 2450 } 2451 2452 void ldrd(Condition cond, Register rt, Register rt2, Location* location); 2453 bool ldrd_info(Condition cond, 2454 Register rt, 2455 Register rt2, 2456 Location* location, 2457 const struct ReferenceInfo** info); ldrd(Register rt,Register rt2,Location * location)2458 void ldrd(Register rt, Register rt2, Location* location) { 2459 ldrd(al, rt, rt2, location); 2460 } 2461 2462 void ldrex(Condition cond, Register rt, const MemOperand& operand); ldrex(Register rt,const MemOperand & operand)2463 void ldrex(Register rt, const MemOperand& operand) { ldrex(al, rt, operand); } 2464 2465 void ldrexb(Condition cond, Register rt, const MemOperand& operand); ldrexb(Register rt,const MemOperand & operand)2466 void ldrexb(Register rt, const MemOperand& operand) { 2467 ldrexb(al, rt, operand); 2468 } 2469 2470 void ldrexd(Condition cond, 2471 Register rt, 2472 Register rt2, 2473 const MemOperand& operand); ldrexd(Register rt,Register rt2,const MemOperand & operand)2474 void ldrexd(Register rt, Register rt2, const MemOperand& operand) { 2475 ldrexd(al, rt, rt2, operand); 2476 } 2477 2478 void ldrexh(Condition cond, Register rt, const MemOperand& operand); ldrexh(Register rt,const MemOperand & operand)2479 void ldrexh(Register rt, const MemOperand& operand) { 2480 ldrexh(al, rt, operand); 2481 } 2482 2483 void ldrh(Condition cond, 2484 EncodingSize size, 2485 Register rt, 2486 const MemOperand& operand); ldrh(Register rt,const MemOperand & operand)2487 void ldrh(Register rt, const MemOperand& operand) { 2488 ldrh(al, Best, rt, operand); 2489 } ldrh(Condition cond,Register rt,const MemOperand & operand)2490 void ldrh(Condition cond, Register rt, const MemOperand& operand) { 2491 ldrh(cond, Best, rt, operand); 2492 } ldrh(EncodingSize size,Register rt,const MemOperand & operand)2493 void ldrh(EncodingSize size, Register rt, const MemOperand& operand) { 2494 ldrh(al, size, rt, operand); 2495 } 2496 2497 void ldrh(Condition cond, Register rt, Location* location); 2498 bool ldrh_info(Condition cond, 2499 Register rt, 2500 Location* location, 2501 const struct ReferenceInfo** info); ldrh(Register rt,Location * location)2502 void ldrh(Register rt, Location* location) { ldrh(al, rt, location); } 2503 2504 void ldrsb(Condition cond, 2505 EncodingSize size, 2506 Register rt, 2507 const MemOperand& operand); ldrsb(Register rt,const MemOperand & operand)2508 void ldrsb(Register rt, const MemOperand& operand) { 2509 ldrsb(al, Best, rt, operand); 2510 } ldrsb(Condition cond,Register rt,const MemOperand & operand)2511 void ldrsb(Condition cond, Register rt, const MemOperand& operand) { 2512 ldrsb(cond, Best, rt, operand); 2513 } ldrsb(EncodingSize size,Register rt,const MemOperand & operand)2514 void ldrsb(EncodingSize size, Register rt, const MemOperand& operand) { 2515 ldrsb(al, size, rt, operand); 2516 } 2517 2518 void ldrsb(Condition cond, Register rt, Location* location); 2519 bool ldrsb_info(Condition cond, 2520 Register rt, 2521 Location* location, 2522 const struct ReferenceInfo** info); ldrsb(Register rt,Location * location)2523 void ldrsb(Register rt, Location* location) { ldrsb(al, rt, location); } 2524 2525 void ldrsh(Condition cond, 2526 EncodingSize size, 2527 Register rt, 2528 const MemOperand& operand); ldrsh(Register rt,const MemOperand & operand)2529 void ldrsh(Register rt, const MemOperand& operand) { 2530 ldrsh(al, Best, rt, operand); 2531 } ldrsh(Condition cond,Register rt,const MemOperand & operand)2532 void ldrsh(Condition cond, Register rt, const MemOperand& operand) { 2533 ldrsh(cond, Best, rt, operand); 2534 } ldrsh(EncodingSize size,Register rt,const MemOperand & operand)2535 void ldrsh(EncodingSize size, Register rt, const MemOperand& operand) { 2536 ldrsh(al, size, rt, operand); 2537 } 2538 2539 void ldrsh(Condition cond, Register rt, Location* location); 2540 bool ldrsh_info(Condition cond, 2541 Register rt, 2542 Location* location, 2543 const struct ReferenceInfo** info); ldrsh(Register rt,Location * location)2544 void ldrsh(Register rt, Location* location) { ldrsh(al, rt, location); } 2545 2546 void lsl(Condition cond, 2547 EncodingSize size, 2548 Register rd, 2549 Register rm, 2550 const Operand& operand); lsl(Register rd,Register rm,const Operand & operand)2551 void lsl(Register rd, Register rm, const Operand& operand) { 2552 lsl(al, Best, rd, rm, operand); 2553 } lsl(Condition cond,Register rd,Register rm,const Operand & operand)2554 void lsl(Condition cond, Register rd, Register rm, const Operand& operand) { 2555 lsl(cond, Best, rd, rm, operand); 2556 } lsl(EncodingSize size,Register rd,Register rm,const Operand & operand)2557 void lsl(EncodingSize size, 2558 Register rd, 2559 Register rm, 2560 const Operand& operand) { 2561 lsl(al, size, rd, rm, operand); 2562 } 2563 2564 void lsls(Condition cond, 2565 EncodingSize size, 2566 Register rd, 2567 Register rm, 2568 const Operand& operand); lsls(Register rd,Register rm,const Operand & operand)2569 void lsls(Register rd, Register rm, const Operand& operand) { 2570 lsls(al, Best, rd, rm, operand); 2571 } lsls(Condition cond,Register rd,Register rm,const Operand & operand)2572 void lsls(Condition cond, Register rd, Register rm, const Operand& operand) { 2573 lsls(cond, Best, rd, rm, operand); 2574 } lsls(EncodingSize size,Register rd,Register rm,const Operand & operand)2575 void lsls(EncodingSize size, 2576 Register rd, 2577 Register rm, 2578 const Operand& operand) { 2579 lsls(al, size, rd, rm, operand); 2580 } 2581 2582 void lsr(Condition cond, 2583 EncodingSize size, 2584 Register rd, 2585 Register rm, 2586 const Operand& operand); lsr(Register rd,Register rm,const Operand & operand)2587 void lsr(Register rd, Register rm, const Operand& operand) { 2588 lsr(al, Best, rd, rm, operand); 2589 } lsr(Condition cond,Register rd,Register rm,const Operand & operand)2590 void lsr(Condition cond, Register rd, Register rm, const Operand& operand) { 2591 lsr(cond, Best, rd, rm, operand); 2592 } lsr(EncodingSize size,Register rd,Register rm,const Operand & operand)2593 void lsr(EncodingSize size, 2594 Register rd, 2595 Register rm, 2596 const Operand& operand) { 2597 lsr(al, size, rd, rm, operand); 2598 } 2599 2600 void lsrs(Condition cond, 2601 EncodingSize size, 2602 Register rd, 2603 Register rm, 2604 const Operand& operand); lsrs(Register rd,Register rm,const Operand & operand)2605 void lsrs(Register rd, Register rm, const Operand& operand) { 2606 lsrs(al, Best, rd, rm, operand); 2607 } lsrs(Condition cond,Register rd,Register rm,const Operand & operand)2608 void lsrs(Condition cond, Register rd, Register rm, const Operand& operand) { 2609 lsrs(cond, Best, rd, rm, operand); 2610 } lsrs(EncodingSize size,Register rd,Register rm,const Operand & operand)2611 void lsrs(EncodingSize size, 2612 Register rd, 2613 Register rm, 2614 const Operand& operand) { 2615 lsrs(al, size, rd, rm, operand); 2616 } 2617 2618 void mla(Condition cond, Register rd, Register rn, Register rm, Register ra); mla(Register rd,Register rn,Register rm,Register ra)2619 void mla(Register rd, Register rn, Register rm, Register ra) { 2620 mla(al, rd, rn, rm, ra); 2621 } 2622 2623 void mlas(Condition cond, Register rd, Register rn, Register rm, Register ra); mlas(Register rd,Register rn,Register rm,Register ra)2624 void mlas(Register rd, Register rn, Register rm, Register ra) { 2625 mlas(al, rd, rn, rm, ra); 2626 } 2627 2628 void mls(Condition cond, Register rd, Register rn, Register rm, Register ra); mls(Register rd,Register rn,Register rm,Register ra)2629 void mls(Register rd, Register rn, Register rm, Register ra) { 2630 mls(al, rd, rn, rm, ra); 2631 } 2632 2633 void mov(Condition cond, 2634 EncodingSize size, 2635 Register rd, 2636 const Operand& operand); mov(Register rd,const Operand & operand)2637 void mov(Register rd, const Operand& operand) { mov(al, Best, rd, operand); } mov(Condition cond,Register rd,const Operand & operand)2638 void mov(Condition cond, Register rd, const Operand& operand) { 2639 mov(cond, Best, rd, operand); 2640 } mov(EncodingSize size,Register rd,const Operand & operand)2641 void mov(EncodingSize size, Register rd, const Operand& operand) { 2642 mov(al, size, rd, operand); 2643 } 2644 2645 void movs(Condition cond, 2646 EncodingSize size, 2647 Register rd, 2648 const Operand& operand); movs(Register rd,const Operand & operand)2649 void movs(Register rd, const Operand& operand) { 2650 movs(al, Best, rd, operand); 2651 } movs(Condition cond,Register rd,const Operand & operand)2652 void movs(Condition cond, Register rd, const Operand& operand) { 2653 movs(cond, Best, rd, operand); 2654 } movs(EncodingSize size,Register rd,const Operand & operand)2655 void movs(EncodingSize size, Register rd, const Operand& operand) { 2656 movs(al, size, rd, operand); 2657 } 2658 2659 void movt(Condition cond, Register rd, const Operand& operand); movt(Register rd,const Operand & operand)2660 void movt(Register rd, const Operand& operand) { movt(al, rd, operand); } 2661 2662 void movw(Condition cond, Register rd, const Operand& operand); movw(Register rd,const Operand & operand)2663 void movw(Register rd, const Operand& operand) { movw(al, rd, operand); } 2664 2665 void mrs(Condition cond, Register rd, SpecialRegister spec_reg); mrs(Register rd,SpecialRegister spec_reg)2666 void mrs(Register rd, SpecialRegister spec_reg) { mrs(al, rd, spec_reg); } 2667 2668 void msr(Condition cond, 2669 MaskedSpecialRegister spec_reg, 2670 const Operand& operand); msr(MaskedSpecialRegister spec_reg,const Operand & operand)2671 void msr(MaskedSpecialRegister spec_reg, const Operand& operand) { 2672 msr(al, spec_reg, operand); 2673 } 2674 2675 void mul( 2676 Condition cond, EncodingSize size, Register rd, Register rn, Register rm); mul(Register rd,Register rn,Register rm)2677 void mul(Register rd, Register rn, Register rm) { mul(al, Best, rd, rn, rm); } mul(Condition cond,Register rd,Register rn,Register rm)2678 void mul(Condition cond, Register rd, Register rn, Register rm) { 2679 mul(cond, Best, rd, rn, rm); 2680 } mul(EncodingSize size,Register rd,Register rn,Register rm)2681 void mul(EncodingSize size, Register rd, Register rn, Register rm) { 2682 mul(al, size, rd, rn, rm); 2683 } 2684 2685 void muls(Condition cond, Register rd, Register rn, Register rm); muls(Register rd,Register rn,Register rm)2686 void muls(Register rd, Register rn, Register rm) { muls(al, rd, rn, rm); } 2687 2688 void mvn(Condition cond, 2689 EncodingSize size, 2690 Register rd, 2691 const Operand& operand); mvn(Register rd,const Operand & operand)2692 void mvn(Register rd, const Operand& operand) { mvn(al, Best, rd, operand); } mvn(Condition cond,Register rd,const Operand & operand)2693 void mvn(Condition cond, Register rd, const Operand& operand) { 2694 mvn(cond, Best, rd, operand); 2695 } mvn(EncodingSize size,Register rd,const Operand & operand)2696 void mvn(EncodingSize size, Register rd, const Operand& operand) { 2697 mvn(al, size, rd, operand); 2698 } 2699 2700 void mvns(Condition cond, 2701 EncodingSize size, 2702 Register rd, 2703 const Operand& operand); mvns(Register rd,const Operand & operand)2704 void mvns(Register rd, const Operand& operand) { 2705 mvns(al, Best, rd, operand); 2706 } mvns(Condition cond,Register rd,const Operand & operand)2707 void mvns(Condition cond, Register rd, const Operand& operand) { 2708 mvns(cond, Best, rd, operand); 2709 } mvns(EncodingSize size,Register rd,const Operand & operand)2710 void mvns(EncodingSize size, Register rd, const Operand& operand) { 2711 mvns(al, size, rd, operand); 2712 } 2713 2714 void nop(Condition cond, EncodingSize size); nop()2715 void nop() { nop(al, Best); } nop(Condition cond)2716 void nop(Condition cond) { nop(cond, Best); } nop(EncodingSize size)2717 void nop(EncodingSize size) { nop(al, size); } 2718 2719 void orn(Condition cond, Register rd, Register rn, const Operand& operand); orn(Register rd,Register rn,const Operand & operand)2720 void orn(Register rd, Register rn, const Operand& operand) { 2721 orn(al, rd, rn, operand); 2722 } 2723 2724 void orns(Condition cond, Register rd, Register rn, const Operand& operand); orns(Register rd,Register rn,const Operand & operand)2725 void orns(Register rd, Register rn, const Operand& operand) { 2726 orns(al, rd, rn, operand); 2727 } 2728 2729 void orr(Condition cond, 2730 EncodingSize size, 2731 Register rd, 2732 Register rn, 2733 const Operand& operand); orr(Register rd,Register rn,const Operand & operand)2734 void orr(Register rd, Register rn, const Operand& operand) { 2735 orr(al, Best, rd, rn, operand); 2736 } orr(Condition cond,Register rd,Register rn,const Operand & operand)2737 void orr(Condition cond, Register rd, Register rn, const Operand& operand) { 2738 orr(cond, Best, rd, rn, operand); 2739 } orr(EncodingSize size,Register rd,Register rn,const Operand & operand)2740 void orr(EncodingSize size, 2741 Register rd, 2742 Register rn, 2743 const Operand& operand) { 2744 orr(al, size, rd, rn, operand); 2745 } 2746 2747 void orrs(Condition cond, 2748 EncodingSize size, 2749 Register rd, 2750 Register rn, 2751 const Operand& operand); orrs(Register rd,Register rn,const Operand & operand)2752 void orrs(Register rd, Register rn, const Operand& operand) { 2753 orrs(al, Best, rd, rn, operand); 2754 } orrs(Condition cond,Register rd,Register rn,const Operand & operand)2755 void orrs(Condition cond, Register rd, Register rn, const Operand& operand) { 2756 orrs(cond, Best, rd, rn, operand); 2757 } orrs(EncodingSize size,Register rd,Register rn,const Operand & operand)2758 void orrs(EncodingSize size, 2759 Register rd, 2760 Register rn, 2761 const Operand& operand) { 2762 orrs(al, size, rd, rn, operand); 2763 } 2764 2765 void pkhbt(Condition cond, Register rd, Register rn, const Operand& operand); pkhbt(Register rd,Register rn,const Operand & operand)2766 void pkhbt(Register rd, Register rn, const Operand& operand) { 2767 pkhbt(al, rd, rn, operand); 2768 } 2769 2770 void pkhtb(Condition cond, Register rd, Register rn, const Operand& operand); pkhtb(Register rd,Register rn,const Operand & operand)2771 void pkhtb(Register rd, Register rn, const Operand& operand) { 2772 pkhtb(al, rd, rn, operand); 2773 } 2774 2775 void pld(Condition cond, Location* location); 2776 bool pld_info(Condition cond, 2777 Location* location, 2778 const struct ReferenceInfo** info); pld(Location * location)2779 void pld(Location* location) { pld(al, location); } 2780 2781 void pld(Condition cond, const MemOperand& operand); pld(const MemOperand & operand)2782 void pld(const MemOperand& operand) { pld(al, operand); } 2783 2784 void pldw(Condition cond, const MemOperand& operand); pldw(const MemOperand & operand)2785 void pldw(const MemOperand& operand) { pldw(al, operand); } 2786 2787 void pli(Condition cond, const MemOperand& operand); pli(const MemOperand & operand)2788 void pli(const MemOperand& operand) { pli(al, operand); } 2789 2790 void pli(Condition cond, Location* location); 2791 bool pli_info(Condition cond, 2792 Location* location, 2793 const struct ReferenceInfo** info); pli(Location * location)2794 void pli(Location* location) { pli(al, location); } 2795 2796 void pop(Condition cond, EncodingSize size, RegisterList registers); pop(RegisterList registers)2797 void pop(RegisterList registers) { pop(al, Best, registers); } pop(Condition cond,RegisterList registers)2798 void pop(Condition cond, RegisterList registers) { 2799 pop(cond, Best, registers); 2800 } pop(EncodingSize size,RegisterList registers)2801 void pop(EncodingSize size, RegisterList registers) { 2802 pop(al, size, registers); 2803 } 2804 2805 void pop(Condition cond, EncodingSize size, Register rt); pop(Register rt)2806 void pop(Register rt) { pop(al, Best, rt); } pop(Condition cond,Register rt)2807 void pop(Condition cond, Register rt) { pop(cond, Best, rt); } pop(EncodingSize size,Register rt)2808 void pop(EncodingSize size, Register rt) { pop(al, size, rt); } 2809 2810 void push(Condition cond, EncodingSize size, RegisterList registers); push(RegisterList registers)2811 void push(RegisterList registers) { push(al, Best, registers); } push(Condition cond,RegisterList registers)2812 void push(Condition cond, RegisterList registers) { 2813 push(cond, Best, registers); 2814 } push(EncodingSize size,RegisterList registers)2815 void push(EncodingSize size, RegisterList registers) { 2816 push(al, size, registers); 2817 } 2818 2819 void push(Condition cond, EncodingSize size, Register rt); push(Register rt)2820 void push(Register rt) { push(al, Best, rt); } push(Condition cond,Register rt)2821 void push(Condition cond, Register rt) { push(cond, Best, rt); } push(EncodingSize size,Register rt)2822 void push(EncodingSize size, Register rt) { push(al, size, rt); } 2823 2824 void qadd(Condition cond, Register rd, Register rm, Register rn); qadd(Register rd,Register rm,Register rn)2825 void qadd(Register rd, Register rm, Register rn) { qadd(al, rd, rm, rn); } 2826 2827 void qadd16(Condition cond, Register rd, Register rn, Register rm); qadd16(Register rd,Register rn,Register rm)2828 void qadd16(Register rd, Register rn, Register rm) { qadd16(al, rd, rn, rm); } 2829 2830 void qadd8(Condition cond, Register rd, Register rn, Register rm); qadd8(Register rd,Register rn,Register rm)2831 void qadd8(Register rd, Register rn, Register rm) { qadd8(al, rd, rn, rm); } 2832 2833 void qasx(Condition cond, Register rd, Register rn, Register rm); qasx(Register rd,Register rn,Register rm)2834 void qasx(Register rd, Register rn, Register rm) { qasx(al, rd, rn, rm); } 2835 2836 void qdadd(Condition cond, Register rd, Register rm, Register rn); qdadd(Register rd,Register rm,Register rn)2837 void qdadd(Register rd, Register rm, Register rn) { qdadd(al, rd, rm, rn); } 2838 2839 void qdsub(Condition cond, Register rd, Register rm, Register rn); qdsub(Register rd,Register rm,Register rn)2840 void qdsub(Register rd, Register rm, Register rn) { qdsub(al, rd, rm, rn); } 2841 2842 void qsax(Condition cond, Register rd, Register rn, Register rm); qsax(Register rd,Register rn,Register rm)2843 void qsax(Register rd, Register rn, Register rm) { qsax(al, rd, rn, rm); } 2844 2845 void qsub(Condition cond, Register rd, Register rm, Register rn); qsub(Register rd,Register rm,Register rn)2846 void qsub(Register rd, Register rm, Register rn) { qsub(al, rd, rm, rn); } 2847 2848 void qsub16(Condition cond, Register rd, Register rn, Register rm); qsub16(Register rd,Register rn,Register rm)2849 void qsub16(Register rd, Register rn, Register rm) { qsub16(al, rd, rn, rm); } 2850 2851 void qsub8(Condition cond, Register rd, Register rn, Register rm); qsub8(Register rd,Register rn,Register rm)2852 void qsub8(Register rd, Register rn, Register rm) { qsub8(al, rd, rn, rm); } 2853 2854 void rbit(Condition cond, Register rd, Register rm); rbit(Register rd,Register rm)2855 void rbit(Register rd, Register rm) { rbit(al, rd, rm); } 2856 2857 void rev(Condition cond, EncodingSize size, Register rd, Register rm); rev(Register rd,Register rm)2858 void rev(Register rd, Register rm) { rev(al, Best, rd, rm); } rev(Condition cond,Register rd,Register rm)2859 void rev(Condition cond, Register rd, Register rm) { 2860 rev(cond, Best, rd, rm); 2861 } rev(EncodingSize size,Register rd,Register rm)2862 void rev(EncodingSize size, Register rd, Register rm) { 2863 rev(al, size, rd, rm); 2864 } 2865 2866 void rev16(Condition cond, EncodingSize size, Register rd, Register rm); rev16(Register rd,Register rm)2867 void rev16(Register rd, Register rm) { rev16(al, Best, rd, rm); } rev16(Condition cond,Register rd,Register rm)2868 void rev16(Condition cond, Register rd, Register rm) { 2869 rev16(cond, Best, rd, rm); 2870 } rev16(EncodingSize size,Register rd,Register rm)2871 void rev16(EncodingSize size, Register rd, Register rm) { 2872 rev16(al, size, rd, rm); 2873 } 2874 2875 void revsh(Condition cond, EncodingSize size, Register rd, Register rm); revsh(Register rd,Register rm)2876 void revsh(Register rd, Register rm) { revsh(al, Best, rd, rm); } revsh(Condition cond,Register rd,Register rm)2877 void revsh(Condition cond, Register rd, Register rm) { 2878 revsh(cond, Best, rd, rm); 2879 } revsh(EncodingSize size,Register rd,Register rm)2880 void revsh(EncodingSize size, Register rd, Register rm) { 2881 revsh(al, size, rd, rm); 2882 } 2883 2884 void ror(Condition cond, 2885 EncodingSize size, 2886 Register rd, 2887 Register rm, 2888 const Operand& operand); ror(Register rd,Register rm,const Operand & operand)2889 void ror(Register rd, Register rm, const Operand& operand) { 2890 ror(al, Best, rd, rm, operand); 2891 } ror(Condition cond,Register rd,Register rm,const Operand & operand)2892 void ror(Condition cond, Register rd, Register rm, const Operand& operand) { 2893 ror(cond, Best, rd, rm, operand); 2894 } ror(EncodingSize size,Register rd,Register rm,const Operand & operand)2895 void ror(EncodingSize size, 2896 Register rd, 2897 Register rm, 2898 const Operand& operand) { 2899 ror(al, size, rd, rm, operand); 2900 } 2901 2902 void rors(Condition cond, 2903 EncodingSize size, 2904 Register rd, 2905 Register rm, 2906 const Operand& operand); rors(Register rd,Register rm,const Operand & operand)2907 void rors(Register rd, Register rm, const Operand& operand) { 2908 rors(al, Best, rd, rm, operand); 2909 } rors(Condition cond,Register rd,Register rm,const Operand & operand)2910 void rors(Condition cond, Register rd, Register rm, const Operand& operand) { 2911 rors(cond, Best, rd, rm, operand); 2912 } rors(EncodingSize size,Register rd,Register rm,const Operand & operand)2913 void rors(EncodingSize size, 2914 Register rd, 2915 Register rm, 2916 const Operand& operand) { 2917 rors(al, size, rd, rm, operand); 2918 } 2919 2920 void rrx(Condition cond, Register rd, Register rm); rrx(Register rd,Register rm)2921 void rrx(Register rd, Register rm) { rrx(al, rd, rm); } 2922 2923 void rrxs(Condition cond, Register rd, Register rm); rrxs(Register rd,Register rm)2924 void rrxs(Register rd, Register rm) { rrxs(al, rd, rm); } 2925 2926 void rsb(Condition cond, 2927 EncodingSize size, 2928 Register rd, 2929 Register rn, 2930 const Operand& operand); rsb(Register rd,Register rn,const Operand & operand)2931 void rsb(Register rd, Register rn, const Operand& operand) { 2932 rsb(al, Best, rd, rn, operand); 2933 } rsb(Condition cond,Register rd,Register rn,const Operand & operand)2934 void rsb(Condition cond, Register rd, Register rn, const Operand& operand) { 2935 rsb(cond, Best, rd, rn, operand); 2936 } rsb(EncodingSize size,Register rd,Register rn,const Operand & operand)2937 void rsb(EncodingSize size, 2938 Register rd, 2939 Register rn, 2940 const Operand& operand) { 2941 rsb(al, size, rd, rn, operand); 2942 } 2943 2944 void rsbs(Condition cond, 2945 EncodingSize size, 2946 Register rd, 2947 Register rn, 2948 const Operand& operand); rsbs(Register rd,Register rn,const Operand & operand)2949 void rsbs(Register rd, Register rn, const Operand& operand) { 2950 rsbs(al, Best, rd, rn, operand); 2951 } rsbs(Condition cond,Register rd,Register rn,const Operand & operand)2952 void rsbs(Condition cond, Register rd, Register rn, const Operand& operand) { 2953 rsbs(cond, Best, rd, rn, operand); 2954 } rsbs(EncodingSize size,Register rd,Register rn,const Operand & operand)2955 void rsbs(EncodingSize size, 2956 Register rd, 2957 Register rn, 2958 const Operand& operand) { 2959 rsbs(al, size, rd, rn, operand); 2960 } 2961 2962 void rsc(Condition cond, Register rd, Register rn, const Operand& operand); rsc(Register rd,Register rn,const Operand & operand)2963 void rsc(Register rd, Register rn, const Operand& operand) { 2964 rsc(al, rd, rn, operand); 2965 } 2966 2967 void rscs(Condition cond, Register rd, Register rn, const Operand& operand); rscs(Register rd,Register rn,const Operand & operand)2968 void rscs(Register rd, Register rn, const Operand& operand) { 2969 rscs(al, rd, rn, operand); 2970 } 2971 2972 void sadd16(Condition cond, Register rd, Register rn, Register rm); sadd16(Register rd,Register rn,Register rm)2973 void sadd16(Register rd, Register rn, Register rm) { sadd16(al, rd, rn, rm); } 2974 2975 void sadd8(Condition cond, Register rd, Register rn, Register rm); sadd8(Register rd,Register rn,Register rm)2976 void sadd8(Register rd, Register rn, Register rm) { sadd8(al, rd, rn, rm); } 2977 2978 void sasx(Condition cond, Register rd, Register rn, Register rm); sasx(Register rd,Register rn,Register rm)2979 void sasx(Register rd, Register rn, Register rm) { sasx(al, rd, rn, rm); } 2980 2981 void sbc(Condition cond, 2982 EncodingSize size, 2983 Register rd, 2984 Register rn, 2985 const Operand& operand); sbc(Register rd,Register rn,const Operand & operand)2986 void sbc(Register rd, Register rn, const Operand& operand) { 2987 sbc(al, Best, rd, rn, operand); 2988 } sbc(Condition cond,Register rd,Register rn,const Operand & operand)2989 void sbc(Condition cond, Register rd, Register rn, const Operand& operand) { 2990 sbc(cond, Best, rd, rn, operand); 2991 } sbc(EncodingSize size,Register rd,Register rn,const Operand & operand)2992 void sbc(EncodingSize size, 2993 Register rd, 2994 Register rn, 2995 const Operand& operand) { 2996 sbc(al, size, rd, rn, operand); 2997 } 2998 2999 void sbcs(Condition cond, 3000 EncodingSize size, 3001 Register rd, 3002 Register rn, 3003 const Operand& operand); sbcs(Register rd,Register rn,const Operand & operand)3004 void sbcs(Register rd, Register rn, const Operand& operand) { 3005 sbcs(al, Best, rd, rn, operand); 3006 } sbcs(Condition cond,Register rd,Register rn,const Operand & operand)3007 void sbcs(Condition cond, Register rd, Register rn, const Operand& operand) { 3008 sbcs(cond, Best, rd, rn, operand); 3009 } sbcs(EncodingSize size,Register rd,Register rn,const Operand & operand)3010 void sbcs(EncodingSize size, 3011 Register rd, 3012 Register rn, 3013 const Operand& operand) { 3014 sbcs(al, size, rd, rn, operand); 3015 } 3016 3017 void sbfx( 3018 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width); sbfx(Register rd,Register rn,uint32_t lsb,uint32_t width)3019 void sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width) { 3020 sbfx(al, rd, rn, lsb, width); 3021 } 3022 3023 void sdiv(Condition cond, Register rd, Register rn, Register rm); sdiv(Register rd,Register rn,Register rm)3024 void sdiv(Register rd, Register rn, Register rm) { sdiv(al, rd, rn, rm); } 3025 3026 void sel(Condition cond, Register rd, Register rn, Register rm); sel(Register rd,Register rn,Register rm)3027 void sel(Register rd, Register rn, Register rm) { sel(al, rd, rn, rm); } 3028 3029 void shadd16(Condition cond, Register rd, Register rn, Register rm); shadd16(Register rd,Register rn,Register rm)3030 void shadd16(Register rd, Register rn, Register rm) { 3031 shadd16(al, rd, rn, rm); 3032 } 3033 3034 void shadd8(Condition cond, Register rd, Register rn, Register rm); shadd8(Register rd,Register rn,Register rm)3035 void shadd8(Register rd, Register rn, Register rm) { shadd8(al, rd, rn, rm); } 3036 3037 void shasx(Condition cond, Register rd, Register rn, Register rm); shasx(Register rd,Register rn,Register rm)3038 void shasx(Register rd, Register rn, Register rm) { shasx(al, rd, rn, rm); } 3039 3040 void shsax(Condition cond, Register rd, Register rn, Register rm); shsax(Register rd,Register rn,Register rm)3041 void shsax(Register rd, Register rn, Register rm) { shsax(al, rd, rn, rm); } 3042 3043 void shsub16(Condition cond, Register rd, Register rn, Register rm); shsub16(Register rd,Register rn,Register rm)3044 void shsub16(Register rd, Register rn, Register rm) { 3045 shsub16(al, rd, rn, rm); 3046 } 3047 3048 void shsub8(Condition cond, Register rd, Register rn, Register rm); shsub8(Register rd,Register rn,Register rm)3049 void shsub8(Register rd, Register rn, Register rm) { shsub8(al, rd, rn, rm); } 3050 3051 void smlabb( 3052 Condition cond, Register rd, Register rn, Register rm, Register ra); smlabb(Register rd,Register rn,Register rm,Register ra)3053 void smlabb(Register rd, Register rn, Register rm, Register ra) { 3054 smlabb(al, rd, rn, rm, ra); 3055 } 3056 3057 void smlabt( 3058 Condition cond, Register rd, Register rn, Register rm, Register ra); smlabt(Register rd,Register rn,Register rm,Register ra)3059 void smlabt(Register rd, Register rn, Register rm, Register ra) { 3060 smlabt(al, rd, rn, rm, ra); 3061 } 3062 3063 void smlad( 3064 Condition cond, Register rd, Register rn, Register rm, Register ra); smlad(Register rd,Register rn,Register rm,Register ra)3065 void smlad(Register rd, Register rn, Register rm, Register ra) { 3066 smlad(al, rd, rn, rm, ra); 3067 } 3068 3069 void smladx( 3070 Condition cond, Register rd, Register rn, Register rm, Register ra); smladx(Register rd,Register rn,Register rm,Register ra)3071 void smladx(Register rd, Register rn, Register rm, Register ra) { 3072 smladx(al, rd, rn, rm, ra); 3073 } 3074 3075 void smlal( 3076 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); smlal(Register rdlo,Register rdhi,Register rn,Register rm)3077 void smlal(Register rdlo, Register rdhi, Register rn, Register rm) { 3078 smlal(al, rdlo, rdhi, rn, rm); 3079 } 3080 3081 void smlalbb( 3082 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); smlalbb(Register rdlo,Register rdhi,Register rn,Register rm)3083 void smlalbb(Register rdlo, Register rdhi, Register rn, Register rm) { 3084 smlalbb(al, rdlo, rdhi, rn, rm); 3085 } 3086 3087 void smlalbt( 3088 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); smlalbt(Register rdlo,Register rdhi,Register rn,Register rm)3089 void smlalbt(Register rdlo, Register rdhi, Register rn, Register rm) { 3090 smlalbt(al, rdlo, rdhi, rn, rm); 3091 } 3092 3093 void smlald( 3094 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); smlald(Register rdlo,Register rdhi,Register rn,Register rm)3095 void smlald(Register rdlo, Register rdhi, Register rn, Register rm) { 3096 smlald(al, rdlo, rdhi, rn, rm); 3097 } 3098 3099 void smlaldx( 3100 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); smlaldx(Register rdlo,Register rdhi,Register rn,Register rm)3101 void smlaldx(Register rdlo, Register rdhi, Register rn, Register rm) { 3102 smlaldx(al, rdlo, rdhi, rn, rm); 3103 } 3104 3105 void smlals( 3106 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); smlals(Register rdlo,Register rdhi,Register rn,Register rm)3107 void smlals(Register rdlo, Register rdhi, Register rn, Register rm) { 3108 smlals(al, rdlo, rdhi, rn, rm); 3109 } 3110 3111 void smlaltb( 3112 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); smlaltb(Register rdlo,Register rdhi,Register rn,Register rm)3113 void smlaltb(Register rdlo, Register rdhi, Register rn, Register rm) { 3114 smlaltb(al, rdlo, rdhi, rn, rm); 3115 } 3116 3117 void smlaltt( 3118 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); smlaltt(Register rdlo,Register rdhi,Register rn,Register rm)3119 void smlaltt(Register rdlo, Register rdhi, Register rn, Register rm) { 3120 smlaltt(al, rdlo, rdhi, rn, rm); 3121 } 3122 3123 void smlatb( 3124 Condition cond, Register rd, Register rn, Register rm, Register ra); smlatb(Register rd,Register rn,Register rm,Register ra)3125 void smlatb(Register rd, Register rn, Register rm, Register ra) { 3126 smlatb(al, rd, rn, rm, ra); 3127 } 3128 3129 void smlatt( 3130 Condition cond, Register rd, Register rn, Register rm, Register ra); smlatt(Register rd,Register rn,Register rm,Register ra)3131 void smlatt(Register rd, Register rn, Register rm, Register ra) { 3132 smlatt(al, rd, rn, rm, ra); 3133 } 3134 3135 void smlawb( 3136 Condition cond, Register rd, Register rn, Register rm, Register ra); smlawb(Register rd,Register rn,Register rm,Register ra)3137 void smlawb(Register rd, Register rn, Register rm, Register ra) { 3138 smlawb(al, rd, rn, rm, ra); 3139 } 3140 3141 void smlawt( 3142 Condition cond, Register rd, Register rn, Register rm, Register ra); smlawt(Register rd,Register rn,Register rm,Register ra)3143 void smlawt(Register rd, Register rn, Register rm, Register ra) { 3144 smlawt(al, rd, rn, rm, ra); 3145 } 3146 3147 void smlsd( 3148 Condition cond, Register rd, Register rn, Register rm, Register ra); smlsd(Register rd,Register rn,Register rm,Register ra)3149 void smlsd(Register rd, Register rn, Register rm, Register ra) { 3150 smlsd(al, rd, rn, rm, ra); 3151 } 3152 3153 void smlsdx( 3154 Condition cond, Register rd, Register rn, Register rm, Register ra); smlsdx(Register rd,Register rn,Register rm,Register ra)3155 void smlsdx(Register rd, Register rn, Register rm, Register ra) { 3156 smlsdx(al, rd, rn, rm, ra); 3157 } 3158 3159 void smlsld( 3160 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); smlsld(Register rdlo,Register rdhi,Register rn,Register rm)3161 void smlsld(Register rdlo, Register rdhi, Register rn, Register rm) { 3162 smlsld(al, rdlo, rdhi, rn, rm); 3163 } 3164 3165 void smlsldx( 3166 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); smlsldx(Register rdlo,Register rdhi,Register rn,Register rm)3167 void smlsldx(Register rdlo, Register rdhi, Register rn, Register rm) { 3168 smlsldx(al, rdlo, rdhi, rn, rm); 3169 } 3170 3171 void smmla( 3172 Condition cond, Register rd, Register rn, Register rm, Register ra); smmla(Register rd,Register rn,Register rm,Register ra)3173 void smmla(Register rd, Register rn, Register rm, Register ra) { 3174 smmla(al, rd, rn, rm, ra); 3175 } 3176 3177 void smmlar( 3178 Condition cond, Register rd, Register rn, Register rm, Register ra); smmlar(Register rd,Register rn,Register rm,Register ra)3179 void smmlar(Register rd, Register rn, Register rm, Register ra) { 3180 smmlar(al, rd, rn, rm, ra); 3181 } 3182 3183 void smmls( 3184 Condition cond, Register rd, Register rn, Register rm, Register ra); smmls(Register rd,Register rn,Register rm,Register ra)3185 void smmls(Register rd, Register rn, Register rm, Register ra) { 3186 smmls(al, rd, rn, rm, ra); 3187 } 3188 3189 void smmlsr( 3190 Condition cond, Register rd, Register rn, Register rm, Register ra); smmlsr(Register rd,Register rn,Register rm,Register ra)3191 void smmlsr(Register rd, Register rn, Register rm, Register ra) { 3192 smmlsr(al, rd, rn, rm, ra); 3193 } 3194 3195 void smmul(Condition cond, Register rd, Register rn, Register rm); smmul(Register rd,Register rn,Register rm)3196 void smmul(Register rd, Register rn, Register rm) { smmul(al, rd, rn, rm); } 3197 3198 void smmulr(Condition cond, Register rd, Register rn, Register rm); smmulr(Register rd,Register rn,Register rm)3199 void smmulr(Register rd, Register rn, Register rm) { smmulr(al, rd, rn, rm); } 3200 3201 void smuad(Condition cond, Register rd, Register rn, Register rm); smuad(Register rd,Register rn,Register rm)3202 void smuad(Register rd, Register rn, Register rm) { smuad(al, rd, rn, rm); } 3203 3204 void smuadx(Condition cond, Register rd, Register rn, Register rm); smuadx(Register rd,Register rn,Register rm)3205 void smuadx(Register rd, Register rn, Register rm) { smuadx(al, rd, rn, rm); } 3206 3207 void smulbb(Condition cond, Register rd, Register rn, Register rm); smulbb(Register rd,Register rn,Register rm)3208 void smulbb(Register rd, Register rn, Register rm) { smulbb(al, rd, rn, rm); } 3209 3210 void smulbt(Condition cond, Register rd, Register rn, Register rm); smulbt(Register rd,Register rn,Register rm)3211 void smulbt(Register rd, Register rn, Register rm) { smulbt(al, rd, rn, rm); } 3212 3213 void smull( 3214 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); smull(Register rdlo,Register rdhi,Register rn,Register rm)3215 void smull(Register rdlo, Register rdhi, Register rn, Register rm) { 3216 smull(al, rdlo, rdhi, rn, rm); 3217 } 3218 3219 void smulls( 3220 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); smulls(Register rdlo,Register rdhi,Register rn,Register rm)3221 void smulls(Register rdlo, Register rdhi, Register rn, Register rm) { 3222 smulls(al, rdlo, rdhi, rn, rm); 3223 } 3224 3225 void smultb(Condition cond, Register rd, Register rn, Register rm); smultb(Register rd,Register rn,Register rm)3226 void smultb(Register rd, Register rn, Register rm) { smultb(al, rd, rn, rm); } 3227 3228 void smultt(Condition cond, Register rd, Register rn, Register rm); smultt(Register rd,Register rn,Register rm)3229 void smultt(Register rd, Register rn, Register rm) { smultt(al, rd, rn, rm); } 3230 3231 void smulwb(Condition cond, Register rd, Register rn, Register rm); smulwb(Register rd,Register rn,Register rm)3232 void smulwb(Register rd, Register rn, Register rm) { smulwb(al, rd, rn, rm); } 3233 3234 void smulwt(Condition cond, Register rd, Register rn, Register rm); smulwt(Register rd,Register rn,Register rm)3235 void smulwt(Register rd, Register rn, Register rm) { smulwt(al, rd, rn, rm); } 3236 3237 void smusd(Condition cond, Register rd, Register rn, Register rm); smusd(Register rd,Register rn,Register rm)3238 void smusd(Register rd, Register rn, Register rm) { smusd(al, rd, rn, rm); } 3239 3240 void smusdx(Condition cond, Register rd, Register rn, Register rm); smusdx(Register rd,Register rn,Register rm)3241 void smusdx(Register rd, Register rn, Register rm) { smusdx(al, rd, rn, rm); } 3242 3243 void ssat(Condition cond, Register rd, uint32_t imm, const Operand& operand); ssat(Register rd,uint32_t imm,const Operand & operand)3244 void ssat(Register rd, uint32_t imm, const Operand& operand) { 3245 ssat(al, rd, imm, operand); 3246 } 3247 3248 void ssat16(Condition cond, Register rd, uint32_t imm, Register rn); ssat16(Register rd,uint32_t imm,Register rn)3249 void ssat16(Register rd, uint32_t imm, Register rn) { 3250 ssat16(al, rd, imm, rn); 3251 } 3252 3253 void ssax(Condition cond, Register rd, Register rn, Register rm); ssax(Register rd,Register rn,Register rm)3254 void ssax(Register rd, Register rn, Register rm) { ssax(al, rd, rn, rm); } 3255 3256 void ssub16(Condition cond, Register rd, Register rn, Register rm); ssub16(Register rd,Register rn,Register rm)3257 void ssub16(Register rd, Register rn, Register rm) { ssub16(al, rd, rn, rm); } 3258 3259 void ssub8(Condition cond, Register rd, Register rn, Register rm); ssub8(Register rd,Register rn,Register rm)3260 void ssub8(Register rd, Register rn, Register rm) { ssub8(al, rd, rn, rm); } 3261 3262 void stl(Condition cond, Register rt, const MemOperand& operand); stl(Register rt,const MemOperand & operand)3263 void stl(Register rt, const MemOperand& operand) { stl(al, rt, operand); } 3264 3265 void stlb(Condition cond, Register rt, const MemOperand& operand); stlb(Register rt,const MemOperand & operand)3266 void stlb(Register rt, const MemOperand& operand) { stlb(al, rt, operand); } 3267 3268 void stlex(Condition cond, 3269 Register rd, 3270 Register rt, 3271 const MemOperand& operand); stlex(Register rd,Register rt,const MemOperand & operand)3272 void stlex(Register rd, Register rt, const MemOperand& operand) { 3273 stlex(al, rd, rt, operand); 3274 } 3275 3276 void stlexb(Condition cond, 3277 Register rd, 3278 Register rt, 3279 const MemOperand& operand); stlexb(Register rd,Register rt,const MemOperand & operand)3280 void stlexb(Register rd, Register rt, const MemOperand& operand) { 3281 stlexb(al, rd, rt, operand); 3282 } 3283 3284 void stlexd(Condition cond, 3285 Register rd, 3286 Register rt, 3287 Register rt2, 3288 const MemOperand& operand); stlexd(Register rd,Register rt,Register rt2,const MemOperand & operand)3289 void stlexd(Register rd, 3290 Register rt, 3291 Register rt2, 3292 const MemOperand& operand) { 3293 stlexd(al, rd, rt, rt2, operand); 3294 } 3295 3296 void stlexh(Condition cond, 3297 Register rd, 3298 Register rt, 3299 const MemOperand& operand); stlexh(Register rd,Register rt,const MemOperand & operand)3300 void stlexh(Register rd, Register rt, const MemOperand& operand) { 3301 stlexh(al, rd, rt, operand); 3302 } 3303 3304 void stlh(Condition cond, Register rt, const MemOperand& operand); stlh(Register rt,const MemOperand & operand)3305 void stlh(Register rt, const MemOperand& operand) { stlh(al, rt, operand); } 3306 3307 void stm(Condition cond, 3308 EncodingSize size, 3309 Register rn, 3310 WriteBack write_back, 3311 RegisterList registers); stm(Register rn,WriteBack write_back,RegisterList registers)3312 void stm(Register rn, WriteBack write_back, RegisterList registers) { 3313 stm(al, Best, rn, write_back, registers); 3314 } stm(Condition cond,Register rn,WriteBack write_back,RegisterList registers)3315 void stm(Condition cond, 3316 Register rn, 3317 WriteBack write_back, 3318 RegisterList registers) { 3319 stm(cond, Best, rn, write_back, registers); 3320 } stm(EncodingSize size,Register rn,WriteBack write_back,RegisterList registers)3321 void stm(EncodingSize size, 3322 Register rn, 3323 WriteBack write_back, 3324 RegisterList registers) { 3325 stm(al, size, rn, write_back, registers); 3326 } 3327 3328 void stmda(Condition cond, 3329 Register rn, 3330 WriteBack write_back, 3331 RegisterList registers); stmda(Register rn,WriteBack write_back,RegisterList registers)3332 void stmda(Register rn, WriteBack write_back, RegisterList registers) { 3333 stmda(al, rn, write_back, registers); 3334 } 3335 3336 void stmdb(Condition cond, 3337 EncodingSize size, 3338 Register rn, 3339 WriteBack write_back, 3340 RegisterList registers); stmdb(Register rn,WriteBack write_back,RegisterList registers)3341 void stmdb(Register rn, WriteBack write_back, RegisterList registers) { 3342 stmdb(al, Best, rn, write_back, registers); 3343 } stmdb(Condition cond,Register rn,WriteBack write_back,RegisterList registers)3344 void stmdb(Condition cond, 3345 Register rn, 3346 WriteBack write_back, 3347 RegisterList registers) { 3348 stmdb(cond, Best, rn, write_back, registers); 3349 } stmdb(EncodingSize size,Register rn,WriteBack write_back,RegisterList registers)3350 void stmdb(EncodingSize size, 3351 Register rn, 3352 WriteBack write_back, 3353 RegisterList registers) { 3354 stmdb(al, size, rn, write_back, registers); 3355 } 3356 3357 void stmea(Condition cond, 3358 EncodingSize size, 3359 Register rn, 3360 WriteBack write_back, 3361 RegisterList registers); stmea(Register rn,WriteBack write_back,RegisterList registers)3362 void stmea(Register rn, WriteBack write_back, RegisterList registers) { 3363 stmea(al, Best, rn, write_back, registers); 3364 } stmea(Condition cond,Register rn,WriteBack write_back,RegisterList registers)3365 void stmea(Condition cond, 3366 Register rn, 3367 WriteBack write_back, 3368 RegisterList registers) { 3369 stmea(cond, Best, rn, write_back, registers); 3370 } stmea(EncodingSize size,Register rn,WriteBack write_back,RegisterList registers)3371 void stmea(EncodingSize size, 3372 Register rn, 3373 WriteBack write_back, 3374 RegisterList registers) { 3375 stmea(al, size, rn, write_back, registers); 3376 } 3377 3378 void stmed(Condition cond, 3379 Register rn, 3380 WriteBack write_back, 3381 RegisterList registers); stmed(Register rn,WriteBack write_back,RegisterList registers)3382 void stmed(Register rn, WriteBack write_back, RegisterList registers) { 3383 stmed(al, rn, write_back, registers); 3384 } 3385 3386 void stmfa(Condition cond, 3387 Register rn, 3388 WriteBack write_back, 3389 RegisterList registers); stmfa(Register rn,WriteBack write_back,RegisterList registers)3390 void stmfa(Register rn, WriteBack write_back, RegisterList registers) { 3391 stmfa(al, rn, write_back, registers); 3392 } 3393 3394 void stmfd(Condition cond, 3395 Register rn, 3396 WriteBack write_back, 3397 RegisterList registers); stmfd(Register rn,WriteBack write_back,RegisterList registers)3398 void stmfd(Register rn, WriteBack write_back, RegisterList registers) { 3399 stmfd(al, rn, write_back, registers); 3400 } 3401 3402 void stmib(Condition cond, 3403 Register rn, 3404 WriteBack write_back, 3405 RegisterList registers); stmib(Register rn,WriteBack write_back,RegisterList registers)3406 void stmib(Register rn, WriteBack write_back, RegisterList registers) { 3407 stmib(al, rn, write_back, registers); 3408 } 3409 3410 void str(Condition cond, 3411 EncodingSize size, 3412 Register rt, 3413 const MemOperand& operand); str(Register rt,const MemOperand & operand)3414 void str(Register rt, const MemOperand& operand) { 3415 str(al, Best, rt, operand); 3416 } str(Condition cond,Register rt,const MemOperand & operand)3417 void str(Condition cond, Register rt, const MemOperand& operand) { 3418 str(cond, Best, rt, operand); 3419 } str(EncodingSize size,Register rt,const MemOperand & operand)3420 void str(EncodingSize size, Register rt, const MemOperand& operand) { 3421 str(al, size, rt, operand); 3422 } 3423 3424 void strb(Condition cond, 3425 EncodingSize size, 3426 Register rt, 3427 const MemOperand& operand); strb(Register rt,const MemOperand & operand)3428 void strb(Register rt, const MemOperand& operand) { 3429 strb(al, Best, rt, operand); 3430 } strb(Condition cond,Register rt,const MemOperand & operand)3431 void strb(Condition cond, Register rt, const MemOperand& operand) { 3432 strb(cond, Best, rt, operand); 3433 } strb(EncodingSize size,Register rt,const MemOperand & operand)3434 void strb(EncodingSize size, Register rt, const MemOperand& operand) { 3435 strb(al, size, rt, operand); 3436 } 3437 3438 void strd(Condition cond, 3439 Register rt, 3440 Register rt2, 3441 const MemOperand& operand); strd(Register rt,Register rt2,const MemOperand & operand)3442 void strd(Register rt, Register rt2, const MemOperand& operand) { 3443 strd(al, rt, rt2, operand); 3444 } 3445 3446 void strex(Condition cond, 3447 Register rd, 3448 Register rt, 3449 const MemOperand& operand); strex(Register rd,Register rt,const MemOperand & operand)3450 void strex(Register rd, Register rt, const MemOperand& operand) { 3451 strex(al, rd, rt, operand); 3452 } 3453 3454 void strexb(Condition cond, 3455 Register rd, 3456 Register rt, 3457 const MemOperand& operand); strexb(Register rd,Register rt,const MemOperand & operand)3458 void strexb(Register rd, Register rt, const MemOperand& operand) { 3459 strexb(al, rd, rt, operand); 3460 } 3461 3462 void strexd(Condition cond, 3463 Register rd, 3464 Register rt, 3465 Register rt2, 3466 const MemOperand& operand); strexd(Register rd,Register rt,Register rt2,const MemOperand & operand)3467 void strexd(Register rd, 3468 Register rt, 3469 Register rt2, 3470 const MemOperand& operand) { 3471 strexd(al, rd, rt, rt2, operand); 3472 } 3473 3474 void strexh(Condition cond, 3475 Register rd, 3476 Register rt, 3477 const MemOperand& operand); strexh(Register rd,Register rt,const MemOperand & operand)3478 void strexh(Register rd, Register rt, const MemOperand& operand) { 3479 strexh(al, rd, rt, operand); 3480 } 3481 3482 void strh(Condition cond, 3483 EncodingSize size, 3484 Register rt, 3485 const MemOperand& operand); strh(Register rt,const MemOperand & operand)3486 void strh(Register rt, const MemOperand& operand) { 3487 strh(al, Best, rt, operand); 3488 } strh(Condition cond,Register rt,const MemOperand & operand)3489 void strh(Condition cond, Register rt, const MemOperand& operand) { 3490 strh(cond, Best, rt, operand); 3491 } strh(EncodingSize size,Register rt,const MemOperand & operand)3492 void strh(EncodingSize size, Register rt, const MemOperand& operand) { 3493 strh(al, size, rt, operand); 3494 } 3495 3496 void sub(Condition cond, 3497 EncodingSize size, 3498 Register rd, 3499 Register rn, 3500 const Operand& operand); sub(Register rd,Register rn,const Operand & operand)3501 void sub(Register rd, Register rn, const Operand& operand) { 3502 sub(al, Best, rd, rn, operand); 3503 } sub(Condition cond,Register rd,Register rn,const Operand & operand)3504 void sub(Condition cond, Register rd, Register rn, const Operand& operand) { 3505 sub(cond, Best, rd, rn, operand); 3506 } sub(EncodingSize size,Register rd,Register rn,const Operand & operand)3507