1 /* 2 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without modification, are permitted 5 * provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright notice, this list of 7 * conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright notice, this list of 9 * conditions and the following disclaimer in the documentation and/or other materials provided 10 * with the distribution. 11 * * Neither the name of The Linux Foundation nor the names of its contributors may be used to 12 * endorse or promote products derived from this software without specific prior written 13 * permission. 14 * 15 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 16 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 17 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 21 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 22 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25 #ifndef __HW_INFO_TYPES_H__ 26 #define __HW_INFO_TYPES_H__ 27 28 #include <stdint.h> 29 #include <core/display_interface.h> 30 #include <core/core_interface.h> 31 #include <vector> 32 #include <map> 33 #include <string> 34 #include <bitset> 35 36 namespace sdm { 37 using std::string; 38 39 const int kMaxSDELayers = 16; // Maximum number of layers that can be handled by MDP5 hardware 40 // in a given layer stack. 41 #define MAX_PLANES 4 42 #define MAX_DETAIL_ENHANCE_CURVE 3 43 #define MAJOR 28 44 #define MINOR 16 45 #define SDEVERSION(major, minor, hw_rev) ((major) << MAJOR) | ((minor) << MINOR) | (hw_rev) 46 47 enum HWDeviceType { 48 kDevicePrimary, 49 kDeviceHDMI, 50 kDeviceVirtual, 51 kDeviceRotator, 52 kDeviceMax, 53 }; 54 55 enum HWBlockType { 56 kHWPrimary, 57 kHWHDMI, 58 kHWWriteback0, 59 kHWWriteback1, 60 kHWWriteback2, 61 kHWBlockMax 62 }; 63 64 enum HWDisplayMode { 65 kModeDefault, 66 kModeVideo, 67 kModeCommand, 68 }; 69 70 enum PipeType { 71 kPipeTypeUnused, 72 kPipeTypeVIG, 73 kPipeTypeRGB, 74 kPipeTypeDMA, 75 kPipeTypeCursor, 76 }; 77 78 enum HWSubBlockType { 79 kHWVIGPipe, 80 kHWRGBPipe, 81 kHWDMAPipe, 82 kHWCursorPipe, 83 kHWRotatorInput, 84 kHWRotatorOutput, 85 kHWWBIntfOutput, 86 kHWDestinationScalar, 87 kHWSubBlockMax, 88 }; 89 90 enum HWAlphaInterpolation { 91 kInterpolationPixelRepeat, 92 kInterpolationBilinear, 93 kInterpolation2D, 94 kInterpolationMax, 95 }; 96 97 enum HWBlendingFilter { 98 kBlendFilterCircular, 99 kBlendFilterSeparable, 100 kBlendFilterMax, 101 }; 102 103 enum HWPipeFlags { 104 kIGC = 0x01, 105 kMultiRect = 0x02, 106 kMultiRectParallelMode = 0x04, 107 }; 108 109 enum HWAVRModes { 110 kContinuousMode, // Mode to enable AVR feature for every frame. 111 kOneShotMode, // Mode to enable AVR feature for particular frame. 112 }; 113 114 enum HWTopology { 115 kUnknown, 116 kSingleLM, 117 kSingleLMDSC, 118 kDualLM, 119 kDualLMDSC, 120 kDualLMMerge, 121 kDualLMMergeDSC, 122 kDualLMDSCMerge, 123 kPPSplit, 124 }; 125 126 enum HwHdrEotf { 127 kHdrEOTFInvalid = 0, 128 kHdrEOTFSDR = 0x1, 129 kHdrEOTFHdrLumRange = 0x2, 130 kHdrEOTFHDR10 = 0x4, 131 kHdrEOTFHLG = 0x8, 132 }; 133 134 typedef std::map<HWSubBlockType, std::vector<LayerBufferFormat>> FormatsMap; 135 typedef std::map<LayerBufferFormat, float> CompRatioMap; 136 137 struct HWDynBwLimitInfo { 138 uint32_t cur_mode = kBwDefault; 139 uint64_t total_bw_limit[kBwModeMax] = { 0 }; 140 uint64_t pipe_bw_limit[kBwModeMax] = { 0 }; 141 }; 142 143 struct HWPipeCaps { 144 PipeType type = kPipeTypeUnused; 145 uint32_t id = 0; 146 uint32_t master_pipe_id = 0; 147 uint32_t max_rects = 1; 148 bool block_sec_ui = false; 149 }; 150 151 struct HWRotatorInfo { 152 enum { ROT_TYPE_MDSS, ROT_TYPE_V4L2 }; 153 uint32_t type = ROT_TYPE_MDSS; 154 uint32_t num_rotator = 0; 155 bool has_downscale = false; 156 std::string device_path = ""; 157 float min_downscale = 2.0f; 158 bool downscale_compression = false; 159 }; 160 161 enum HWQseedStepVersion { 162 kQseed3v2, 163 kQseed3v3, 164 kQseed3v4, 165 }; 166 167 struct HWDestScalarInfo { 168 uint32_t count = 0; 169 uint32_t max_input_width = 0; 170 uint32_t max_output_width = 0; 171 uint32_t max_scale_up = 1; 172 uint32_t prefill_lines = 4; 173 }; 174 175 enum SmartDMARevision { 176 V1, 177 V2, 178 }; 179 180 struct HWResourceInfo { 181 uint32_t hw_version = 0; 182 uint32_t hw_revision = 0; 183 uint32_t num_dma_pipe = 0; 184 uint32_t num_vig_pipe = 0; 185 uint32_t num_rgb_pipe = 0; 186 uint32_t num_cursor_pipe = 0; 187 uint32_t num_blending_stages = 0; 188 uint32_t num_solidfill_stages = 0; 189 uint32_t num_control = 0; 190 uint32_t num_mixer_to_disp = 0; 191 uint32_t smp_total = 0; 192 uint32_t smp_size = 0; 193 uint32_t num_smp_per_pipe = 0; 194 uint32_t max_scale_up = 1; 195 uint32_t max_scale_down = 1; 196 uint64_t max_bandwidth_low = 0; 197 uint64_t max_bandwidth_high = 0; 198 uint32_t max_mixer_width = 2048; 199 uint32_t max_pipe_width = 2048; 200 uint32_t max_cursor_size = 0; 201 uint64_t max_pipe_bw = 0; 202 uint32_t max_sde_clk = 0; 203 float clk_fudge_factor = 1.0f; 204 uint32_t macrotile_nv12_factor = 0; 205 uint32_t macrotile_factor = 0; 206 uint32_t linear_factor = 0; 207 uint32_t scale_factor = 0; 208 uint32_t extra_fudge_factor = 0; 209 uint32_t amortizable_threshold = 0; 210 uint32_t system_overhead_lines = 0; 211 bool has_bwc = false; 212 bool has_ubwc = false; 213 bool has_decimation = false; 214 bool has_macrotile = false; 215 bool has_non_scalar_rgb = false; 216 bool is_src_split = false; 217 bool has_dyn_bw_support = false; 218 bool separate_rotator = false; 219 bool has_qseed3 = false; 220 bool has_concurrent_writeback = false; 221 bool has_ppp = false; 222 uint32_t writeback_index = kHWBlockMax; 223 HWDynBwLimitInfo dyn_bw_info; 224 std::vector<HWPipeCaps> hw_pipes; 225 FormatsMap supported_formats_map; 226 HWRotatorInfo hw_rot_info; 227 HWDestScalarInfo hw_dest_scalar_info; 228 bool has_avr = false; 229 bool has_hdr = false; 230 SmartDMARevision smart_dma_rev = SmartDMARevision::V1; 231 float ib_fudge_factor = 1.0f; 232 uint32_t undersized_prefill_lines = 0; 233 CompRatioMap comp_ratio_rt_map; 234 CompRatioMap comp_ratio_nrt_map; 235 uint32_t cache_size = 0; // cache size in bytes 236 HWQseedStepVersion pipe_qseed3_version = kQseed3v2; // only valid when has_qseed3=true 237 uint32_t min_prefill_lines = 0; 238 }; 239 240 struct HWSplitInfo { 241 uint32_t left_split = 0; 242 uint32_t right_split = 0; 243 244 bool operator !=(const HWSplitInfo &split_info) { 245 return ((left_split != split_info.left_split) || (right_split != split_info.right_split)); 246 } 247 248 bool operator ==(const HWSplitInfo &split_info) { 249 return !(operator !=(split_info)); 250 } 251 }; 252 253 enum HWS3DMode { 254 kS3DModeNone, 255 kS3DModeLR, 256 kS3DModeRL, 257 kS3DModeTB, 258 kS3DModeFP, 259 kS3DModeMax, 260 }; 261 262 struct HWColorPrimaries { 263 uint32_t white_point[2] = {}; // White point 264 uint32_t red[2] = {}; // Red color primary 265 uint32_t green[2] = {}; // Green color primary 266 uint32_t blue[2] = {}; // Blue color primary 267 }; 268 269 struct HWPanelOrientation { 270 bool rotation = false; 271 bool flip_horizontal = false; 272 bool flip_vertical = false; 273 }; 274 275 struct HWPanelInfo { 276 DisplayPort port = kPortDefault; // Display port 277 HWDisplayMode mode = kModeDefault; // Display mode 278 bool partial_update = false; // Partial update feature 279 int left_align = 1; // ROI left alignment restriction 280 int width_align = 1; // ROI width alignment restriction 281 int top_align = 1; // ROI top alignment restriction 282 int height_align = 1; // ROI height alignment restriction 283 int min_roi_width = 1; // Min width needed for ROI 284 int min_roi_height = 1; // Min height needed for ROI 285 bool needs_roi_merge = false; // Merge ROI's of both the DSI's 286 bool dynamic_fps = false; // Panel Supports dynamic fps 287 bool dfps_porch_mode = false; // dynamic fps VFP or HFP mode 288 bool ping_pong_split = false; // Supports Ping pong split 289 uint32_t min_fps = 0; // Min fps supported by panel 290 uint32_t max_fps = 0; // Max fps supported by panel 291 bool is_primary_panel = false; // Panel is primary display 292 bool is_pluggable = false; // Panel is pluggable 293 HWSplitInfo split_info; // Panel split configuration 294 char panel_name[256] = {0}; // Panel name 295 HWS3DMode s3d_mode = kS3DModeNone; // Panel's current s3d mode. 296 int panel_max_brightness = 0; // Max panel brightness 297 uint32_t left_roi_count = 1; // Number if ROI supported on left panel 298 uint32_t right_roi_count = 1; // Number if ROI supported on right panel 299 bool hdr_enabled = false; // HDR feature supported 300 bool hdr_metadata_type_one = false; // Static HDR metadata type one 301 uint32_t hdr_eotf = 0; // Electro optical transfer function 302 uint32_t peak_luminance = 0; // Panel's peak luminance level 303 uint32_t average_luminance = 0; // Panel's average luminance level 304 uint32_t blackness_level = 0; // Panel's blackness level 305 HWColorPrimaries primaries = {}; // WRGB color primaries 306 HWPanelOrientation panel_orientation = {}; // Panel Orientation 307 uint32_t transfer_time_us = 0; // transfer time in micro seconds to panel's active region 308 309 bool operator !=(const HWPanelInfo &panel_info) { 310 return ((port != panel_info.port) || (mode != panel_info.mode) || 311 (partial_update != panel_info.partial_update) || 312 (left_align != panel_info.left_align) || (width_align != panel_info.width_align) || 313 (top_align != panel_info.top_align) || (height_align != panel_info.height_align) || 314 (min_roi_width != panel_info.min_roi_width) || 315 (min_roi_height != panel_info.min_roi_height) || 316 (needs_roi_merge != panel_info.needs_roi_merge) || 317 (dynamic_fps != panel_info.dynamic_fps) || (min_fps != panel_info.min_fps) || 318 (dfps_porch_mode != panel_info.dfps_porch_mode) || 319 (ping_pong_split != panel_info.ping_pong_split) || 320 (max_fps != panel_info.max_fps) || (is_primary_panel != panel_info.is_primary_panel) || 321 (split_info != panel_info.split_info) || (s3d_mode != panel_info.s3d_mode) || 322 (left_roi_count != panel_info.left_roi_count) || 323 (right_roi_count != panel_info.right_roi_count) || 324 (transfer_time_us != panel_info.transfer_time_us)); 325 } 326 327 bool operator ==(const HWPanelInfo &panel_info) { 328 return !(operator !=(panel_info)); 329 } 330 }; 331 332 struct HWSessionConfig { 333 LayerRect src_rect {}; 334 LayerRect dst_rect {}; 335 uint32_t buffer_count = 0; 336 bool secure = false; 337 uint32_t frame_rate = 0; 338 LayerTransform transform; 339 bool secure_camera = false; 340 341 bool operator==(const HWSessionConfig& config) const { 342 return (src_rect == config.src_rect && 343 dst_rect == config.dst_rect && 344 buffer_count == config.buffer_count && 345 secure == config.secure && 346 frame_rate == config.frame_rate && 347 transform == config.transform && 348 secure_camera == config.secure_camera); 349 } 350 351 bool operator!=(const HWSessionConfig& config) const { 352 return !operator==(config); 353 } 354 }; 355 356 enum HWRotatorMode { 357 kRotatorNone, 358 kRotatorOffline, 359 kRotatorInline 360 }; 361 362 struct HWRotateInfo { 363 int pipe_id = -1; // Not actual pipe id, but the relative DMA id 364 int writeback_id = -1; // Writeback block id, but this is the same as DMA id 365 LayerRect src_roi {}; // Source crop of each split 366 LayerRect dst_roi {}; // Destination crop of each split 367 bool valid = false; 368 int rotate_id = -1; // Actual rotator session id with driver 369 }; 370 371 struct HWRotatorSession { 372 HWRotateInfo hw_rotate_info[kMaxRotatePerLayer] {}; 373 uint32_t hw_block_count = 0; // number of rotator hw blocks used by rotator session 374 int session_id = -1; // A handle with Session Manager 375 HWSessionConfig hw_session_config {}; 376 LayerBuffer input_buffer {}; // Input to rotator 377 LayerBuffer output_buffer {}; // Output of rotator, crop width and stride are same 378 float input_compression = 1.0f; 379 float output_compression = 1.0f; 380 bool is_buffer_cached = false; 381 HWRotatorMode mode = kRotatorNone; 382 }; 383 384 struct HWScaleLutInfo { 385 uint32_t dir_lut_size = 0; 386 uint32_t cir_lut_size = 0; 387 uint32_t sep_lut_size = 0; 388 uint64_t dir_lut = 0; 389 uint64_t cir_lut = 0; 390 uint64_t sep_lut = 0; 391 }; 392 393 struct HWDetailEnhanceData : DisplayDetailEnhancerData { 394 uint16_t prec_shift = 0; 395 int16_t adjust_a[MAX_DETAIL_ENHANCE_CURVE] = {0}; 396 int16_t adjust_b[MAX_DETAIL_ENHANCE_CURVE] = {0}; 397 int16_t adjust_c[MAX_DETAIL_ENHANCE_CURVE] = {0}; 398 }; 399 400 struct HWPixelExtension { 401 int32_t extension = 0; // Number of pixels extension in left, right, top and bottom directions 402 // for all color components. This pixel value for each color component 403 // should be sum of fetch and repeat pixels. 404 405 int32_t overfetch = 0; // Number of pixels need to be overfetched in left, right, top and bottom 406 // directions from source image for scaling. 407 408 int32_t repeat = 0; // Number of pixels need to be repeated in left, right, top and bottom 409 // directions for scaling. 410 }; 411 412 struct HWPlane { 413 int32_t init_phase_x = 0; 414 int32_t phase_step_x = 0; 415 int32_t init_phase_y = 0; 416 int32_t phase_step_y = 0; 417 HWPixelExtension left {}; 418 HWPixelExtension top {}; 419 HWPixelExtension right {}; 420 HWPixelExtension bottom {}; 421 uint32_t roi_width = 0; 422 int32_t preload_x = 0; 423 int32_t preload_y = 0; 424 uint32_t src_width = 0; 425 uint32_t src_height = 0; 426 }; 427 428 struct HWScaleData { 429 struct enable { 430 uint8_t scale = 0; 431 uint8_t direction_detection = 0; 432 uint8_t detail_enhance = 0; 433 } enable; 434 uint32_t dst_width = 0; 435 uint32_t dst_height = 0; 436 HWPlane plane[MAX_PLANES] {}; 437 // scale_v2_data fields 438 ScalingFilterConfig y_rgb_filter_cfg = kFilterEdgeDirected; 439 ScalingFilterConfig uv_filter_cfg = kFilterEdgeDirected; 440 HWAlphaInterpolation alpha_filter_cfg = kInterpolationPixelRepeat; 441 HWBlendingFilter blend_cfg = kBlendFilterCircular; 442 443 struct lut_flags { 444 uint8_t lut_swap = 0; 445 uint8_t lut_dir_wr = 0; 446 uint8_t lut_y_cir_wr = 0; 447 uint8_t lut_uv_cir_wr = 0; 448 uint8_t lut_y_sep_wr = 0; 449 uint8_t lut_uv_sep_wr = 0; 450 } lut_flag; 451 452 uint32_t dir_lut_idx = 0; 453 /* for Y(RGB) and UV planes*/ 454 uint32_t y_rgb_cir_lut_idx = 0; 455 uint32_t uv_cir_lut_idx = 0; 456 uint32_t y_rgb_sep_lut_idx = 0; 457 uint32_t uv_sep_lut_idx = 0; 458 HWDetailEnhanceData detail_enhance {}; 459 }; 460 461 struct HWDestScaleInfo { 462 uint32_t mixer_width = 0; 463 uint32_t mixer_height = 0; 464 bool scale_update = false; 465 HWScaleData scale_data = {}; 466 LayerRect panel_roi = {}; 467 }; 468 469 typedef std::map<uint32_t, HWDestScaleInfo *> DestScaleInfoMap; 470 471 struct HWAVRInfo { 472 bool enable = false; // Flag to Enable AVR feature 473 HWAVRModes mode = kContinuousMode; // Specifies the AVR mode 474 }; 475 476 struct HWPipeInfo { 477 HWPipeInfo *pair = NULL; 478 uint8_t rect = 255; 479 uint32_t pipe_id = 0; 480 HWSubBlockType sub_block_type = kHWSubBlockMax; 481 LayerRect src_roi {}; 482 LayerRect dst_roi {}; 483 uint8_t horizontal_decimation = 0; 484 uint8_t vertical_decimation = 0; 485 HWScaleData scale_data {}; 486 uint32_t z_order = 0; 487 uint8_t flags = 0; 488 bool valid = false; 489 bool is_virtual = 0; 490 }; 491 492 struct HWSolidfillStage { 493 uint32_t z_order = kMaxSDELayers; 494 uint32_t color = 0; 495 LayerRect roi = {}; 496 bool is_exclusion_rect = false; 497 LayerSolidFill solid_fill_info = {}; 498 }; 499 500 struct HWLayerConfig { 501 HWPipeInfo left_pipe {}; // pipe for left side of output 502 HWPipeInfo right_pipe {}; // pipe for right side of output 503 HWRotatorSession hw_rotator_session {}; 504 HWSolidfillStage hw_solidfill_stage {}; 505 float compression = 1.0f; 506 bool use_solidfill_stage = false; 507 }; 508 509 struct HWHDRLayerInfo { 510 enum HDROperation { 511 kNoOp, // No-op. 512 kSet, // Sets the HDR MetaData - Start of HDR 513 kReset, // resets the previously set HDR Metadata, End of HDR 514 }; 515 516 int32_t layer_index = -1; 517 HDROperation operation = kNoOp; 518 }; 519 520 struct HWLayersInfo { 521 LayerStack *stack = NULL; // Input layer stack. Set by the caller. 522 uint32_t app_layer_count = 0; // Total number of app layers. Must not be 0. 523 uint32_t gpu_target_index = 0; // GPU target layer index. 0 if not present. 524 std::vector<Layer> hw_layers = {}; // Layers which need to be programmed on the HW 525 std::vector<uint32_t> index {}; // Indexes of the layers from the layer stack which need to 526 std::vector<uint32_t> roi_index {}; // Stores the ROI index where the layers are visible. 527 int sync_handle = -1; // Release fence id for current draw cycle. 528 int set_idle_time_ms = -1; // Set idle time to the new specified value. 529 // -1 indicates no change in idle time since last set value. 530 std::vector<LayerRect> left_frame_roi = {}; // Left ROI. 531 std::vector<LayerRect> right_frame_roi = {}; // Right ROI. 532 LayerRect partial_fb_roi = {}; // Damaged area in framebuffer. 533 bool roi_split = false; // Indicates separated left and right ROI 534 bool async_cursor_updates = false; // Cursor layer allowed to have async updates 535 DestScaleInfoMap dest_scale_info_map = {}; 536 HWHDRLayerInfo hdr_layer_info = {}; 537 Handle pvt_data = NULL; // Private data used by sdm extension only. 538 }; 539 540 struct HWQosData { 541 uint64_t core_ab_bps = 0; 542 uint64_t core_ib_bps = 0; 543 uint64_t llcc_ab_bps = 0; 544 uint64_t llcc_ib_bps = 0; 545 uint64_t dram_ab_bps = 0; 546 uint64_t dram_ib_bps = 0; 547 uint64_t rot_prefill_bw_bps = 0; 548 uint32_t clock_hz = 0; 549 uint32_t rot_clock_hz = 0; 550 }; 551 552 struct HWLayers { 553 HWLayersInfo info {}; 554 HWLayerConfig config[kMaxSDELayers] {}; 555 float output_compression = 1.0f; 556 HWQosData qos_data = {}; 557 HWAVRInfo hw_avr_info = {}; 558 }; 559 560 struct HWDisplayAttributes : DisplayConfigVariableInfo { 561 bool is_device_split = false; 562 uint32_t v_front_porch = 0; //!< Vertical front porch of panel 563 uint32_t v_back_porch = 0; //!< Vertical back porch of panel 564 uint32_t v_pulse_width = 0; //!< Vertical pulse width of panel 565 uint32_t h_total = 0; //!< Total width of panel (hActive + hFP + hBP + hPulseWidth) 566 uint32_t v_total = 0; //!< Total height of panel (vActive + vFP + vBP + vPulseWidth) 567 std::bitset<32> s3d_config {}; //!< Stores the bit mask of S3D modes 568 uint32_t clock_khz = 0; //!< Stores the pixel clock of panel in khz 569 HWTopology topology = kUnknown; //!< Stores the topology information. 570 571 bool operator !=(const HWDisplayAttributes &display_attributes) { 572 return ((is_device_split != display_attributes.is_device_split) || 573 (x_pixels != display_attributes.x_pixels) || 574 (y_pixels != display_attributes.y_pixels) || 575 (x_dpi != display_attributes.x_dpi) || 576 (y_dpi != display_attributes.y_dpi) || 577 (fps != display_attributes.fps) || 578 (vsync_period_ns != display_attributes.vsync_period_ns) || 579 (v_front_porch != display_attributes.v_front_porch) || 580 (v_back_porch != display_attributes.v_back_porch) || 581 (v_pulse_width != display_attributes.v_pulse_width) || 582 (h_total != display_attributes.h_total) || 583 (is_yuv != display_attributes.is_yuv) || 584 (s3d_config != display_attributes.s3d_config) || 585 (clock_khz != display_attributes.clock_khz) || 586 (topology != display_attributes.topology)); 587 } 588 589 bool operator ==(const HWDisplayAttributes &display_attributes) { 590 return !(operator !=(display_attributes)); 591 } 592 }; 593 594 struct HWMixerAttributes { 595 uint32_t width = 0; // Layer mixer width 596 uint32_t height = 0; // Layer mixer height 597 uint32_t split_left = 0; 598 LayerBufferFormat output_format = kFormatRGB101010; // Layer mixer output format 599 600 bool operator !=(const HWMixerAttributes &mixer_attributes) { 601 return ((width != mixer_attributes.width) || 602 (height != mixer_attributes.height) || 603 (output_format != mixer_attributes.output_format) || 604 (split_left != mixer_attributes.split_left)); 605 } 606 607 bool operator ==(const HWMixerAttributes &mixer_attributes) { 608 return !(operator !=(mixer_attributes)); 609 } 610 IsValidHWMixerAttributes611 bool IsValid() { 612 return (width > 0 && height > 0); 613 } 614 }; 615 616 } // namespace sdm 617 618 #endif // __HW_INFO_TYPES_H__ 619 620