1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * From coreboot file of same name
4 *
5 * Copyright (C) 2008-2009 coresystems GmbH
6 * Copyright (C) 2014 Google, Inc
7 */
8
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/lapic.h>
12 #include <asm/msr.h>
13 #include <asm/msr-index.h>
14 #include <asm/post.h>
15
lapic_read(unsigned long reg)16 unsigned long lapic_read(unsigned long reg)
17 {
18 return readl(LAPIC_DEFAULT_BASE + reg);
19 }
20
21 #define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
22 sizeof(*(ptr))))
23
24 struct __xchg_dummy { unsigned long a[100]; };
25 #define __xg(x) ((struct __xchg_dummy *)(x))
26
27 /*
28 * Note: no "lock" prefix even on SMP. xchg always implies lock anyway.
29 *
30 * Note 2: xchg has side effect, so that attribute volatile is necessary,
31 * but generally the primitive is invalid, *ptr is output argument.
32 */
__xchg(unsigned long x,volatile void * ptr,int size)33 static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
34 int size)
35 {
36 switch (size) {
37 case 1:
38 __asm__ __volatile__("xchgb %b0,%1"
39 : "=q" (x)
40 : "m" (*__xg(ptr)), "0" (x)
41 : "memory");
42 break;
43 case 2:
44 __asm__ __volatile__("xchgw %w0,%1"
45 : "=r" (x)
46 : "m" (*__xg(ptr)), "0" (x)
47 : "memory");
48 break;
49 case 4:
50 __asm__ __volatile__("xchgl %0,%1"
51 : "=r" (x)
52 : "m" (*__xg(ptr)), "0" (x)
53 : "memory");
54 break;
55 }
56
57 return x;
58 }
59
lapic_write(unsigned long reg,unsigned long v)60 void lapic_write(unsigned long reg, unsigned long v)
61 {
62 (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
63 }
64
enable_lapic(void)65 void enable_lapic(void)
66 {
67 if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
68 msr_t msr;
69
70 msr = msr_read(MSR_IA32_APICBASE);
71 msr.hi &= 0xffffff00;
72 msr.lo |= MSR_IA32_APICBASE_ENABLE;
73 msr.lo &= ~MSR_IA32_APICBASE_BASE;
74 msr.lo |= LAPIC_DEFAULT_BASE;
75 msr_write(MSR_IA32_APICBASE, msr);
76 }
77 }
78
disable_lapic(void)79 void disable_lapic(void)
80 {
81 if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
82 msr_t msr;
83
84 msr = msr_read(MSR_IA32_APICBASE);
85 msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
86 msr_write(MSR_IA32_APICBASE, msr);
87 }
88 }
89
lapicid(void)90 unsigned long lapicid(void)
91 {
92 return lapic_read(LAPIC_ID) >> 24;
93 }
94
lapic_wait_icr_idle(void)95 static void lapic_wait_icr_idle(void)
96 {
97 do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY);
98 }
99
lapic_remote_read(int apicid,int reg,unsigned long * pvalue)100 int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
101 {
102 int timeout;
103 unsigned long status;
104 int result;
105
106 lapic_wait_icr_idle();
107 lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
108 lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
109
110 timeout = 0;
111 do {
112 status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
113 } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
114
115 result = -1;
116 if (status == LAPIC_ICR_RR_VALID) {
117 *pvalue = lapic_read(LAPIC_RRR);
118 result = 0;
119 }
120
121 return result;
122 }
123
lapic_setup(void)124 void lapic_setup(void)
125 {
126 /* Only Pentium Pro and later have those MSR stuff */
127 debug("Setting up local apic: ");
128
129 /* Enable the local apic */
130 enable_lapic();
131
132 /* Set Task Priority to 'accept all' */
133 lapic_write(LAPIC_TASKPRI,
134 lapic_read(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
135
136 /* Put the local apic in virtual wire mode */
137 lapic_write(LAPIC_SPIV, (lapic_read(LAPIC_SPIV) &
138 ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
139 lapic_write(LAPIC_LVT0, (lapic_read(LAPIC_LVT0) &
140 ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
141 LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
142 LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
143 LAPIC_DELIVERY_MODE_MASK)) |
144 (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
145 LAPIC_DELIVERY_MODE_EXTINT));
146 lapic_write(LAPIC_LVT1, (lapic_read(LAPIC_LVT1) &
147 ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
148 LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
149 LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
150 LAPIC_DELIVERY_MODE_MASK)) |
151 (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
152 LAPIC_DELIVERY_MODE_NMI));
153
154 debug("apic_id: 0x%02lx, ", lapicid());
155
156 debug("done.\n");
157 post_code(POST_LAPIC);
158 }
159