1 /*
2 * tools/testing/selftests/kvm/lib/x86_64/vmx.c
3 *
4 * Copyright (C) 2018, Google LLC.
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2.
7 */
8
9 #define _GNU_SOURCE /* for program_invocation_name */
10
11 #include "test_util.h"
12 #include "kvm_util.h"
13 #include "processor.h"
14 #include "vmx.h"
15
16 bool enable_evmcs;
17
18 /* Allocate memory regions for nested VMX tests.
19 *
20 * Input Args:
21 * vm - The VM to allocate guest-virtual addresses in.
22 *
23 * Output Args:
24 * p_vmx_gva - The guest virtual address for the struct vmx_pages.
25 *
26 * Return:
27 * Pointer to structure with the addresses of the VMX areas.
28 */
29 struct vmx_pages *
vcpu_alloc_vmx(struct kvm_vm * vm,vm_vaddr_t * p_vmx_gva)30 vcpu_alloc_vmx(struct kvm_vm *vm, vm_vaddr_t *p_vmx_gva)
31 {
32 vm_vaddr_t vmx_gva = vm_vaddr_alloc(vm, getpagesize(), 0x10000, 0, 0);
33 struct vmx_pages *vmx = addr_gva2hva(vm, vmx_gva);
34
35 /* Setup of a region of guest memory for the vmxon region. */
36 vmx->vmxon = (void *)vm_vaddr_alloc(vm, getpagesize(), 0x10000, 0, 0);
37 vmx->vmxon_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmxon);
38 vmx->vmxon_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmxon);
39
40 /* Setup of a region of guest memory for a vmcs. */
41 vmx->vmcs = (void *)vm_vaddr_alloc(vm, getpagesize(), 0x10000, 0, 0);
42 vmx->vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmcs);
43 vmx->vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmcs);
44
45 /* Setup of a region of guest memory for the MSR bitmap. */
46 vmx->msr = (void *)vm_vaddr_alloc(vm, getpagesize(), 0x10000, 0, 0);
47 vmx->msr_hva = addr_gva2hva(vm, (uintptr_t)vmx->msr);
48 vmx->msr_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->msr);
49 memset(vmx->msr_hva, 0, getpagesize());
50
51 /* Setup of a region of guest memory for the shadow VMCS. */
52 vmx->shadow_vmcs = (void *)vm_vaddr_alloc(vm, getpagesize(), 0x10000, 0, 0);
53 vmx->shadow_vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->shadow_vmcs);
54 vmx->shadow_vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->shadow_vmcs);
55
56 /* Setup of a region of guest memory for the VMREAD and VMWRITE bitmaps. */
57 vmx->vmread = (void *)vm_vaddr_alloc(vm, getpagesize(), 0x10000, 0, 0);
58 vmx->vmread_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmread);
59 vmx->vmread_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmread);
60 memset(vmx->vmread_hva, 0, getpagesize());
61
62 vmx->vmwrite = (void *)vm_vaddr_alloc(vm, getpagesize(), 0x10000, 0, 0);
63 vmx->vmwrite_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmwrite);
64 vmx->vmwrite_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmwrite);
65 memset(vmx->vmwrite_hva, 0, getpagesize());
66
67 /* Setup of a region of guest memory for the VP Assist page. */
68 vmx->vp_assist = (void *)vm_vaddr_alloc(vm, getpagesize(),
69 0x10000, 0, 0);
70 vmx->vp_assist_hva = addr_gva2hva(vm, (uintptr_t)vmx->vp_assist);
71 vmx->vp_assist_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vp_assist);
72
73 /* Setup of a region of guest memory for the enlightened VMCS. */
74 vmx->enlightened_vmcs = (void *)vm_vaddr_alloc(vm, getpagesize(),
75 0x10000, 0, 0);
76 vmx->enlightened_vmcs_hva =
77 addr_gva2hva(vm, (uintptr_t)vmx->enlightened_vmcs);
78 vmx->enlightened_vmcs_gpa =
79 addr_gva2gpa(vm, (uintptr_t)vmx->enlightened_vmcs);
80
81 *p_vmx_gva = vmx_gva;
82 return vmx;
83 }
84
prepare_for_vmx_operation(struct vmx_pages * vmx)85 bool prepare_for_vmx_operation(struct vmx_pages *vmx)
86 {
87 uint64_t feature_control;
88 uint64_t required;
89 unsigned long cr0;
90 unsigned long cr4;
91
92 /*
93 * Ensure bits in CR0 and CR4 are valid in VMX operation:
94 * - Bit X is 1 in _FIXED0: bit X is fixed to 1 in CRx.
95 * - Bit X is 0 in _FIXED1: bit X is fixed to 0 in CRx.
96 */
97 __asm__ __volatile__("mov %%cr0, %0" : "=r"(cr0) : : "memory");
98 cr0 &= rdmsr(MSR_IA32_VMX_CR0_FIXED1);
99 cr0 |= rdmsr(MSR_IA32_VMX_CR0_FIXED0);
100 __asm__ __volatile__("mov %0, %%cr0" : : "r"(cr0) : "memory");
101
102 __asm__ __volatile__("mov %%cr4, %0" : "=r"(cr4) : : "memory");
103 cr4 &= rdmsr(MSR_IA32_VMX_CR4_FIXED1);
104 cr4 |= rdmsr(MSR_IA32_VMX_CR4_FIXED0);
105 /* Enable VMX operation */
106 cr4 |= X86_CR4_VMXE;
107 __asm__ __volatile__("mov %0, %%cr4" : : "r"(cr4) : "memory");
108
109 /*
110 * Configure IA32_FEATURE_CONTROL MSR to allow VMXON:
111 * Bit 0: Lock bit. If clear, VMXON causes a #GP.
112 * Bit 2: Enables VMXON outside of SMX operation. If clear, VMXON
113 * outside of SMX causes a #GP.
114 */
115 required = FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
116 required |= FEATURE_CONTROL_LOCKED;
117 feature_control = rdmsr(MSR_IA32_FEATURE_CONTROL);
118 if ((feature_control & required) != required)
119 wrmsr(MSR_IA32_FEATURE_CONTROL, feature_control | required);
120
121 /* Enter VMX root operation. */
122 *(uint32_t *)(vmx->vmxon) = vmcs_revision();
123 if (vmxon(vmx->vmxon_gpa))
124 return false;
125
126 return true;
127 }
128
load_vmcs(struct vmx_pages * vmx)129 bool load_vmcs(struct vmx_pages *vmx)
130 {
131 if (!enable_evmcs) {
132 /* Load a VMCS. */
133 *(uint32_t *)(vmx->vmcs) = vmcs_revision();
134 if (vmclear(vmx->vmcs_gpa))
135 return false;
136
137 if (vmptrld(vmx->vmcs_gpa))
138 return false;
139
140 /* Setup shadow VMCS, do not load it yet. */
141 *(uint32_t *)(vmx->shadow_vmcs) =
142 vmcs_revision() | 0x80000000ul;
143 if (vmclear(vmx->shadow_vmcs_gpa))
144 return false;
145 } else {
146 if (evmcs_vmptrld(vmx->enlightened_vmcs_gpa,
147 vmx->enlightened_vmcs))
148 return false;
149 current_evmcs->revision_id = vmcs_revision();
150 }
151
152 return true;
153 }
154
155 /*
156 * Initialize the control fields to the most basic settings possible.
157 */
init_vmcs_control_fields(struct vmx_pages * vmx)158 static inline void init_vmcs_control_fields(struct vmx_pages *vmx)
159 {
160 vmwrite(VIRTUAL_PROCESSOR_ID, 0);
161 vmwrite(POSTED_INTR_NV, 0);
162
163 vmwrite(PIN_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS));
164 if (!vmwrite(SECONDARY_VM_EXEC_CONTROL, 0))
165 vmwrite(CPU_BASED_VM_EXEC_CONTROL,
166 rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
167 else
168 vmwrite(CPU_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS));
169 vmwrite(EXCEPTION_BITMAP, 0);
170 vmwrite(PAGE_FAULT_ERROR_CODE_MASK, 0);
171 vmwrite(PAGE_FAULT_ERROR_CODE_MATCH, -1); /* Never match */
172 vmwrite(CR3_TARGET_COUNT, 0);
173 vmwrite(VM_EXIT_CONTROLS, rdmsr(MSR_IA32_VMX_EXIT_CTLS) |
174 VM_EXIT_HOST_ADDR_SPACE_SIZE); /* 64-bit host */
175 vmwrite(VM_EXIT_MSR_STORE_COUNT, 0);
176 vmwrite(VM_EXIT_MSR_LOAD_COUNT, 0);
177 vmwrite(VM_ENTRY_CONTROLS, rdmsr(MSR_IA32_VMX_ENTRY_CTLS) |
178 VM_ENTRY_IA32E_MODE); /* 64-bit guest */
179 vmwrite(VM_ENTRY_MSR_LOAD_COUNT, 0);
180 vmwrite(VM_ENTRY_INTR_INFO_FIELD, 0);
181 vmwrite(TPR_THRESHOLD, 0);
182
183 vmwrite(CR0_GUEST_HOST_MASK, 0);
184 vmwrite(CR4_GUEST_HOST_MASK, 0);
185 vmwrite(CR0_READ_SHADOW, get_cr0());
186 vmwrite(CR4_READ_SHADOW, get_cr4());
187
188 vmwrite(MSR_BITMAP, vmx->msr_gpa);
189 vmwrite(VMREAD_BITMAP, vmx->vmread_gpa);
190 vmwrite(VMWRITE_BITMAP, vmx->vmwrite_gpa);
191 }
192
193 /*
194 * Initialize the host state fields based on the current host state, with
195 * the exception of HOST_RSP and HOST_RIP, which should be set by vmlaunch
196 * or vmresume.
197 */
init_vmcs_host_state(void)198 static inline void init_vmcs_host_state(void)
199 {
200 uint32_t exit_controls = vmreadz(VM_EXIT_CONTROLS);
201
202 vmwrite(HOST_ES_SELECTOR, get_es());
203 vmwrite(HOST_CS_SELECTOR, get_cs());
204 vmwrite(HOST_SS_SELECTOR, get_ss());
205 vmwrite(HOST_DS_SELECTOR, get_ds());
206 vmwrite(HOST_FS_SELECTOR, get_fs());
207 vmwrite(HOST_GS_SELECTOR, get_gs());
208 vmwrite(HOST_TR_SELECTOR, get_tr());
209
210 if (exit_controls & VM_EXIT_LOAD_IA32_PAT)
211 vmwrite(HOST_IA32_PAT, rdmsr(MSR_IA32_CR_PAT));
212 if (exit_controls & VM_EXIT_LOAD_IA32_EFER)
213 vmwrite(HOST_IA32_EFER, rdmsr(MSR_EFER));
214 if (exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
215 vmwrite(HOST_IA32_PERF_GLOBAL_CTRL,
216 rdmsr(MSR_CORE_PERF_GLOBAL_CTRL));
217
218 vmwrite(HOST_IA32_SYSENTER_CS, rdmsr(MSR_IA32_SYSENTER_CS));
219
220 vmwrite(HOST_CR0, get_cr0());
221 vmwrite(HOST_CR3, get_cr3());
222 vmwrite(HOST_CR4, get_cr4());
223 vmwrite(HOST_FS_BASE, rdmsr(MSR_FS_BASE));
224 vmwrite(HOST_GS_BASE, rdmsr(MSR_GS_BASE));
225 vmwrite(HOST_TR_BASE,
226 get_desc64_base((struct desc64 *)(get_gdt_base() + get_tr())));
227 vmwrite(HOST_GDTR_BASE, get_gdt_base());
228 vmwrite(HOST_IDTR_BASE, get_idt_base());
229 vmwrite(HOST_IA32_SYSENTER_ESP, rdmsr(MSR_IA32_SYSENTER_ESP));
230 vmwrite(HOST_IA32_SYSENTER_EIP, rdmsr(MSR_IA32_SYSENTER_EIP));
231 }
232
233 /*
234 * Initialize the guest state fields essentially as a clone of
235 * the host state fields. Some host state fields have fixed
236 * values, and we set the corresponding guest state fields accordingly.
237 */
init_vmcs_guest_state(void * rip,void * rsp)238 static inline void init_vmcs_guest_state(void *rip, void *rsp)
239 {
240 vmwrite(GUEST_ES_SELECTOR, vmreadz(HOST_ES_SELECTOR));
241 vmwrite(GUEST_CS_SELECTOR, vmreadz(HOST_CS_SELECTOR));
242 vmwrite(GUEST_SS_SELECTOR, vmreadz(HOST_SS_SELECTOR));
243 vmwrite(GUEST_DS_SELECTOR, vmreadz(HOST_DS_SELECTOR));
244 vmwrite(GUEST_FS_SELECTOR, vmreadz(HOST_FS_SELECTOR));
245 vmwrite(GUEST_GS_SELECTOR, vmreadz(HOST_GS_SELECTOR));
246 vmwrite(GUEST_LDTR_SELECTOR, 0);
247 vmwrite(GUEST_TR_SELECTOR, vmreadz(HOST_TR_SELECTOR));
248 vmwrite(GUEST_INTR_STATUS, 0);
249 vmwrite(GUEST_PML_INDEX, 0);
250
251 vmwrite(VMCS_LINK_POINTER, -1ll);
252 vmwrite(GUEST_IA32_DEBUGCTL, 0);
253 vmwrite(GUEST_IA32_PAT, vmreadz(HOST_IA32_PAT));
254 vmwrite(GUEST_IA32_EFER, vmreadz(HOST_IA32_EFER));
255 vmwrite(GUEST_IA32_PERF_GLOBAL_CTRL,
256 vmreadz(HOST_IA32_PERF_GLOBAL_CTRL));
257
258 vmwrite(GUEST_ES_LIMIT, -1);
259 vmwrite(GUEST_CS_LIMIT, -1);
260 vmwrite(GUEST_SS_LIMIT, -1);
261 vmwrite(GUEST_DS_LIMIT, -1);
262 vmwrite(GUEST_FS_LIMIT, -1);
263 vmwrite(GUEST_GS_LIMIT, -1);
264 vmwrite(GUEST_LDTR_LIMIT, -1);
265 vmwrite(GUEST_TR_LIMIT, 0x67);
266 vmwrite(GUEST_GDTR_LIMIT, 0xffff);
267 vmwrite(GUEST_IDTR_LIMIT, 0xffff);
268 vmwrite(GUEST_ES_AR_BYTES,
269 vmreadz(GUEST_ES_SELECTOR) == 0 ? 0x10000 : 0xc093);
270 vmwrite(GUEST_CS_AR_BYTES, 0xa09b);
271 vmwrite(GUEST_SS_AR_BYTES, 0xc093);
272 vmwrite(GUEST_DS_AR_BYTES,
273 vmreadz(GUEST_DS_SELECTOR) == 0 ? 0x10000 : 0xc093);
274 vmwrite(GUEST_FS_AR_BYTES,
275 vmreadz(GUEST_FS_SELECTOR) == 0 ? 0x10000 : 0xc093);
276 vmwrite(GUEST_GS_AR_BYTES,
277 vmreadz(GUEST_GS_SELECTOR) == 0 ? 0x10000 : 0xc093);
278 vmwrite(GUEST_LDTR_AR_BYTES, 0x10000);
279 vmwrite(GUEST_TR_AR_BYTES, 0x8b);
280 vmwrite(GUEST_INTERRUPTIBILITY_INFO, 0);
281 vmwrite(GUEST_ACTIVITY_STATE, 0);
282 vmwrite(GUEST_SYSENTER_CS, vmreadz(HOST_IA32_SYSENTER_CS));
283 vmwrite(VMX_PREEMPTION_TIMER_VALUE, 0);
284
285 vmwrite(GUEST_CR0, vmreadz(HOST_CR0));
286 vmwrite(GUEST_CR3, vmreadz(HOST_CR3));
287 vmwrite(GUEST_CR4, vmreadz(HOST_CR4));
288 vmwrite(GUEST_ES_BASE, 0);
289 vmwrite(GUEST_CS_BASE, 0);
290 vmwrite(GUEST_SS_BASE, 0);
291 vmwrite(GUEST_DS_BASE, 0);
292 vmwrite(GUEST_FS_BASE, vmreadz(HOST_FS_BASE));
293 vmwrite(GUEST_GS_BASE, vmreadz(HOST_GS_BASE));
294 vmwrite(GUEST_LDTR_BASE, 0);
295 vmwrite(GUEST_TR_BASE, vmreadz(HOST_TR_BASE));
296 vmwrite(GUEST_GDTR_BASE, vmreadz(HOST_GDTR_BASE));
297 vmwrite(GUEST_IDTR_BASE, vmreadz(HOST_IDTR_BASE));
298 vmwrite(GUEST_DR7, 0x400);
299 vmwrite(GUEST_RSP, (uint64_t)rsp);
300 vmwrite(GUEST_RIP, (uint64_t)rip);
301 vmwrite(GUEST_RFLAGS, 2);
302 vmwrite(GUEST_PENDING_DBG_EXCEPTIONS, 0);
303 vmwrite(GUEST_SYSENTER_ESP, vmreadz(HOST_IA32_SYSENTER_ESP));
304 vmwrite(GUEST_SYSENTER_EIP, vmreadz(HOST_IA32_SYSENTER_EIP));
305 }
306
prepare_vmcs(struct vmx_pages * vmx,void * guest_rip,void * guest_rsp)307 void prepare_vmcs(struct vmx_pages *vmx, void *guest_rip, void *guest_rsp)
308 {
309 init_vmcs_control_fields(vmx);
310 init_vmcs_host_state();
311 init_vmcs_guest_state(guest_rip, guest_rsp);
312 }
313