1 /*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <assert.h>
9 #include <debug.h>
10 #include <delay_timer.h>
11 #include <m0_ctl.h>
12 #include <mmio.h>
13 #include <plat_private.h>
14 #include <rk3399_def.h>
15 #include <secure.h>
16 #include <soc.h>
17
m0_init(void)18 void m0_init(void)
19 {
20 /* secure config for M0 */
21 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7));
22 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), WMSK_BIT(12));
23
24 /* set the execute address for M0 */
25 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3),
26 BITS_WITH_WMASK((M0_BINCODE_BASE >> 12) & 0xffff,
27 0xffff, 0));
28 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7),
29 BITS_WITH_WMASK((M0_BINCODE_BASE >> 28) & 0xf,
30 0xf, 0));
31
32 /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */
33 mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02);
34
35 /*
36 * To switch the parent to xin24M and div == 1,
37 *
38 * We need to close most of the PLLs and clocks except the OSC 24MHz
39 * durning suspend, and this should be enough to supplies the ddrfreq,
40 * For the simple handle, we just keep the fixed 24MHz to supply the
41 * suspend and ddrfreq directly.
42 */
43 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0,
44 BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8));
45
46 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5));
47 }
48
m0_start(void)49 void m0_start(void)
50 {
51 /* enable clocks for M0 */
52 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
53 BITS_WITH_WMASK(0x0, 0xf, 0));
54
55 /* clean the PARAM_M0_DONE flag, mean that M0 will start working */
56 mmio_write_32(M0_PARAM_ADDR + PARAM_M0_DONE, 0);
57 dmbst();
58
59 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
60 BITS_WITH_WMASK(0x0, 0x4, 0));
61
62 udelay(5);
63 /* start M0 */
64 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
65 BITS_WITH_WMASK(0x0, 0x20, 0));
66 dmbst();
67 }
68
m0_stop(void)69 void m0_stop(void)
70 {
71 /* stop M0 */
72 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
73 BITS_WITH_WMASK(0x24, 0x24, 0));
74
75 /* disable clocks for M0 */
76 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
77 BITS_WITH_WMASK(0xf, 0xf, 0));
78 }
79
m0_wait_done(void)80 void m0_wait_done(void)
81 {
82 do {
83 /*
84 * Don't starve the M0 for access to SRAM, so delay before
85 * reading the PARAM_M0_DONE value again.
86 */
87 udelay(5);
88 dsb();
89 } while (mmio_read_32(M0_PARAM_ADDR + PARAM_M0_DONE) != M0_DONE_FLAG);
90
91 /*
92 * Let the M0 settle into WFI before we leave. This is so we don't reset
93 * the M0 in a bad spot which can cause problems with the M0.
94 */
95 udelay(10);
96 dsb();
97 }
98