1 /*
2 * Copyright 2013 Vadim Girlin <vadimgirlin@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Vadim Girlin
25 */
26
27 #define PSC_DEBUG 0
28
29 #if PSC_DEBUG
30 #define PSC_DUMP(a) do { a } while (0)
31 #else
32 #define PSC_DUMP(a)
33 #endif
34
35 #include "sb_bc.h"
36 #include "sb_shader.h"
37 #include "sb_pass.h"
38 #include "sb_sched.h"
39 #include "eg_sq.h" // V_SQ_CF_INDEX_NONE/0/1
40
41 namespace r600_sb {
42
rp_kcache_tracker(shader & sh)43 rp_kcache_tracker::rp_kcache_tracker(shader &sh) : rp(), uc(),
44 // FIXME: for now we'll use "two const pairs" limit for r600, same as
45 // for other chips, otherwise additional check in alu_group_tracker is
46 // required to make sure that all 4 consts in the group fit into 2
47 // kcache sets
48 sel_count(2) {}
49
try_reserve(sel_chan r)50 bool rp_kcache_tracker::try_reserve(sel_chan r) {
51 unsigned sel = kc_sel(r);
52
53 for (unsigned i = 0; i < sel_count; ++i) {
54 if (rp[i] == 0) {
55 rp[i] = sel;
56 ++uc[i];
57 return true;
58 }
59 if (rp[i] == sel) {
60 ++uc[i];
61 return true;
62 }
63 }
64 return false;
65 }
66
try_reserve(node * n)67 bool rp_kcache_tracker::try_reserve(node* n) {
68 bool need_unreserve = false;
69 vvec::iterator I(n->src.begin()), E(n->src.end());
70
71 for (; I != E; ++I) {
72 value *v = *I;
73 if (v->is_kcache()) {
74 if (!try_reserve(v->select))
75 break;
76 else
77 need_unreserve = true;
78 }
79 }
80 if (I == E)
81 return true;
82
83 if (need_unreserve && I != n->src.begin()) {
84 do {
85 --I;
86 value *v =*I;
87 if (v->is_kcache())
88 unreserve(v->select);
89 } while (I != n->src.begin());
90 }
91 return false;
92 }
93
94 inline
unreserve(node * n)95 void rp_kcache_tracker::unreserve(node* n) {
96 vvec::iterator I(n->src.begin()), E(n->src.end());
97 for (; I != E; ++I) {
98 value *v = *I;
99 if (v->is_kcache())
100 unreserve(v->select);
101 }
102 }
103
unreserve(sel_chan r)104 void rp_kcache_tracker::unreserve(sel_chan r) {
105 unsigned sel = kc_sel(r);
106
107 for (unsigned i = 0; i < sel_count; ++i)
108 if (rp[i] == sel) {
109 if (--uc[i] == 0)
110 rp[i] = 0;
111 return;
112 }
113 assert(0);
114 return;
115 }
116
try_reserve(alu_node * n)117 bool literal_tracker::try_reserve(alu_node* n) {
118 bool need_unreserve = false;
119
120 vvec::iterator I(n->src.begin()), E(n->src.end());
121
122 for (; I != E; ++I) {
123 value *v = *I;
124 if (v->is_literal()) {
125 if (!try_reserve(v->literal_value))
126 break;
127 else
128 need_unreserve = true;
129 }
130 }
131 if (I == E)
132 return true;
133
134 if (need_unreserve && I != n->src.begin()) {
135 do {
136 --I;
137 value *v =*I;
138 if (v->is_literal())
139 unreserve(v->literal_value);
140 } while (I != n->src.begin());
141 }
142 return false;
143 }
144
unreserve(alu_node * n)145 void literal_tracker::unreserve(alu_node* n) {
146 unsigned nsrc = n->bc.op_ptr->src_count, i;
147
148 for (i = 0; i < nsrc; ++i) {
149 value *v = n->src[i];
150 if (v->is_literal())
151 unreserve(v->literal_value);
152 }
153 }
154
try_reserve(literal l)155 bool literal_tracker::try_reserve(literal l) {
156
157 PSC_DUMP( sblog << "literal reserve " << l.u << " " << l.f << "\n"; );
158
159 for (unsigned i = 0; i < MAX_ALU_LITERALS; ++i) {
160 if (lt[i] == 0) {
161 lt[i] = l;
162 ++uc[i];
163 PSC_DUMP( sblog << " reserved new uc = " << uc[i] << "\n"; );
164 return true;
165 } else if (lt[i] == l) {
166 ++uc[i];
167 PSC_DUMP( sblog << " reserved uc = " << uc[i] << "\n"; );
168 return true;
169 }
170 }
171 PSC_DUMP( sblog << " failed to reserve literal\n"; );
172 return false;
173 }
174
unreserve(literal l)175 void literal_tracker::unreserve(literal l) {
176
177 PSC_DUMP( sblog << "literal unreserve " << l.u << " " << l.f << "\n"; );
178
179 for (unsigned i = 0; i < MAX_ALU_LITERALS; ++i) {
180 if (lt[i] == l) {
181 if (--uc[i] == 0)
182 lt[i] = 0;
183 return;
184 }
185 }
186 assert(0);
187 return;
188 }
189
bs_cycle_vector(unsigned bs,unsigned src)190 static inline unsigned bs_cycle_vector(unsigned bs, unsigned src) {
191 static const unsigned swz[VEC_NUM][3] = {
192 {0, 1, 2}, {0, 2, 1}, {1, 2, 0}, {1, 0, 2}, {2, 0, 1}, {2, 1, 0}
193 };
194 assert(bs < VEC_NUM && src < 3);
195 return swz[bs][src];
196 }
197
bs_cycle_scalar(unsigned bs,unsigned src)198 static inline unsigned bs_cycle_scalar(unsigned bs, unsigned src) {
199 static const unsigned swz[SCL_NUM][3] = {
200 {2, 1, 0}, {1, 2, 2}, {2, 1, 2}, {2, 2, 1}
201 };
202
203 if (bs >= SCL_NUM || src >= 3) {
204 // this prevents gcc warning "array subscript is above array bounds"
205 // AFAICS we should never hit this path
206 abort();
207 }
208 return swz[bs][src];
209 }
210
bs_cycle(bool trans,unsigned bs,unsigned src)211 static inline unsigned bs_cycle(bool trans, unsigned bs, unsigned src) {
212 return trans ? bs_cycle_scalar(bs, src) : bs_cycle_vector(bs, src);
213 }
214
215 inline
try_reserve(unsigned cycle,unsigned sel,unsigned chan)216 bool rp_gpr_tracker::try_reserve(unsigned cycle, unsigned sel, unsigned chan) {
217 ++sel;
218 if (rp[cycle][chan] == 0) {
219 rp[cycle][chan] = sel;
220 ++uc[cycle][chan];
221 return true;
222 } else if (rp[cycle][chan] == sel) {
223 ++uc[cycle][chan];
224 return true;
225 }
226 return false;
227 }
228
229 inline
unreserve(alu_node * n)230 void rp_gpr_tracker::unreserve(alu_node* n) {
231 unsigned nsrc = n->bc.op_ptr->src_count, i;
232 unsigned trans = n->bc.slot == SLOT_TRANS;
233 unsigned bs = n->bc.bank_swizzle;
234 unsigned opt = !trans
235 && n->bc.src[0].sel == n->bc.src[1].sel
236 && n->bc.src[0].chan == n->bc.src[1].chan;
237
238 for (i = 0; i < nsrc; ++i) {
239 value *v = n->src[i];
240 if (v->is_readonly() || v->is_undef())
241 continue;
242 if (i == 1 && opt)
243 continue;
244 unsigned cycle = bs_cycle(trans, bs, i);
245 unreserve(cycle, n->bc.src[i].sel, n->bc.src[i].chan);
246 }
247 }
248
249 inline
unreserve(unsigned cycle,unsigned sel,unsigned chan)250 void rp_gpr_tracker::unreserve(unsigned cycle, unsigned sel, unsigned chan) {
251 ++sel;
252 assert(rp[cycle][chan] == sel && uc[cycle][chan]);
253 if (--uc[cycle][chan] == 0)
254 rp[cycle][chan] = 0;
255 }
256
257 inline
try_reserve(alu_node * n)258 bool rp_gpr_tracker::try_reserve(alu_node* n) {
259 unsigned nsrc = n->bc.op_ptr->src_count, i;
260 unsigned trans = n->bc.slot == SLOT_TRANS;
261 unsigned bs = n->bc.bank_swizzle;
262 unsigned opt = !trans && nsrc >= 2 &&
263 n->src[0] == n->src[1];
264
265 bool need_unreserve = false;
266 unsigned const_count = 0, min_gpr_cycle = 3;
267
268 for (i = 0; i < nsrc; ++i) {
269 value *v = n->src[i];
270 if (v->is_readonly() || v->is_undef()) {
271 const_count++;
272 if (trans && const_count == 3)
273 break;
274 } else {
275 if (i == 1 && opt)
276 continue;
277
278 unsigned cycle = bs_cycle(trans, bs, i);
279
280 if (trans && cycle < min_gpr_cycle)
281 min_gpr_cycle = cycle;
282
283 if (const_count && cycle < const_count && trans)
284 break;
285
286 if (!try_reserve(cycle, n->bc.src[i].sel, n->bc.src[i].chan))
287 break;
288 else
289 need_unreserve = true;
290 }
291 }
292
293 if ((i == nsrc) && (min_gpr_cycle + 1 > const_count))
294 return true;
295
296 if (need_unreserve && i--) {
297 do {
298 value *v = n->src[i];
299 if (!v->is_readonly() && !v->is_undef()) {
300 if (i == 1 && opt)
301 continue;
302 unreserve(bs_cycle(trans, bs, i), n->bc.src[i].sel,
303 n->bc.src[i].chan);
304 }
305 } while (i--);
306 }
307 return false;
308 }
309
alu_group_tracker(shader & sh)310 alu_group_tracker::alu_group_tracker(shader &sh)
311 : sh(sh), kc(sh),
312 gpr(), lt(), slots(),
313 max_slots(sh.get_ctx().is_cayman() ? 4 : 5),
314 has_mova(), uses_ar(), has_predset(), has_kill(),
315 updates_exec_mask(), consumes_lds_oqa(), produces_lds_oqa(), chan_count(), interp_param(), next_id() {
316
317 available_slots = sh.get_ctx().has_trans ? 0x1F : 0x0F;
318 }
319
320 inline
get_value_id(value * v)321 sel_chan alu_group_tracker::get_value_id(value* v) {
322 unsigned &id = vmap[v];
323 if (!id)
324 id = ++next_id;
325 return sel_chan(id, v->get_final_chan());
326 }
327
328 inline
assign_slot(unsigned slot,alu_node * n)329 void alu_group_tracker::assign_slot(unsigned slot, alu_node* n) {
330 update_flags(n);
331 slots[slot] = n;
332 available_slots &= ~(1 << slot);
333
334 unsigned param = n->interp_param();
335
336 if (param) {
337 assert(!interp_param || interp_param == param);
338 interp_param = param;
339 }
340 }
341
342
discard_all_slots(container_node & removed_nodes)343 void alu_group_tracker::discard_all_slots(container_node &removed_nodes) {
344 PSC_DUMP( sblog << "agt::discard_all_slots\n"; );
345 discard_slots(~available_slots & ((1 << max_slots) - 1), removed_nodes);
346 }
347
discard_slots(unsigned slot_mask,container_node & removed_nodes)348 void alu_group_tracker::discard_slots(unsigned slot_mask,
349 container_node &removed_nodes) {
350
351 PSC_DUMP(
352 sblog << "discard_slots : packed_ops : "
353 << (unsigned)packed_ops.size() << "\n";
354 );
355
356 for (node_vec::iterator N, I = packed_ops.begin();
357 I != packed_ops.end(); I = N) {
358 N = I; ++N;
359
360 alu_packed_node *n = static_cast<alu_packed_node*>(*I);
361 unsigned pslots = n->get_slot_mask();
362
363 PSC_DUMP(
364 sblog << "discard_slots : packed slot_mask : " << pslots << "\n";
365 );
366
367 if (pslots & slot_mask) {
368
369 PSC_DUMP(
370 sblog << "discard_slots : discarding packed...\n";
371 );
372
373 removed_nodes.push_back(n);
374 slot_mask &= ~pslots;
375 N = packed_ops.erase(I);
376 available_slots |= pslots;
377 for (unsigned k = 0; k < max_slots; ++k) {
378 if (pslots & (1 << k))
379 slots[k] = NULL;
380 }
381 }
382 }
383
384 for (unsigned slot = 0; slot < max_slots; ++slot) {
385 unsigned slot_bit = 1 << slot;
386
387 if (slot_mask & slot_bit) {
388 assert(!(available_slots & slot_bit));
389 assert(slots[slot]);
390
391 assert(!(slots[slot]->bc.slot_flags & AF_4SLOT));
392
393 PSC_DUMP(
394 sblog << "discarding slot " << slot << " : ";
395 dump::dump_op(slots[slot]);
396 sblog << "\n";
397 );
398
399 removed_nodes.push_back(slots[slot]);
400 slots[slot] = NULL;
401 available_slots |= slot_bit;
402 }
403 }
404
405 alu_node *t = slots[4];
406 if (t && (t->bc.slot_flags & AF_V)) {
407 unsigned chan = t->bc.dst_chan;
408 if (!slots[chan]) {
409 PSC_DUMP(
410 sblog << "moving ";
411 dump::dump_op(t);
412 sblog << " from trans slot to free slot " << chan << "\n";
413 );
414
415 slots[chan] = t;
416 slots[4] = NULL;
417 t->bc.slot = chan;
418 }
419 }
420
421 reinit();
422 }
423
emit()424 alu_group_node* alu_group_tracker::emit() {
425
426 alu_group_node *g = sh.create_alu_group();
427
428 lt.init_group_literals(g);
429
430 for (unsigned i = 0; i < max_slots; ++i) {
431 alu_node *n = slots[i];
432 if (n) {
433 g->push_back(n);
434 }
435 }
436 return g;
437 }
438
try_reserve(alu_node * n)439 bool alu_group_tracker::try_reserve(alu_node* n) {
440 unsigned nsrc = n->bc.op_ptr->src_count;
441 unsigned slot = n->bc.slot;
442 bool trans = slot == 4;
443
444 if (slots[slot])
445 return false;
446
447 unsigned flags = n->bc.op_ptr->flags;
448
449 unsigned param = n->interp_param();
450
451 if (param && interp_param && interp_param != param)
452 return false;
453
454 if ((flags & AF_KILL) && has_predset)
455 return false;
456 if ((flags & AF_ANY_PRED) && (has_kill || has_predset))
457 return false;
458 if ((flags & AF_MOVA) && (has_mova || uses_ar))
459 return false;
460
461 if (n->uses_ar() && has_mova)
462 return false;
463
464 if (consumes_lds_oqa)
465 return false;
466 if (n->consumes_lds_oq() && available_slots != (sh.get_ctx().has_trans ? 0x1F : 0x0F))
467 return false;
468 for (unsigned i = 0; i < nsrc; ++i) {
469
470 unsigned last_id = next_id;
471
472 value *v = n->src[i];
473 if (!v->is_any_gpr() && !v->is_rel())
474 continue;
475 sel_chan vid = get_value_id(n->src[i]);
476
477 if (vid > last_id && chan_count[vid.chan()] == 3) {
478 return false;
479 }
480
481 n->bc.src[i].sel = vid.sel();
482 n->bc.src[i].chan = vid.chan();
483 }
484
485 if (!lt.try_reserve(n))
486 return false;
487
488 if (!kc.try_reserve(n)) {
489 lt.unreserve(n);
490 return false;
491 }
492
493 unsigned fbs = n->forced_bank_swizzle();
494
495 n->bc.bank_swizzle = 0;
496
497 if (!trans && fbs)
498 n->bc.bank_swizzle = VEC_210;
499
500 if (gpr.try_reserve(n)) {
501 assign_slot(slot, n);
502 return true;
503 }
504
505 if (!fbs) {
506 unsigned swz_num = trans ? SCL_NUM : VEC_NUM;
507 for (unsigned bs = 0; bs < swz_num; ++bs) {
508 n->bc.bank_swizzle = bs;
509 if (gpr.try_reserve(n)) {
510 assign_slot(slot, n);
511 return true;
512 }
513 }
514 }
515
516 gpr.reset();
517
518 slots[slot] = n;
519 unsigned forced_swz_slots = 0;
520 int first_slot = ~0, first_nf = ~0, last_slot = ~0;
521 unsigned save_bs[5];
522
523 for (unsigned i = 0; i < max_slots; ++i) {
524 alu_node *a = slots[i];
525 if (a) {
526 if (first_slot == ~0)
527 first_slot = i;
528 last_slot = i;
529 save_bs[i] = a->bc.bank_swizzle;
530 if (a->forced_bank_swizzle()) {
531 assert(i != SLOT_TRANS);
532 forced_swz_slots |= (1 << i);
533 a->bc.bank_swizzle = VEC_210;
534 if (!gpr.try_reserve(a))
535 assert(!"internal reservation error");
536 } else {
537 if (first_nf == ~0)
538 first_nf = i;
539
540 a->bc.bank_swizzle = 0;
541 }
542 }
543 }
544
545 if (first_nf == ~0) {
546 assign_slot(slot, n);
547 return true;
548 }
549
550 assert(first_slot != ~0 && last_slot != ~0);
551
552 // silence "array subscript is above array bounds" with gcc 4.8
553 if (last_slot >= 5)
554 abort();
555
556 int i = first_nf;
557 alu_node *a = slots[i];
558 bool backtrack = false;
559
560 while (1) {
561
562 PSC_DUMP(
563 sblog << " bs: trying s" << i << " bs:" << a->bc.bank_swizzle
564 << " bt:" << backtrack << "\n";
565 );
566
567 if (!backtrack && gpr.try_reserve(a)) {
568 PSC_DUMP(
569 sblog << " bs: reserved s" << i << " bs:" << a->bc.bank_swizzle
570 << "\n";
571 );
572
573 while ((++i <= last_slot) && !slots[i]);
574 if (i <= last_slot)
575 a = slots[i];
576 else
577 break;
578 } else {
579 bool itrans = i == SLOT_TRANS;
580 unsigned max_swz = itrans ? SCL_221 : VEC_210;
581
582 if (a->bc.bank_swizzle < max_swz) {
583 ++a->bc.bank_swizzle;
584
585 PSC_DUMP(
586 sblog << " bs: inc s" << i << " bs:" << a->bc.bank_swizzle
587 << "\n";
588 );
589
590 } else {
591
592 a->bc.bank_swizzle = 0;
593 while ((--i >= first_nf) && !slots[i]);
594 if (i < first_nf)
595 break;
596 a = slots[i];
597 PSC_DUMP(
598 sblog << " bs: unreserve s" << i << " bs:" << a->bc.bank_swizzle
599 << "\n";
600 );
601 gpr.unreserve(a);
602 backtrack = true;
603
604 continue;
605 }
606 }
607 backtrack = false;
608 }
609
610 if (i == last_slot + 1) {
611 assign_slot(slot, n);
612 return true;
613 }
614
615 // reservation failed, restore previous state
616 slots[slot] = NULL;
617 gpr.reset();
618 for (unsigned i = 0; i < max_slots; ++i) {
619 alu_node *a = slots[i];
620 if (a) {
621 a->bc.bank_swizzle = save_bs[i];
622 bool b = gpr.try_reserve(a);
623 assert(b);
624 }
625 }
626
627 kc.unreserve(n);
628 lt.unreserve(n);
629 return false;
630 }
631
try_reserve(alu_packed_node * p)632 bool alu_group_tracker::try_reserve(alu_packed_node* p) {
633 bool need_unreserve = false;
634 node_iterator I(p->begin()), E(p->end());
635
636 for (; I != E; ++I) {
637 alu_node *n = static_cast<alu_node*>(*I);
638 if (!try_reserve(n))
639 break;
640 else
641 need_unreserve = true;
642 }
643
644 if (I == E) {
645 packed_ops.push_back(p);
646 return true;
647 }
648
649 if (need_unreserve) {
650 while (--I != E) {
651 alu_node *n = static_cast<alu_node*>(*I);
652 slots[n->bc.slot] = NULL;
653 }
654 reinit();
655 }
656 return false;
657 }
658
reinit()659 void alu_group_tracker::reinit() {
660 alu_node * s[5];
661 memcpy(s, slots, sizeof(slots));
662
663 reset(true);
664
665 for (int i = max_slots - 1; i >= 0; --i) {
666 if (s[i] && !try_reserve(s[i])) {
667 sblog << "alu_group_tracker: reinit error on slot " << i << "\n";
668 for (unsigned i = 0; i < max_slots; ++i) {
669 sblog << " slot " << i << " : ";
670 if (s[i])
671 dump::dump_op(s[i]);
672
673 sblog << "\n";
674 }
675 assert(!"alu_group_tracker: reinit error");
676 }
677 }
678 }
679
reset(bool keep_packed)680 void alu_group_tracker::reset(bool keep_packed) {
681 kc.reset();
682 gpr.reset();
683 lt.reset();
684 memset(slots, 0, sizeof(slots));
685 vmap.clear();
686 next_id = 0;
687 produces_lds_oqa = 0;
688 consumes_lds_oqa = 0;
689 has_mova = false;
690 uses_ar = false;
691 has_predset = false;
692 has_kill = false;
693 updates_exec_mask = false;
694 available_slots = sh.get_ctx().has_trans ? 0x1F : 0x0F;
695 interp_param = 0;
696
697 chan_count[0] = 0;
698 chan_count[1] = 0;
699 chan_count[2] = 0;
700 chan_count[3] = 0;
701
702 if (!keep_packed)
703 packed_ops.clear();
704 }
705
update_flags(alu_node * n)706 void alu_group_tracker::update_flags(alu_node* n) {
707 unsigned flags = n->bc.op_ptr->flags;
708 has_kill |= (flags & AF_KILL);
709 has_mova |= (flags & AF_MOVA);
710 has_predset |= (flags & AF_ANY_PRED);
711 uses_ar |= n->uses_ar();
712 consumes_lds_oqa |= n->consumes_lds_oq();
713 produces_lds_oqa |= n->produces_lds_oq();
714 if (flags & AF_ANY_PRED) {
715 if (n->dst[2] != NULL)
716 updates_exec_mask = true;
717 }
718 }
719
run()720 int post_scheduler::run() {
721 return run_on(sh.root) ? 0 : 1;
722 }
723
run_on(container_node * n)724 bool post_scheduler::run_on(container_node* n) {
725 int r = true;
726 for (node_riterator I = n->rbegin(), E = n->rend(); I != E; ++I) {
727 if (I->is_container()) {
728 if (I->subtype == NST_BB) {
729 bb_node* bb = static_cast<bb_node*>(*I);
730 r = schedule_bb(bb);
731 } else {
732 r = run_on(static_cast<container_node*>(*I));
733 }
734 if (!r)
735 break;
736 }
737 }
738 return r;
739 }
740
init_uc_val(container_node * c,value * v)741 void post_scheduler::init_uc_val(container_node *c, value *v) {
742 node *d = v->any_def();
743 if (d && d->parent == c)
744 ++ucm[d];
745 }
746
init_uc_vec(container_node * c,vvec & vv,bool src)747 void post_scheduler::init_uc_vec(container_node *c, vvec &vv, bool src) {
748 for (vvec::iterator I = vv.begin(), E = vv.end(); I != E; ++I) {
749 value *v = *I;
750 if (!v || v->is_readonly())
751 continue;
752
753 if (v->is_rel()) {
754 init_uc_val(c, v->rel);
755 init_uc_vec(c, v->muse, true);
756 } if (src) {
757 init_uc_val(c, v);
758 }
759 }
760 }
761
init_ucm(container_node * c,node * n)762 unsigned post_scheduler::init_ucm(container_node *c, node *n) {
763 init_uc_vec(c, n->src, true);
764 init_uc_vec(c, n->dst, false);
765
766 uc_map::iterator F = ucm.find(n);
767 return F == ucm.end() ? 0 : F->second;
768 }
769
schedule_bb(bb_node * bb)770 bool post_scheduler::schedule_bb(bb_node* bb) {
771 PSC_DUMP(
772 sblog << "scheduling BB " << bb->id << "\n";
773 if (!pending.empty())
774 dump::dump_op_list(&pending);
775 );
776
777 assert(pending.empty());
778 assert(bb_pending.empty());
779 assert(ready.empty());
780
781 bb_pending.append_from(bb);
782 cur_bb = bb;
783
784 node *n;
785
786 while ((n = bb_pending.back())) {
787
788 PSC_DUMP(
789 sblog << "post_sched_bb ";
790 dump::dump_op(n);
791 sblog << "\n";
792 );
793
794 // May require emitting ALU ops to load index registers
795 if (n->is_fetch_clause()) {
796 n->remove();
797 process_fetch(static_cast<container_node *>(n));
798 continue;
799 }
800
801 if (n->is_alu_clause()) {
802 n->remove();
803 bool r = process_alu(static_cast<container_node*>(n));
804 if (r)
805 continue;
806 return false;
807 }
808
809 n->remove();
810 bb->push_front(n);
811 }
812
813 this->cur_bb = NULL;
814 return true;
815 }
816
init_regmap()817 void post_scheduler::init_regmap() {
818
819 regmap.clear();
820
821 PSC_DUMP(
822 sblog << "init_regmap: live: ";
823 dump::dump_set(sh, live);
824 sblog << "\n";
825 );
826
827 for (val_set::iterator I = live.begin(sh), E = live.end(sh); I != E; ++I) {
828 value *v = *I;
829 assert(v);
830 if (!v->is_sgpr() || !v->is_prealloc())
831 continue;
832
833 sel_chan r = v->gpr;
834
835 PSC_DUMP(
836 sblog << "init_regmap: " << r << " <= ";
837 dump::dump_val(v);
838 sblog << "\n";
839 );
840
841 assert(r);
842 regmap[r] = v;
843 }
844 }
845
create_set_idx(shader & sh,unsigned ar_idx)846 static alu_node *create_set_idx(shader &sh, unsigned ar_idx) {
847 alu_node *a = sh.create_alu();
848
849 assert(ar_idx == V_SQ_CF_INDEX_0 || ar_idx == V_SQ_CF_INDEX_1);
850 if (ar_idx == V_SQ_CF_INDEX_0)
851 a->bc.set_op(ALU_OP0_SET_CF_IDX0);
852 else
853 a->bc.set_op(ALU_OP0_SET_CF_IDX1);
854 a->bc.slot = SLOT_X;
855 a->dst.resize(1); // Dummy needed for recolor
856
857 PSC_DUMP(
858 sblog << "created IDX load: ";
859 dump::dump_op(a);
860 sblog << "\n";
861 );
862
863 return a;
864 }
865
load_index_register(value * v,unsigned ar_idx)866 void post_scheduler::load_index_register(value *v, unsigned ar_idx)
867 {
868 alu.reset();
869
870 if (!sh.get_ctx().is_cayman()) {
871 // Evergreen has to first load address register, then use CF_SET_IDX0/1
872 alu_group_tracker &rt = alu.grp();
873 alu_node *set_idx = create_set_idx(sh, ar_idx);
874 if (!rt.try_reserve(set_idx)) {
875 sblog << "can't emit SET_CF_IDX";
876 dump::dump_op(set_idx);
877 sblog << "\n";
878 }
879 process_group();
880
881 if (!alu.check_clause_limits()) {
882 // Can't happen since clause only contains MOVA/CF_SET_IDX0/1
883 }
884 alu.emit_group();
885 }
886
887 alu_group_tracker &rt = alu.grp();
888 alu_node *a = alu.create_ar_load(v, ar_idx == V_SQ_CF_INDEX_1 ? SEL_Z : SEL_Y);
889
890 if (!rt.try_reserve(a)) {
891 sblog << "can't emit AR load : ";
892 dump::dump_op(a);
893 sblog << "\n";
894 }
895
896 process_group();
897
898 if (!alu.check_clause_limits()) {
899 // Can't happen since clause only contains MOVA/CF_SET_IDX0/1
900 }
901
902 alu.emit_group();
903 alu.emit_clause(cur_bb);
904 }
905
process_fetch(container_node * c)906 void post_scheduler::process_fetch(container_node *c) {
907 if (c->empty())
908 return;
909
910 for (node_iterator N, I = c->begin(), E = c->end(); I != E; I = N) {
911 N = I;
912 ++N;
913
914 node *n = *I;
915
916 fetch_node *f = static_cast<fetch_node*>(n);
917
918 PSC_DUMP(
919 sblog << "process_tex ";
920 dump::dump_op(n);
921 sblog << " ";
922 );
923
924 // TODO: If same values used can avoid reloading index register
925 if (f->bc.sampler_index_mode != V_SQ_CF_INDEX_NONE ||
926 f->bc.resource_index_mode != V_SQ_CF_INDEX_NONE) {
927 unsigned index_mode = f->bc.sampler_index_mode != V_SQ_CF_INDEX_NONE ?
928 f->bc.sampler_index_mode : f->bc.resource_index_mode;
929
930 // Currently require prior opt passes to use one TEX per indexed op
931 assert(f->parent->count() == 1);
932
933 value *v = f->src.back(); // Last src is index offset
934 assert(v);
935
936 cur_bb->push_front(c);
937
938 load_index_register(v, index_mode);
939 f->src.pop_back(); // Don't need index value any more
940
941 return;
942 }
943 }
944
945 cur_bb->push_front(c);
946 }
947
process_alu(container_node * c)948 bool post_scheduler::process_alu(container_node *c) {
949
950 if (c->empty())
951 return true;
952
953 ucm.clear();
954 alu.reset();
955
956 live = c->live_after;
957
958 init_globals(c->live_after, true);
959 init_globals(c->live_before, true);
960
961 init_regmap();
962
963 update_local_interferences();
964
965 for (node_riterator N, I = c->rbegin(), E = c->rend(); I != E; I = N) {
966 N = I;
967 ++N;
968
969 node *n = *I;
970 unsigned uc = init_ucm(c, n);
971
972 PSC_DUMP(
973 sblog << "process_alu uc=" << uc << " ";
974 dump::dump_op(n);
975 sblog << " ";
976 );
977
978 if (uc) {
979 n->remove();
980
981 pending.push_back(n);
982 PSC_DUMP( sblog << "pending\n"; );
983 } else {
984 release_op(n);
985 }
986 }
987
988 return schedule_alu(c);
989 }
990
update_local_interferences()991 void post_scheduler::update_local_interferences() {
992
993 PSC_DUMP(
994 sblog << "update_local_interferences : ";
995 dump::dump_set(sh, live);
996 sblog << "\n";
997 );
998
999
1000 for (val_set::iterator I = live.begin(sh), E = live.end(sh); I != E; ++I) {
1001 value *v = *I;
1002 if (v->is_prealloc())
1003 continue;
1004
1005 v->interferences.add_set(live);
1006 }
1007 }
1008
update_live_src_vec(vvec & vv,val_set * born,bool src)1009 void post_scheduler::update_live_src_vec(vvec &vv, val_set *born, bool src) {
1010 for (vvec::iterator I = vv.begin(), E = vv.end(); I != E; ++I) {
1011 value *v = *I;
1012
1013 if (!v)
1014 continue;
1015
1016 if (src && v->is_any_gpr()) {
1017 if (live.add_val(v)) {
1018 if (!v->is_prealloc()) {
1019 if (!cleared_interf.contains(v)) {
1020 PSC_DUMP(
1021 sblog << "clearing interferences for " << *v << "\n";
1022 );
1023 v->interferences.clear();
1024 cleared_interf.add_val(v);
1025 }
1026 }
1027 if (born)
1028 born->add_val(v);
1029 }
1030 } else if (v->is_rel()) {
1031 if (!v->rel->is_any_gpr())
1032 live.add_val(v->rel);
1033 update_live_src_vec(v->muse, born, true);
1034 }
1035 }
1036 }
1037
update_live_dst_vec(vvec & vv)1038 void post_scheduler::update_live_dst_vec(vvec &vv) {
1039 for (vvec::iterator I = vv.begin(), E = vv.end(); I != E; ++I) {
1040 value *v = *I;
1041 if (!v)
1042 continue;
1043
1044 if (v->is_rel()) {
1045 update_live_dst_vec(v->mdef);
1046 } else if (v->is_any_gpr()) {
1047 if (!live.remove_val(v)) {
1048 PSC_DUMP(
1049 sblog << "failed to remove ";
1050 dump::dump_val(v);
1051 sblog << " from live : ";
1052 dump::dump_set(sh, live);
1053 sblog << "\n";
1054 );
1055 }
1056 }
1057 }
1058 }
1059
update_live(node * n,val_set * born)1060 void post_scheduler::update_live(node *n, val_set *born) {
1061 update_live_dst_vec(n->dst);
1062 update_live_src_vec(n->src, born, true);
1063 update_live_src_vec(n->dst, born, false);
1064 }
1065
process_group()1066 void post_scheduler::process_group() {
1067 alu_group_tracker &rt = alu.grp();
1068
1069 val_set vals_born;
1070
1071 recolor_locals();
1072
1073 PSC_DUMP(
1074 sblog << "process_group: live_before : ";
1075 dump::dump_set(sh, live);
1076 sblog << "\n";
1077 );
1078
1079 for (unsigned s = 0; s < ctx.num_slots; ++s) {
1080 alu_node *n = rt.slot(s);
1081 if (!n)
1082 continue;
1083
1084 update_live(n, &vals_born);
1085 }
1086
1087 PSC_DUMP(
1088 sblog << "process_group: live_after : ";
1089 dump::dump_set(sh, live);
1090 sblog << "\n";
1091 );
1092
1093 update_local_interferences();
1094
1095 for (unsigned i = 0; i < 5; ++i) {
1096 node *n = rt.slot(i);
1097 if (n && !n->is_mova()) {
1098 release_src_values(n);
1099 }
1100 }
1101 }
1102
init_globals(val_set & s,bool prealloc)1103 void post_scheduler::init_globals(val_set &s, bool prealloc) {
1104
1105 PSC_DUMP(
1106 sblog << "init_globals: ";
1107 dump::dump_set(sh, s);
1108 sblog << "\n";
1109 );
1110
1111 for (val_set::iterator I = s.begin(sh), E = s.end(sh); I != E; ++I) {
1112 value *v = *I;
1113 if (v->is_sgpr() && !v->is_global()) {
1114 v->set_global();
1115
1116 if (prealloc && v->is_fixed()) {
1117 v->set_prealloc();
1118 }
1119 }
1120 }
1121 }
1122
emit_index_registers()1123 void post_scheduler::emit_index_registers() {
1124 for (unsigned i = 0; i < 2; i++) {
1125 if (alu.current_idx[i]) {
1126 regmap = prev_regmap;
1127 alu.discard_current_group();
1128
1129 load_index_register(alu.current_idx[i], KC_INDEX_0 + i);
1130 alu.current_idx[i] = NULL;
1131 }
1132 }
1133 }
1134
emit_clause()1135 void post_scheduler::emit_clause() {
1136
1137 if (alu.current_ar) {
1138 emit_load_ar();
1139 process_group();
1140 if (!alu.check_clause_limits()) {
1141 // Can't happen since clause only contains MOVA/CF_SET_IDX0/1
1142 }
1143 alu.emit_group();
1144 }
1145
1146 if (!alu.is_empty()) {
1147 alu.emit_clause(cur_bb);
1148 }
1149
1150 emit_index_registers();
1151 }
1152
schedule_alu(container_node * c)1153 bool post_scheduler::schedule_alu(container_node *c) {
1154
1155 assert(!ready.empty() || !ready_copies.empty());
1156
1157 bool improving = true;
1158 int last_pending = pending.count();
1159 while (improving) {
1160 prev_regmap = regmap;
1161 if (!prepare_alu_group()) {
1162
1163 int new_pending = pending.count();
1164 improving = (new_pending < last_pending) || (last_pending == 0);
1165 last_pending = new_pending;
1166
1167 if (alu.current_idx[0] || alu.current_idx[1]) {
1168 regmap = prev_regmap;
1169 emit_clause();
1170 init_globals(live, false);
1171
1172 continue;
1173 }
1174
1175 if (alu.current_ar) {
1176 emit_load_ar();
1177 continue;
1178 } else
1179 break;
1180 }
1181
1182 if (!alu.check_clause_limits()) {
1183 regmap = prev_regmap;
1184 emit_clause();
1185 init_globals(live, false);
1186
1187 continue;
1188 }
1189
1190 process_group();
1191 alu.emit_group();
1192 };
1193
1194 if (!alu.is_empty()) {
1195 emit_clause();
1196 }
1197
1198 if (!ready.empty()) {
1199 sblog << "##post_scheduler: unscheduled ready instructions :";
1200 dump::dump_op_list(&ready);
1201 assert(!"unscheduled ready instructions");
1202 }
1203
1204 if (!pending.empty()) {
1205 sblog << "##post_scheduler: unscheduled pending instructions :";
1206 dump::dump_op_list(&pending);
1207 assert(!"unscheduled pending instructions");
1208 }
1209 return improving;
1210 }
1211
add_interferences(value * v,sb_bitset & rb,val_set & vs)1212 void post_scheduler::add_interferences(value *v, sb_bitset &rb, val_set &vs) {
1213 unsigned chan = v->gpr.chan();
1214
1215 for (val_set::iterator I = vs.begin(sh), E = vs.end(sh);
1216 I != E; ++I) {
1217 value *vi = *I;
1218 sel_chan gpr = vi->get_final_gpr();
1219
1220 if (vi->is_any_gpr() && gpr && vi != v &&
1221 (!v->chunk || v->chunk != vi->chunk) &&
1222 vi->is_fixed() && gpr.chan() == chan) {
1223
1224 unsigned r = gpr.sel();
1225
1226 PSC_DUMP(
1227 sblog << "\tadd_interferences: " << *vi << "\n";
1228 );
1229
1230 if (rb.size() <= r)
1231 rb.resize(r + 32);
1232 rb.set(r);
1233 }
1234 }
1235 }
1236
set_color_local_val(value * v,sel_chan color)1237 void post_scheduler::set_color_local_val(value *v, sel_chan color) {
1238 v->gpr = color;
1239
1240 PSC_DUMP(
1241 sblog << " recolored: ";
1242 dump::dump_val(v);
1243 sblog << "\n";
1244 );
1245 }
1246
set_color_local(value * v,sel_chan color)1247 void post_scheduler::set_color_local(value *v, sel_chan color) {
1248 if (v->chunk) {
1249 vvec &vv = v->chunk->values;
1250 for (vvec::iterator I = vv.begin(), E = vv.end(); I != E; ++I) {
1251 value *v2 =*I;
1252 set_color_local_val(v2, color);
1253 }
1254 v->chunk->fix();
1255 } else {
1256 set_color_local_val(v, color);
1257 v->fix();
1258 }
1259 }
1260
recolor_local(value * v)1261 bool post_scheduler::recolor_local(value *v) {
1262
1263 sb_bitset rb;
1264
1265 assert(v->is_sgpr());
1266 assert(!v->is_prealloc());
1267 assert(v->gpr);
1268
1269 unsigned chan = v->gpr.chan();
1270
1271 PSC_DUMP(
1272 sblog << "recolor_local: ";
1273 dump::dump_val(v);
1274 sblog << " interferences: ";
1275 dump::dump_set(sh, v->interferences);
1276 sblog << "\n";
1277 if (v->chunk) {
1278 sblog << " in chunk: ";
1279 coalescer::dump_chunk(v->chunk);
1280 sblog << "\n";
1281 }
1282 );
1283
1284 if (v->chunk) {
1285 for (vvec::iterator I = v->chunk->values.begin(),
1286 E = v->chunk->values.end(); I != E; ++I) {
1287 value *v2 = *I;
1288
1289 PSC_DUMP( sblog << " add_interferences for " << *v2 << " :\n"; );
1290
1291 add_interferences(v, rb, v2->interferences);
1292 }
1293 } else {
1294 add_interferences(v, rb, v->interferences);
1295 }
1296
1297 PSC_DUMP(
1298 unsigned sz = rb.size();
1299 sblog << "registers bits: " << sz;
1300 for (unsigned r = 0; r < sz; ++r) {
1301 if ((r & 7) == 0)
1302 sblog << "\n " << r << " ";
1303 sblog << (rb.get(r) ? 1 : 0);
1304 }
1305 );
1306
1307 bool no_temp_gprs = v->is_global();
1308 unsigned rs, re, pass = no_temp_gprs ? 1 : 0;
1309
1310 while (pass < 2) {
1311
1312 if (pass == 0) {
1313 rs = sh.first_temp_gpr();
1314 re = MAX_GPR;
1315 } else {
1316 rs = 0;
1317 re = sh.num_nontemp_gpr();
1318 }
1319
1320 for (unsigned reg = rs; reg < re; ++reg) {
1321 if (reg >= rb.size() || !rb.get(reg)) {
1322 // color found
1323 set_color_local(v, sel_chan(reg, chan));
1324 return true;
1325 }
1326 }
1327 ++pass;
1328 }
1329
1330 assert(!"recolor_local failed");
1331 return true;
1332 }
1333
emit_load_ar()1334 void post_scheduler::emit_load_ar() {
1335
1336 regmap = prev_regmap;
1337 alu.discard_current_group();
1338
1339 alu_group_tracker &rt = alu.grp();
1340 alu_node *a = alu.create_ar_load(alu.current_ar, SEL_X);
1341
1342 if (!rt.try_reserve(a)) {
1343 sblog << "can't emit AR load : ";
1344 dump::dump_op(a);
1345 sblog << "\n";
1346 }
1347
1348 alu.current_ar = 0;
1349 }
1350
unmap_dst_val(value * d)1351 bool post_scheduler::unmap_dst_val(value *d) {
1352
1353 if (d == alu.current_ar) {
1354 emit_load_ar();
1355 return false;
1356 }
1357
1358 if (d->is_prealloc()) {
1359 sel_chan gpr = d->get_final_gpr();
1360 rv_map::iterator F = regmap.find(gpr);
1361 value *c = NULL;
1362 if (F != regmap.end())
1363 c = F->second;
1364
1365 if (c && c!=d && (!c->chunk || c->chunk != d->chunk)) {
1366 PSC_DUMP(
1367 sblog << "dst value conflict : ";
1368 dump::dump_val(d);
1369 sblog << " regmap contains ";
1370 dump::dump_val(c);
1371 sblog << "\n";
1372 );
1373 assert(!"scheduler error");
1374 return false;
1375 } else if (c) {
1376 regmap.erase(F);
1377 }
1378 }
1379 return true;
1380 }
1381
unmap_dst(alu_node * n)1382 bool post_scheduler::unmap_dst(alu_node *n) {
1383 value *d = n->dst.empty() ? NULL : n->dst[0];
1384
1385 if (!d)
1386 return true;
1387
1388 if (!d->is_rel()) {
1389 if (d && d->is_any_reg()) {
1390
1391 if (d->is_AR()) {
1392 if (alu.current_ar != d) {
1393 sblog << "loading wrong ar value\n";
1394 assert(0);
1395 } else {
1396 alu.current_ar = NULL;
1397 }
1398
1399 } else if (d->is_any_gpr()) {
1400 if (!unmap_dst_val(d))
1401 return false;
1402 }
1403 }
1404 } else {
1405 for (vvec::iterator I = d->mdef.begin(), E = d->mdef.end();
1406 I != E; ++I) {
1407 d = *I;
1408 if (!d)
1409 continue;
1410
1411 assert(d->is_any_gpr());
1412
1413 if (!unmap_dst_val(d))
1414 return false;
1415 }
1416 }
1417 return true;
1418 }
1419
map_src_val(value * v)1420 bool post_scheduler::map_src_val(value *v) {
1421
1422 if (!v->is_prealloc())
1423 return true;
1424
1425 sel_chan gpr = v->get_final_gpr();
1426 rv_map::iterator F = regmap.find(gpr);
1427 value *c = NULL;
1428 if (F != regmap.end()) {
1429 c = F->second;
1430 if (!v->v_equal(c)) {
1431 PSC_DUMP(
1432 sblog << "can't map src value ";
1433 dump::dump_val(v);
1434 sblog << ", regmap contains ";
1435 dump::dump_val(c);
1436 sblog << "\n";
1437 );
1438 return false;
1439 }
1440 } else {
1441 regmap.insert(std::make_pair(gpr, v));
1442 }
1443 return true;
1444 }
1445
map_src_vec(vvec & vv,bool src)1446 bool post_scheduler::map_src_vec(vvec &vv, bool src) {
1447 if (src) {
1448 // Handle possible UBO indexing
1449 bool ubo_indexing[2] = { false, false };
1450 for (vvec::iterator I = vv.begin(), E = vv.end(); I != E; ++I) {
1451 value *v = *I;
1452 if (!v)
1453 continue;
1454
1455 if (v->is_kcache()) {
1456 unsigned index_mode = v->select.kcache_index_mode();
1457 if (index_mode == KC_INDEX_0 || index_mode == KC_INDEX_1) {
1458 ubo_indexing[index_mode - KC_INDEX_0] = true;
1459 }
1460 }
1461 }
1462
1463 // idx values stored at end of src vec, see bc_parser::prepare_alu_group
1464 for (unsigned i = 2; i != 0; i--) {
1465 if (ubo_indexing[i-1]) {
1466 // TODO: skip adding value to kcache reservation somehow, causes
1467 // unnecessary group breaks and cache line locks
1468 value *v = vv.back();
1469 if (alu.current_idx[i-1] && alu.current_idx[i-1] != v) {
1470 PSC_DUMP(
1471 sblog << "IDX" << i-1 << " already set to " <<
1472 *alu.current_idx[i-1] << ", trying to set " << *v << "\n";
1473 );
1474 return false;
1475 }
1476
1477 alu.current_idx[i-1] = v;
1478 PSC_DUMP(sblog << "IDX" << i-1 << " set to " << *v << "\n";);
1479 }
1480 }
1481 }
1482
1483 for (vvec::iterator I = vv.begin(), E = vv.end(); I != E; ++I) {
1484 value *v = *I;
1485 if (!v)
1486 continue;
1487
1488 if ((!v->is_any_gpr() || !v->is_fixed()) && !v->is_rel())
1489 continue;
1490
1491 if (v->is_rel()) {
1492 value *rel = v->rel;
1493 assert(rel);
1494
1495 if (!rel->is_const()) {
1496 if (!map_src_vec(v->muse, true))
1497 return false;
1498
1499 if (rel != alu.current_ar) {
1500 if (alu.current_ar) {
1501 PSC_DUMP(
1502 sblog << " current_AR is " << *alu.current_ar
1503 << " trying to use " << *rel << "\n";
1504 );
1505 return false;
1506 }
1507
1508 alu.current_ar = rel;
1509
1510 PSC_DUMP(
1511 sblog << " new current_AR assigned: " << *alu.current_ar
1512 << "\n";
1513 );
1514 }
1515 }
1516
1517 } else if (src) {
1518 if (!map_src_val(v)) {
1519 return false;
1520 }
1521 }
1522 }
1523 return true;
1524 }
1525
map_src(alu_node * n)1526 bool post_scheduler::map_src(alu_node *n) {
1527 if (!map_src_vec(n->dst, false))
1528 return false;
1529
1530 if (!map_src_vec(n->src, true))
1531 return false;
1532
1533 return true;
1534 }
1535
dump_regmap()1536 void post_scheduler::dump_regmap() {
1537
1538 sblog << "# REGMAP :\n";
1539
1540 for(rv_map::iterator I = regmap.begin(), E = regmap.end(); I != E; ++I) {
1541 sblog << " # " << I->first << " => " << *(I->second) << "\n";
1542 }
1543
1544 if (alu.current_ar)
1545 sblog << " current_AR: " << *alu.current_ar << "\n";
1546 if (alu.current_pr)
1547 sblog << " current_PR: " << *alu.current_pr << "\n";
1548 if (alu.current_idx[0])
1549 sblog << " current IDX0: " << *alu.current_idx[0] << "\n";
1550 if (alu.current_idx[1])
1551 sblog << " current IDX1: " << *alu.current_idx[1] << "\n";
1552 }
1553
recolor_locals()1554 void post_scheduler::recolor_locals() {
1555 alu_group_tracker &rt = alu.grp();
1556
1557 for (unsigned s = 0; s < ctx.num_slots; ++s) {
1558 alu_node *n = rt.slot(s);
1559 if (n) {
1560 value *d = n->dst[0];
1561 if (d && d->is_sgpr() && !d->is_prealloc()) {
1562 recolor_local(d);
1563 }
1564 }
1565 }
1566 }
1567
1568 // returns true if there are interferences
check_interferences()1569 bool post_scheduler::check_interferences() {
1570
1571 alu_group_tracker &rt = alu.grp();
1572
1573 unsigned interf_slots;
1574
1575 bool discarded = false;
1576
1577 PSC_DUMP(
1578 sblog << "check_interferences: before: \n";
1579 dump_regmap();
1580 );
1581
1582 do {
1583
1584 interf_slots = 0;
1585
1586 for (unsigned s = 0; s < ctx.num_slots; ++s) {
1587 alu_node *n = rt.slot(s);
1588 if (n) {
1589 if (!unmap_dst(n)) {
1590 return true;
1591 }
1592 }
1593 }
1594
1595 for (unsigned s = 0; s < ctx.num_slots; ++s) {
1596 alu_node *n = rt.slot(s);
1597 if (n) {
1598 if (!map_src(n)) {
1599 interf_slots |= (1 << s);
1600 }
1601 }
1602 }
1603
1604 PSC_DUMP(
1605 for (unsigned i = 0; i < 5; ++i) {
1606 if (interf_slots & (1 << i)) {
1607 sblog << "!!!!!! interf slot: " << i << " : ";
1608 dump::dump_op(rt.slot(i));
1609 sblog << "\n";
1610 }
1611 }
1612 );
1613
1614 if (!interf_slots)
1615 break;
1616
1617 PSC_DUMP( sblog << "ci: discarding slots " << interf_slots << "\n"; );
1618
1619 rt.discard_slots(interf_slots, alu.conflict_nodes);
1620 regmap = prev_regmap;
1621 discarded = true;
1622
1623 } while(1);
1624
1625 PSC_DUMP(
1626 sblog << "check_interferences: after: \n";
1627 dump_regmap();
1628 );
1629
1630 return discarded;
1631 }
1632
1633 // add instruction(s) (alu_node or contents of alu_packed_node) to current group
1634 // returns the number of added instructions on success
try_add_instruction(node * n)1635 unsigned post_scheduler::try_add_instruction(node *n) {
1636
1637 alu_group_tracker &rt = alu.grp();
1638
1639 unsigned avail_slots = rt.avail_slots();
1640
1641 // Cannot schedule in same clause as instructions using this index value
1642 if (!n->dst.empty() && n->dst[0] &&
1643 (n->dst[0] == alu.current_idx[0] || n->dst[0] == alu.current_idx[1])) {
1644 PSC_DUMP(sblog << " CF_IDX source: " << *n->dst[0] << "\n";);
1645 return 0;
1646 }
1647
1648 if (n->is_alu_packed()) {
1649 alu_packed_node *p = static_cast<alu_packed_node*>(n);
1650 unsigned slots = p->get_slot_mask();
1651 unsigned cnt = __builtin_popcount(slots);
1652
1653 if ((slots & avail_slots) != slots) {
1654 PSC_DUMP( sblog << " no slots \n"; );
1655 return 0;
1656 }
1657
1658 p->update_packed_items(ctx);
1659
1660 if (!rt.try_reserve(p)) {
1661 PSC_DUMP( sblog << " reservation failed \n"; );
1662 return 0;
1663 }
1664
1665 p->remove();
1666 return cnt;
1667
1668 } else {
1669 alu_node *a = static_cast<alu_node*>(n);
1670 value *d = a->dst.empty() ? NULL : a->dst[0];
1671
1672 if (d && d->is_special_reg()) {
1673 assert((a->bc.op_ptr->flags & AF_MOVA) || d->is_geometry_emit() || d->is_lds_oq() || d->is_lds_access());
1674 d = NULL;
1675 }
1676
1677 unsigned allowed_slots = ctx.alu_slots_mask(a->bc.op_ptr);
1678 unsigned slot;
1679
1680 allowed_slots &= avail_slots;
1681
1682 if (!allowed_slots)
1683 return 0;
1684
1685 if (d) {
1686 slot = d->get_final_chan();
1687 a->bc.dst_chan = slot;
1688 allowed_slots &= (1 << slot) | 0x10;
1689 } else {
1690 if (a->bc.op_ptr->flags & AF_MOVA) {
1691 if (a->bc.slot_flags & AF_V)
1692 allowed_slots &= (1 << SLOT_X);
1693 else
1694 allowed_slots &= (1 << SLOT_TRANS);
1695 }
1696 }
1697
1698 // FIXME workaround for some problems with MULADD in trans slot on r700,
1699 // (is it really needed on r600?)
1700 if ((a->bc.op == ALU_OP3_MULADD || a->bc.op == ALU_OP3_MULADD_IEEE) &&
1701 !ctx.is_egcm()) {
1702 allowed_slots &= 0x0F;
1703 }
1704
1705 if (!allowed_slots) {
1706 PSC_DUMP( sblog << " no suitable slots\n"; );
1707 return 0;
1708 }
1709
1710 slot = __builtin_ctz(allowed_slots);
1711 a->bc.slot = slot;
1712
1713 PSC_DUMP( sblog << "slot: " << slot << "\n"; );
1714
1715 if (!rt.try_reserve(a)) {
1716 PSC_DUMP( sblog << " reservation failed\n"; );
1717 return 0;
1718 }
1719
1720 a->remove();
1721 return 1;
1722 }
1723 }
1724
check_copy(node * n)1725 bool post_scheduler::check_copy(node *n) {
1726 if (!n->is_copy_mov())
1727 return false;
1728
1729 value *s = n->src[0];
1730 value *d = n->dst[0];
1731
1732 if (!s->is_sgpr() || !d->is_sgpr())
1733 return false;
1734
1735 if (!s->is_prealloc()) {
1736 recolor_local(s);
1737
1738 if (!s->chunk || s->chunk != d->chunk)
1739 return false;
1740 }
1741
1742 if (s->gpr == d->gpr) {
1743
1744 PSC_DUMP(
1745 sblog << "check_copy: ";
1746 dump::dump_op(n);
1747 sblog << "\n";
1748 );
1749
1750 rv_map::iterator F = regmap.find(d->gpr);
1751 bool gpr_free = (F == regmap.end());
1752
1753 if (d->is_prealloc()) {
1754 if (gpr_free) {
1755 PSC_DUMP( sblog << " copy not ready...\n";);
1756 return true;
1757 }
1758
1759 value *rv = F->second;
1760 if (rv != d && (!rv->chunk || rv->chunk != d->chunk)) {
1761 PSC_DUMP( sblog << " copy not ready(2)...\n";);
1762 return true;
1763 }
1764
1765 unmap_dst(static_cast<alu_node*>(n));
1766 }
1767
1768 if (s->is_prealloc() && !map_src_val(s))
1769 return true;
1770
1771 update_live(n, NULL);
1772
1773 release_src_values(n);
1774 n->remove();
1775 PSC_DUMP( sblog << " copy coalesced...\n";);
1776 return true;
1777 }
1778 return false;
1779 }
1780
dump_group(alu_group_tracker & rt)1781 void post_scheduler::dump_group(alu_group_tracker &rt) {
1782 for (unsigned i = 0; i < 5; ++i) {
1783 node *n = rt.slot(i);
1784 if (n) {
1785 sblog << "slot " << i << " : ";
1786 dump::dump_op(n);
1787 sblog << "\n";
1788 }
1789 }
1790 }
1791
process_ready_copies()1792 void post_scheduler::process_ready_copies() {
1793
1794 node *last;
1795
1796 do {
1797 last = ready_copies.back();
1798
1799 for (node_iterator N, I = ready_copies.begin(), E = ready_copies.end();
1800 I != E; I = N) {
1801 N = I; ++N;
1802
1803 node *n = *I;
1804
1805 if (!check_copy(n)) {
1806 n->remove();
1807 ready.push_back(n);
1808 }
1809 }
1810 } while (last != ready_copies.back());
1811
1812 update_local_interferences();
1813 }
1814
1815
prepare_alu_group()1816 bool post_scheduler::prepare_alu_group() {
1817
1818 alu_group_tracker &rt = alu.grp();
1819
1820 unsigned i1 = 0;
1821
1822 PSC_DUMP(
1823 sblog << "prepare_alu_group: starting...\n";
1824 dump_group(rt);
1825 );
1826
1827 ready.append_from(&alu.conflict_nodes);
1828
1829 // FIXME rework this loop
1830
1831 do {
1832
1833 process_ready_copies();
1834
1835 ++i1;
1836
1837 for (node_iterator N, I = ready.begin(), E = ready.end(); I != E;
1838 I = N) {
1839 N = I; ++N;
1840 node *n = *I;
1841
1842 PSC_DUMP(
1843 sblog << "p_a_g: ";
1844 dump::dump_op(n);
1845 sblog << "\n";
1846 );
1847
1848
1849 unsigned cnt = try_add_instruction(n);
1850
1851 if (!cnt)
1852 continue;
1853
1854 PSC_DUMP(
1855 sblog << "current group:\n";
1856 dump_group(rt);
1857 );
1858
1859 if (rt.inst_count() == ctx.num_slots) {
1860 PSC_DUMP( sblog << " all slots used\n"; );
1861 break;
1862 }
1863 }
1864
1865 if (!check_interferences())
1866 break;
1867
1868 // don't try to add more instructions to the group with mova if this
1869 // can lead to breaking clause slot count limit - we don't want mova to
1870 // end up in the end of the new clause instead of beginning of the
1871 // current clause.
1872 if (rt.has_ar_load() && alu.total_slots() > 121)
1873 break;
1874
1875 if (rt.inst_count() && i1 > 50)
1876 break;
1877
1878 regmap = prev_regmap;
1879
1880 } while (1);
1881
1882 PSC_DUMP(
1883 sblog << " prepare_alu_group done, " << rt.inst_count()
1884 << " slot(s) \n";
1885
1886 sblog << "$$$$$$$$PAG i1=" << i1
1887 << " ready " << ready.count()
1888 << " pending " << pending.count()
1889 << " conflicting " << alu.conflict_nodes.count()
1890 <<"\n";
1891
1892 );
1893
1894 return rt.inst_count();
1895 }
1896
release_src_values(node * n)1897 void post_scheduler::release_src_values(node* n) {
1898 release_src_vec(n->src, true);
1899 release_src_vec(n->dst, false);
1900 }
1901
release_op(node * n)1902 void post_scheduler::release_op(node *n) {
1903 PSC_DUMP(
1904 sblog << "release_op ";
1905 dump::dump_op(n);
1906 sblog << "\n";
1907 );
1908
1909 n->remove();
1910
1911 if (n->is_copy_mov()) {
1912 ready_copies.push_back(n);
1913 } else if (n->is_mova() || n->is_pred_set()) {
1914 ready.push_front(n);
1915 } else {
1916 ready.push_back(n);
1917 }
1918 }
1919
release_src_val(value * v)1920 void post_scheduler::release_src_val(value *v) {
1921 node *d = v->any_def();
1922 if (d) {
1923 if (!--ucm[d])
1924 release_op(d);
1925 }
1926 }
1927
release_src_vec(vvec & vv,bool src)1928 void post_scheduler::release_src_vec(vvec& vv, bool src) {
1929
1930 for (vvec::iterator I = vv.begin(), E = vv.end(); I != E; ++I) {
1931 value *v = *I;
1932 if (!v || v->is_readonly())
1933 continue;
1934
1935 if (v->is_rel()) {
1936 release_src_val(v->rel);
1937 release_src_vec(v->muse, true);
1938
1939 } else if (src) {
1940 release_src_val(v);
1941 }
1942 }
1943 }
1944
reset()1945 void literal_tracker::reset() {
1946 memset(lt, 0, sizeof(lt));
1947 memset(uc, 0, sizeof(uc));
1948 }
1949
reset()1950 void rp_gpr_tracker::reset() {
1951 memset(rp, 0, sizeof(rp));
1952 memset(uc, 0, sizeof(uc));
1953 }
1954
reset()1955 void rp_kcache_tracker::reset() {
1956 memset(rp, 0, sizeof(rp));
1957 memset(uc, 0, sizeof(uc));
1958 }
1959
reset()1960 void alu_kcache_tracker::reset() {
1961 memset(kc, 0, sizeof(kc));
1962 lines.clear();
1963 }
1964
reset()1965 void alu_clause_tracker::reset() {
1966 group = 0;
1967 slot_count = 0;
1968 outstanding_lds_oqa_reads = 0;
1969 grp0.reset();
1970 grp1.reset();
1971 }
1972
alu_clause_tracker(shader & sh)1973 alu_clause_tracker::alu_clause_tracker(shader &sh)
1974 : sh(sh), kt(sh.get_ctx().hw_class), slot_count(),
1975 grp0(sh), grp1(sh),
1976 group(), clause(),
1977 push_exec_mask(), outstanding_lds_oqa_reads(),
1978 current_ar(), current_pr(), current_idx() {}
1979
emit_group()1980 void alu_clause_tracker::emit_group() {
1981
1982 assert(grp().inst_count());
1983
1984 alu_group_node *g = grp().emit();
1985
1986 if (grp().has_update_exec_mask()) {
1987 assert(!push_exec_mask);
1988 push_exec_mask = true;
1989 }
1990
1991 assert(g);
1992
1993 if (!clause) {
1994 clause = sh.create_clause(NST_ALU_CLAUSE);
1995 }
1996
1997 clause->push_front(g);
1998
1999 outstanding_lds_oqa_reads += grp().get_consumes_lds_oqa();
2000 outstanding_lds_oqa_reads -= grp().get_produces_lds_oqa();
2001 slot_count += grp().slot_count();
2002
2003 new_group();
2004
2005 PSC_DUMP( sblog << " #### group emitted\n"; );
2006 }
2007
emit_clause(container_node * c)2008 void alu_clause_tracker::emit_clause(container_node *c) {
2009 assert(clause);
2010
2011 kt.init_clause(clause->bc);
2012
2013 assert(!outstanding_lds_oqa_reads);
2014 assert(!current_ar);
2015 assert(!current_pr);
2016
2017 if (push_exec_mask)
2018 clause->bc.set_op(CF_OP_ALU_PUSH_BEFORE);
2019
2020 c->push_front(clause);
2021
2022 clause = NULL;
2023 push_exec_mask = false;
2024 slot_count = 0;
2025 kt.reset();
2026
2027 PSC_DUMP( sblog << "######### ALU clause emitted\n"; );
2028 }
2029
check_clause_limits()2030 bool alu_clause_tracker::check_clause_limits() {
2031
2032 alu_group_tracker > = grp();
2033
2034 unsigned slots = gt.slot_count();
2035
2036 // reserving slots to load AR and PR values
2037 unsigned reserve_slots = (current_ar ? 1 : 0) + (current_pr ? 1 : 0);
2038 // ...and index registers
2039 reserve_slots += (current_idx[0] != NULL) + (current_idx[1] != NULL);
2040
2041 if (gt.get_consumes_lds_oqa() && !outstanding_lds_oqa_reads)
2042 reserve_slots += 60;
2043
2044 if (slot_count + slots > MAX_ALU_SLOTS - reserve_slots)
2045 return false;
2046
2047 if (!kt.try_reserve(gt))
2048 return false;
2049
2050 return true;
2051 }
2052
new_group()2053 void alu_clause_tracker::new_group() {
2054 group = !group;
2055 grp().reset();
2056 }
2057
is_empty()2058 bool alu_clause_tracker::is_empty() {
2059 return clause == NULL;
2060 }
2061
init_group_literals(alu_group_node * g)2062 void literal_tracker::init_group_literals(alu_group_node* g) {
2063
2064 g->literals.clear();
2065 for (unsigned i = 0; i < 4; ++i) {
2066 if (!lt[i])
2067 break;
2068
2069 g->literals.push_back(lt[i]);
2070
2071 PSC_DUMP(
2072 sblog << "literal emitted: " << lt[i].f;
2073 sblog.print_zw_hex(lt[i].u, 8);
2074 sblog << " " << lt[i].i << "\n";
2075 );
2076 }
2077 }
2078
try_reserve(alu_group_tracker & gt)2079 bool alu_kcache_tracker::try_reserve(alu_group_tracker& gt) {
2080 rp_kcache_tracker &kt = gt.kcache();
2081
2082 if (!kt.num_sels())
2083 return true;
2084
2085 sb_set<unsigned> group_lines;
2086
2087 unsigned nl = kt.get_lines(group_lines);
2088 assert(nl);
2089
2090 sb_set<unsigned> clause_lines(lines);
2091 lines.add_set(group_lines);
2092
2093 if (clause_lines.size() == lines.size())
2094 return true;
2095
2096 if (update_kc())
2097 return true;
2098
2099 lines = clause_lines;
2100
2101 return false;
2102 }
2103
get_lines(kc_lines & lines)2104 unsigned rp_kcache_tracker::get_lines(kc_lines& lines) {
2105 unsigned cnt = 0;
2106
2107 for (unsigned i = 0; i < sel_count; ++i) {
2108 unsigned line = rp[i] & 0x1fffffffu;
2109 unsigned index_mode = rp[i] >> 29;
2110
2111 if (!line)
2112 return cnt;
2113
2114 --line;
2115 line = (sel_count == 2) ? line >> 5 : line >> 6;
2116 line |= index_mode << 29;
2117
2118 if (lines.insert(line).second)
2119 ++cnt;
2120 }
2121 return cnt;
2122 }
2123
update_kc()2124 bool alu_kcache_tracker::update_kc() {
2125 unsigned c = 0;
2126
2127 bc_kcache old_kc[4];
2128 memcpy(old_kc, kc, sizeof(kc));
2129
2130 for (kc_lines::iterator I = lines.begin(), E = lines.end(); I != E; ++I) {
2131 unsigned index_mode = *I >> 29;
2132 unsigned line = *I & 0x1fffffffu;
2133 unsigned bank = line >> 8;
2134
2135 assert(index_mode <= KC_INDEX_INVALID);
2136 line &= 0xFF;
2137
2138 if (c && (bank == kc[c-1].bank) && (kc[c-1].addr + 1 == line) &&
2139 kc[c-1].index_mode == index_mode)
2140 {
2141 kc[c-1].mode = KC_LOCK_2;
2142 } else {
2143 if (c == max_kcs) {
2144 memcpy(kc, old_kc, sizeof(kc));
2145 return false;
2146 }
2147
2148 kc[c].mode = KC_LOCK_1;
2149
2150 kc[c].bank = bank;
2151 kc[c].addr = line;
2152 kc[c].index_mode = index_mode;
2153 ++c;
2154 }
2155 }
2156 return true;
2157 }
2158
create_ar_load(value * v,chan_select ar_channel)2159 alu_node* alu_clause_tracker::create_ar_load(value *v, chan_select ar_channel) {
2160 alu_node *a = sh.create_alu();
2161
2162 if (sh.get_ctx().uses_mova_gpr) {
2163 a->bc.set_op(ALU_OP1_MOVA_GPR_INT);
2164 a->bc.slot = SLOT_TRANS;
2165 } else {
2166 a->bc.set_op(ALU_OP1_MOVA_INT);
2167 a->bc.slot = SLOT_X;
2168 }
2169 a->bc.dst_chan = ar_channel;
2170 if (ar_channel != SEL_X && sh.get_ctx().is_cayman()) {
2171 a->bc.dst_gpr = ar_channel == SEL_Y ? CM_V_SQ_MOVA_DST_CF_IDX0 : CM_V_SQ_MOVA_DST_CF_IDX1;
2172 }
2173
2174 a->dst.resize(1);
2175 a->src.push_back(v);
2176
2177 PSC_DUMP(
2178 sblog << "created AR load: ";
2179 dump::dump_op(a);
2180 sblog << "\n";
2181 );
2182
2183 return a;
2184 }
2185
discard_current_group()2186 void alu_clause_tracker::discard_current_group() {
2187 PSC_DUMP( sblog << "act::discard_current_group\n"; );
2188 grp().discard_all_slots(conflict_nodes);
2189 }
2190
dump()2191 void rp_gpr_tracker::dump() {
2192 sblog << "=== gpr_tracker dump:\n";
2193 for (int c = 0; c < 3; ++c) {
2194 sblog << "cycle " << c << " ";
2195 for (int h = 0; h < 4; ++h) {
2196 sblog << rp[c][h] << ":" << uc[c][h] << " ";
2197 }
2198 sblog << "\n";
2199 }
2200 }
2201
2202 } // namespace r600_sb
2203