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1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * MUSB OTG driver core code
4  *
5  * Copyright 2005 Mentor Graphics Corporation
6  * Copyright (C) 2005-2006 by Texas Instruments
7  * Copyright (C) 2006-2007 Nokia Corporation
8  */
9 
10 /*
11  * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
12  *
13  * This consists of a Host Controller Driver (HCD) and a peripheral
14  * controller driver implementing the "Gadget" API; OTG support is
15  * in the works.  These are normal Linux-USB controller drivers which
16  * use IRQs and have no dedicated thread.
17  *
18  * This version of the driver has only been used with products from
19  * Texas Instruments.  Those products integrate the Inventra logic
20  * with other DMA, IRQ, and bus modules, as well as other logic that
21  * needs to be reflected in this driver.
22  *
23  *
24  * NOTE:  the original Mentor code here was pretty much a collection
25  * of mechanisms that don't seem to have been fully integrated/working
26  * for *any* Linux kernel version.  This version aims at Linux 2.6.now,
27  * Key open issues include:
28  *
29  *  - Lack of host-side transaction scheduling, for all transfer types.
30  *    The hardware doesn't do it; instead, software must.
31  *
32  *    This is not an issue for OTG devices that don't support external
33  *    hubs, but for more "normal" USB hosts it's a user issue that the
34  *    "multipoint" support doesn't scale in the expected ways.  That
35  *    includes DaVinci EVM in a common non-OTG mode.
36  *
37  *      * Control and bulk use dedicated endpoints, and there's as
38  *        yet no mechanism to either (a) reclaim the hardware when
39  *        peripherals are NAKing, which gets complicated with bulk
40  *        endpoints, or (b) use more than a single bulk endpoint in
41  *        each direction.
42  *
43  *        RESULT:  one device may be perceived as blocking another one.
44  *
45  *      * Interrupt and isochronous will dynamically allocate endpoint
46  *        hardware, but (a) there's no record keeping for bandwidth;
47  *        (b) in the common case that few endpoints are available, there
48  *        is no mechanism to reuse endpoints to talk to multiple devices.
49  *
50  *        RESULT:  At one extreme, bandwidth can be overcommitted in
51  *        some hardware configurations, no faults will be reported.
52  *        At the other extreme, the bandwidth capabilities which do
53  *        exist tend to be severely undercommitted.  You can't yet hook
54  *        up both a keyboard and a mouse to an external USB hub.
55  */
56 
57 /*
58  * This gets many kinds of configuration information:
59  *	- Kconfig for everything user-configurable
60  *	- platform_device for addressing, irq, and platform_data
61  *	- platform_data is mostly for board-specific informarion
62  *	  (plus recentrly, SOC or family details)
63  *
64  * Most of the conditional compilation will (someday) vanish.
65  */
66 
67 #ifndef __UBOOT__
68 #include <linux/module.h>
69 #include <linux/kernel.h>
70 #include <linux/sched.h>
71 #include <linux/slab.h>
72 #include <linux/init.h>
73 #include <linux/list.h>
74 #include <linux/kobject.h>
75 #include <linux/prefetch.h>
76 #include <linux/platform_device.h>
77 #include <linux/io.h>
78 #else
79 #include <common.h>
80 #include <usb.h>
81 #include <linux/errno.h>
82 #include <linux/usb/ch9.h>
83 #include <linux/usb/gadget.h>
84 #include <linux/usb/musb.h>
85 #include <asm/io.h>
86 #include "linux-compat.h"
87 #include "usb-compat.h"
88 #endif
89 
90 #include "musb_core.h"
91 
92 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
93 
94 
95 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
96 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
97 
98 #define MUSB_VERSION "6.0"
99 
100 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
101 
102 #define MUSB_DRIVER_NAME "musb-hdrc"
103 const char musb_driver_name[] = MUSB_DRIVER_NAME;
104 
105 MODULE_DESCRIPTION(DRIVER_INFO);
106 MODULE_AUTHOR(DRIVER_AUTHOR);
107 MODULE_LICENSE("GPL");
108 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
109 
110 
111 #ifndef __UBOOT__
112 /*-------------------------------------------------------------------------*/
113 
dev_to_musb(struct device * dev)114 static inline struct musb *dev_to_musb(struct device *dev)
115 {
116 	return dev_get_drvdata(dev);
117 }
118 
119 /*-------------------------------------------------------------------------*/
120 
musb_ulpi_read(struct usb_phy * phy,u32 offset)121 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
122 {
123 	void __iomem *addr = phy->io_priv;
124 	int	i = 0;
125 	u8	r;
126 	u8	power;
127 	int	ret;
128 
129 	pm_runtime_get_sync(phy->io_dev);
130 
131 	/* Make sure the transceiver is not in low power mode */
132 	power = musb_readb(addr, MUSB_POWER);
133 	power &= ~MUSB_POWER_SUSPENDM;
134 	musb_writeb(addr, MUSB_POWER, power);
135 
136 	/* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
137 	 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
138 	 */
139 
140 	musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
141 	musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
142 			MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
143 
144 	while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
145 				& MUSB_ULPI_REG_CMPLT)) {
146 		i++;
147 		if (i == 10000) {
148 			ret = -ETIMEDOUT;
149 			goto out;
150 		}
151 
152 	}
153 	r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
154 	r &= ~MUSB_ULPI_REG_CMPLT;
155 	musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
156 
157 	ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
158 
159 out:
160 	pm_runtime_put(phy->io_dev);
161 
162 	return ret;
163 }
164 
musb_ulpi_write(struct usb_phy * phy,u32 offset,u32 data)165 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
166 {
167 	void __iomem *addr = phy->io_priv;
168 	int	i = 0;
169 	u8	r = 0;
170 	u8	power;
171 	int	ret = 0;
172 
173 	pm_runtime_get_sync(phy->io_dev);
174 
175 	/* Make sure the transceiver is not in low power mode */
176 	power = musb_readb(addr, MUSB_POWER);
177 	power &= ~MUSB_POWER_SUSPENDM;
178 	musb_writeb(addr, MUSB_POWER, power);
179 
180 	musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
181 	musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
182 	musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
183 
184 	while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
185 				& MUSB_ULPI_REG_CMPLT)) {
186 		i++;
187 		if (i == 10000) {
188 			ret = -ETIMEDOUT;
189 			goto out;
190 		}
191 	}
192 
193 	r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
194 	r &= ~MUSB_ULPI_REG_CMPLT;
195 	musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
196 
197 out:
198 	pm_runtime_put(phy->io_dev);
199 
200 	return ret;
201 }
202 
203 static struct usb_phy_io_ops musb_ulpi_access = {
204 	.read = musb_ulpi_read,
205 	.write = musb_ulpi_write,
206 };
207 #endif
208 
209 /*-------------------------------------------------------------------------*/
210 
211 #if !defined(CONFIG_USB_MUSB_TUSB6010)
212 
213 /*
214  * Load an endpoint's FIFO
215  */
musb_write_fifo(struct musb_hw_ep * hw_ep,u16 len,const u8 * src)216 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
217 {
218 	struct musb *musb = hw_ep->musb;
219 	void __iomem *fifo = hw_ep->fifo;
220 
221 	prefetch((u8 *)src);
222 
223 	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
224 			'T', hw_ep->epnum, fifo, len, src);
225 
226 	/* we can't assume unaligned reads work */
227 	if (likely((0x01 & (unsigned long) src) == 0)) {
228 		u16	index = 0;
229 
230 		/* best case is 32bit-aligned source address */
231 		if ((0x02 & (unsigned long) src) == 0) {
232 			if (len >= 4) {
233 				writesl(fifo, src + index, len >> 2);
234 				index += len & ~0x03;
235 			}
236 			if (len & 0x02) {
237 				musb_writew(fifo, 0, *(u16 *)&src[index]);
238 				index += 2;
239 			}
240 		} else {
241 			if (len >= 2) {
242 				writesw(fifo, src + index, len >> 1);
243 				index += len & ~0x01;
244 			}
245 		}
246 		if (len & 0x01)
247 			musb_writeb(fifo, 0, src[index]);
248 	} else  {
249 		/* byte aligned */
250 		writesb(fifo, src, len);
251 	}
252 }
253 
254 #if !defined(CONFIG_USB_MUSB_AM35X) && !defined(CONFIG_USB_MUSB_PIC32)
255 /*
256  * Unload an endpoint's FIFO
257  */
musb_read_fifo(struct musb_hw_ep * hw_ep,u16 len,u8 * dst)258 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
259 {
260 	struct musb *musb = hw_ep->musb;
261 	void __iomem *fifo = hw_ep->fifo;
262 
263 	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
264 			'R', hw_ep->epnum, fifo, len, dst);
265 
266 	/* we can't assume unaligned writes work */
267 	if (likely((0x01 & (unsigned long) dst) == 0)) {
268 		u16	index = 0;
269 
270 		/* best case is 32bit-aligned destination address */
271 		if ((0x02 & (unsigned long) dst) == 0) {
272 			if (len >= 4) {
273 				readsl(fifo, dst, len >> 2);
274 				index = len & ~0x03;
275 			}
276 			if (len & 0x02) {
277 				*(u16 *)&dst[index] = musb_readw(fifo, 0);
278 				index += 2;
279 			}
280 		} else {
281 			if (len >= 2) {
282 				readsw(fifo, dst, len >> 1);
283 				index = len & ~0x01;
284 			}
285 		}
286 		if (len & 0x01)
287 			dst[index] = musb_readb(fifo, 0);
288 	} else  {
289 		/* byte aligned */
290 		readsb(fifo, dst, len);
291 	}
292 }
293 #endif
294 
295 #endif	/* normal PIO */
296 
297 
298 /*-------------------------------------------------------------------------*/
299 
300 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
301 static const u8 musb_test_packet[53] = {
302 	/* implicit SYNC then DATA0 to start */
303 
304 	/* JKJKJKJK x9 */
305 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
306 	/* JJKKJJKK x8 */
307 	0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
308 	/* JJJJKKKK x8 */
309 	0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
310 	/* JJJJJJJKKKKKKK x8 */
311 	0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
312 	/* JJJJJJJK x8 */
313 	0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
314 	/* JKKKKKKK x10, JK */
315 	0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
316 
317 	/* implicit CRC16 then EOP to end */
318 };
319 
musb_load_testpacket(struct musb * musb)320 void musb_load_testpacket(struct musb *musb)
321 {
322 	void __iomem	*regs = musb->endpoints[0].regs;
323 
324 	musb_ep_select(musb->mregs, 0);
325 	musb_write_fifo(musb->control_ep,
326 			sizeof(musb_test_packet), musb_test_packet);
327 	musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
328 }
329 
330 #ifndef __UBOOT__
331 /*-------------------------------------------------------------------------*/
332 
333 /*
334  * Handles OTG hnp timeouts, such as b_ase0_brst
335  */
musb_otg_timer_func(unsigned long data)336 void musb_otg_timer_func(unsigned long data)
337 {
338 	struct musb	*musb = (struct musb *)data;
339 	unsigned long	flags;
340 
341 	spin_lock_irqsave(&musb->lock, flags);
342 	switch (musb->xceiv->state) {
343 	case OTG_STATE_B_WAIT_ACON:
344 		dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
345 		musb_g_disconnect(musb);
346 		musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
347 		musb->is_active = 0;
348 		break;
349 	case OTG_STATE_A_SUSPEND:
350 	case OTG_STATE_A_WAIT_BCON:
351 		dev_dbg(musb->controller, "HNP: %s timeout\n",
352 			otg_state_string(musb->xceiv->state));
353 		musb_platform_set_vbus(musb, 0);
354 		musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
355 		break;
356 	default:
357 		dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
358 			otg_state_string(musb->xceiv->state));
359 	}
360 	musb->ignore_disconnect = 0;
361 	spin_unlock_irqrestore(&musb->lock, flags);
362 }
363 
364 /*
365  * Stops the HNP transition. Caller must take care of locking.
366  */
musb_hnp_stop(struct musb * musb)367 void musb_hnp_stop(struct musb *musb)
368 {
369 	struct usb_hcd	*hcd = musb_to_hcd(musb);
370 	void __iomem	*mbase = musb->mregs;
371 	u8	reg;
372 
373 	dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
374 
375 	switch (musb->xceiv->state) {
376 	case OTG_STATE_A_PERIPHERAL:
377 		musb_g_disconnect(musb);
378 		dev_dbg(musb->controller, "HNP: back to %s\n",
379 			otg_state_string(musb->xceiv->state));
380 		break;
381 	case OTG_STATE_B_HOST:
382 		dev_dbg(musb->controller, "HNP: Disabling HR\n");
383 		hcd->self.is_b_host = 0;
384 		musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
385 		MUSB_DEV_MODE(musb);
386 		reg = musb_readb(mbase, MUSB_POWER);
387 		reg |= MUSB_POWER_SUSPENDM;
388 		musb_writeb(mbase, MUSB_POWER, reg);
389 		/* REVISIT: Start SESSION_REQUEST here? */
390 		break;
391 	default:
392 		dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
393 			otg_state_string(musb->xceiv->state));
394 	}
395 
396 	/*
397 	 * When returning to A state after HNP, avoid hub_port_rebounce(),
398 	 * which cause occasional OPT A "Did not receive reset after connect"
399 	 * errors.
400 	 */
401 	musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
402 }
403 #endif
404 
405 /*
406  * Interrupt Service Routine to record USB "global" interrupts.
407  * Since these do not happen often and signify things of
408  * paramount importance, it seems OK to check them individually;
409  * the order of the tests is specified in the manual
410  *
411  * @param musb instance pointer
412  * @param int_usb register contents
413  * @param devctl
414  * @param power
415  */
416 
musb_stage0_irq(struct musb * musb,u8 int_usb,u8 devctl,u8 power)417 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
418 				u8 devctl, u8 power)
419 {
420 #ifndef __UBOOT__
421 	struct usb_otg *otg = musb->xceiv->otg;
422 #endif
423 	irqreturn_t handled = IRQ_NONE;
424 
425 	dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
426 		int_usb);
427 
428 #ifndef __UBOOT__
429 	/* in host mode, the peripheral may issue remote wakeup.
430 	 * in peripheral mode, the host may resume the link.
431 	 * spurious RESUME irqs happen too, paired with SUSPEND.
432 	 */
433 	if (int_usb & MUSB_INTR_RESUME) {
434 		handled = IRQ_HANDLED;
435 		dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
436 
437 		if (devctl & MUSB_DEVCTL_HM) {
438 			void __iomem *mbase = musb->mregs;
439 
440 			switch (musb->xceiv->state) {
441 			case OTG_STATE_A_SUSPEND:
442 				/* remote wakeup?  later, GetPortStatus
443 				 * will stop RESUME signaling
444 				 */
445 
446 				if (power & MUSB_POWER_SUSPENDM) {
447 					/* spurious */
448 					musb->int_usb &= ~MUSB_INTR_SUSPEND;
449 					dev_dbg(musb->controller, "Spurious SUSPENDM\n");
450 					break;
451 				}
452 
453 				power &= ~MUSB_POWER_SUSPENDM;
454 				musb_writeb(mbase, MUSB_POWER,
455 						power | MUSB_POWER_RESUME);
456 
457 				musb->port1_status |=
458 						(USB_PORT_STAT_C_SUSPEND << 16)
459 						| MUSB_PORT_STAT_RESUME;
460 				musb->rh_timer = jiffies
461 						+ msecs_to_jiffies(20);
462 
463 				musb->xceiv->state = OTG_STATE_A_HOST;
464 				musb->is_active = 1;
465 				usb_hcd_resume_root_hub(musb_to_hcd(musb));
466 				break;
467 			case OTG_STATE_B_WAIT_ACON:
468 				musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
469 				musb->is_active = 1;
470 				MUSB_DEV_MODE(musb);
471 				break;
472 			default:
473 				WARNING("bogus %s RESUME (%s)\n",
474 					"host",
475 					otg_state_string(musb->xceiv->state));
476 			}
477 		} else {
478 			switch (musb->xceiv->state) {
479 			case OTG_STATE_A_SUSPEND:
480 				/* possibly DISCONNECT is upcoming */
481 				musb->xceiv->state = OTG_STATE_A_HOST;
482 				usb_hcd_resume_root_hub(musb_to_hcd(musb));
483 				break;
484 			case OTG_STATE_B_WAIT_ACON:
485 			case OTG_STATE_B_PERIPHERAL:
486 				/* disconnect while suspended?  we may
487 				 * not get a disconnect irq...
488 				 */
489 				if ((devctl & MUSB_DEVCTL_VBUS)
490 						!= (3 << MUSB_DEVCTL_VBUS_SHIFT)
491 						) {
492 					musb->int_usb |= MUSB_INTR_DISCONNECT;
493 					musb->int_usb &= ~MUSB_INTR_SUSPEND;
494 					break;
495 				}
496 				musb_g_resume(musb);
497 				break;
498 			case OTG_STATE_B_IDLE:
499 				musb->int_usb &= ~MUSB_INTR_SUSPEND;
500 				break;
501 			default:
502 				WARNING("bogus %s RESUME (%s)\n",
503 					"peripheral",
504 					otg_state_string(musb->xceiv->state));
505 			}
506 		}
507 	}
508 
509 	/* see manual for the order of the tests */
510 	if (int_usb & MUSB_INTR_SESSREQ) {
511 		void __iomem *mbase = musb->mregs;
512 
513 		if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
514 				&& (devctl & MUSB_DEVCTL_BDEVICE)) {
515 			dev_dbg(musb->controller, "SessReq while on B state\n");
516 			return IRQ_HANDLED;
517 		}
518 
519 		dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
520 			otg_state_string(musb->xceiv->state));
521 
522 		/* IRQ arrives from ID pin sense or (later, if VBUS power
523 		 * is removed) SRP.  responses are time critical:
524 		 *  - turn on VBUS (with silicon-specific mechanism)
525 		 *  - go through A_WAIT_VRISE
526 		 *  - ... to A_WAIT_BCON.
527 		 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
528 		 */
529 		musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
530 		musb->ep0_stage = MUSB_EP0_START;
531 		musb->xceiv->state = OTG_STATE_A_IDLE;
532 		MUSB_HST_MODE(musb);
533 		musb_platform_set_vbus(musb, 1);
534 
535 		handled = IRQ_HANDLED;
536 	}
537 
538 	if (int_usb & MUSB_INTR_VBUSERROR) {
539 		int	ignore = 0;
540 
541 		/* During connection as an A-Device, we may see a short
542 		 * current spikes causing voltage drop, because of cable
543 		 * and peripheral capacitance combined with vbus draw.
544 		 * (So: less common with truly self-powered devices, where
545 		 * vbus doesn't act like a power supply.)
546 		 *
547 		 * Such spikes are short; usually less than ~500 usec, max
548 		 * of ~2 msec.  That is, they're not sustained overcurrent
549 		 * errors, though they're reported using VBUSERROR irqs.
550 		 *
551 		 * Workarounds:  (a) hardware: use self powered devices.
552 		 * (b) software:  ignore non-repeated VBUS errors.
553 		 *
554 		 * REVISIT:  do delays from lots of DEBUG_KERNEL checks
555 		 * make trouble here, keeping VBUS < 4.4V ?
556 		 */
557 		switch (musb->xceiv->state) {
558 		case OTG_STATE_A_HOST:
559 			/* recovery is dicey once we've gotten past the
560 			 * initial stages of enumeration, but if VBUS
561 			 * stayed ok at the other end of the link, and
562 			 * another reset is due (at least for high speed,
563 			 * to redo the chirp etc), it might work OK...
564 			 */
565 		case OTG_STATE_A_WAIT_BCON:
566 		case OTG_STATE_A_WAIT_VRISE:
567 			if (musb->vbuserr_retry) {
568 				void __iomem *mbase = musb->mregs;
569 
570 				musb->vbuserr_retry--;
571 				ignore = 1;
572 				devctl |= MUSB_DEVCTL_SESSION;
573 				musb_writeb(mbase, MUSB_DEVCTL, devctl);
574 			} else {
575 				musb->port1_status |=
576 					  USB_PORT_STAT_OVERCURRENT
577 					| (USB_PORT_STAT_C_OVERCURRENT << 16);
578 			}
579 			break;
580 		default:
581 			break;
582 		}
583 
584 		dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
585 				otg_state_string(musb->xceiv->state),
586 				devctl,
587 				({ char *s;
588 				switch (devctl & MUSB_DEVCTL_VBUS) {
589 				case 0 << MUSB_DEVCTL_VBUS_SHIFT:
590 					s = "<SessEnd"; break;
591 				case 1 << MUSB_DEVCTL_VBUS_SHIFT:
592 					s = "<AValid"; break;
593 				case 2 << MUSB_DEVCTL_VBUS_SHIFT:
594 					s = "<VBusValid"; break;
595 				/* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
596 				default:
597 					s = "VALID"; break;
598 				}; s; }),
599 				VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
600 				musb->port1_status);
601 
602 		/* go through A_WAIT_VFALL then start a new session */
603 		if (!ignore)
604 			musb_platform_set_vbus(musb, 0);
605 		handled = IRQ_HANDLED;
606 	}
607 
608 	if (int_usb & MUSB_INTR_SUSPEND) {
609 		dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
610 			otg_state_string(musb->xceiv->state), devctl, power);
611 		handled = IRQ_HANDLED;
612 
613 		switch (musb->xceiv->state) {
614 		case OTG_STATE_A_PERIPHERAL:
615 			/* We also come here if the cable is removed, since
616 			 * this silicon doesn't report ID-no-longer-grounded.
617 			 *
618 			 * We depend on T(a_wait_bcon) to shut us down, and
619 			 * hope users don't do anything dicey during this
620 			 * undesired detour through A_WAIT_BCON.
621 			 */
622 			musb_hnp_stop(musb);
623 			usb_hcd_resume_root_hub(musb_to_hcd(musb));
624 			musb_root_disconnect(musb);
625 			musb_platform_try_idle(musb, jiffies
626 					+ msecs_to_jiffies(musb->a_wait_bcon
627 						? : OTG_TIME_A_WAIT_BCON));
628 
629 			break;
630 		case OTG_STATE_B_IDLE:
631 			if (!musb->is_active)
632 				break;
633 		case OTG_STATE_B_PERIPHERAL:
634 			musb_g_suspend(musb);
635 			musb->is_active = is_otg_enabled(musb)
636 					&& otg->gadget->b_hnp_enable;
637 			if (musb->is_active) {
638 				musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
639 				dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
640 				mod_timer(&musb->otg_timer, jiffies
641 					+ msecs_to_jiffies(
642 							OTG_TIME_B_ASE0_BRST));
643 			}
644 			break;
645 		case OTG_STATE_A_WAIT_BCON:
646 			if (musb->a_wait_bcon != 0)
647 				musb_platform_try_idle(musb, jiffies
648 					+ msecs_to_jiffies(musb->a_wait_bcon));
649 			break;
650 		case OTG_STATE_A_HOST:
651 			musb->xceiv->state = OTG_STATE_A_SUSPEND;
652 			musb->is_active = is_otg_enabled(musb)
653 					&& otg->host->b_hnp_enable;
654 			break;
655 		case OTG_STATE_B_HOST:
656 			/* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
657 			dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
658 			break;
659 		default:
660 			/* "should not happen" */
661 			musb->is_active = 0;
662 			break;
663 		}
664 	}
665 #endif
666 
667 	if (int_usb & MUSB_INTR_CONNECT) {
668 		struct usb_hcd *hcd = musb_to_hcd(musb);
669 
670 		handled = IRQ_HANDLED;
671 		musb->is_active = 1;
672 
673 		musb->ep0_stage = MUSB_EP0_START;
674 
675 		/* flush endpoints when transitioning from Device Mode */
676 		if (is_peripheral_active(musb)) {
677 			/* REVISIT HNP; just force disconnect */
678 		}
679 		musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
680 		musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
681 		musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
682 #ifndef __UBOOT__
683 		musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
684 					|USB_PORT_STAT_HIGH_SPEED
685 					|USB_PORT_STAT_ENABLE
686 					);
687 		musb->port1_status |= USB_PORT_STAT_CONNECTION
688 					|(USB_PORT_STAT_C_CONNECTION << 16);
689 
690 		/* high vs full speed is just a guess until after reset */
691 		if (devctl & MUSB_DEVCTL_LSDEV)
692 			musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
693 
694 		/* indicate new connection to OTG machine */
695 		switch (musb->xceiv->state) {
696 		case OTG_STATE_B_PERIPHERAL:
697 			if (int_usb & MUSB_INTR_SUSPEND) {
698 				dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
699 				int_usb &= ~MUSB_INTR_SUSPEND;
700 				goto b_host;
701 			} else
702 				dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
703 			break;
704 		case OTG_STATE_B_WAIT_ACON:
705 			dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
706 b_host:
707 			musb->xceiv->state = OTG_STATE_B_HOST;
708 			hcd->self.is_b_host = 1;
709 			musb->ignore_disconnect = 0;
710 			del_timer(&musb->otg_timer);
711 			break;
712 		default:
713 			if ((devctl & MUSB_DEVCTL_VBUS)
714 					== (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
715 				musb->xceiv->state = OTG_STATE_A_HOST;
716 				hcd->self.is_b_host = 0;
717 			}
718 			break;
719 		}
720 
721 		/* poke the root hub */
722 		MUSB_HST_MODE(musb);
723 		if (hcd->status_urb)
724 			usb_hcd_poll_rh_status(hcd);
725 		else
726 			usb_hcd_resume_root_hub(hcd);
727 
728 		dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
729 				otg_state_string(musb->xceiv->state), devctl);
730 #endif
731 	}
732 
733 #ifndef __UBOOT__
734 	if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
735 		dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
736 				otg_state_string(musb->xceiv->state),
737 				MUSB_MODE(musb), devctl);
738 		handled = IRQ_HANDLED;
739 
740 		switch (musb->xceiv->state) {
741 		case OTG_STATE_A_HOST:
742 		case OTG_STATE_A_SUSPEND:
743 			usb_hcd_resume_root_hub(musb_to_hcd(musb));
744 			musb_root_disconnect(musb);
745 			if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
746 				musb_platform_try_idle(musb, jiffies
747 					+ msecs_to_jiffies(musb->a_wait_bcon));
748 			break;
749 		case OTG_STATE_B_HOST:
750 			/* REVISIT this behaves for "real disconnect"
751 			 * cases; make sure the other transitions from
752 			 * from B_HOST act right too.  The B_HOST code
753 			 * in hnp_stop() is currently not used...
754 			 */
755 			musb_root_disconnect(musb);
756 			musb_to_hcd(musb)->self.is_b_host = 0;
757 			musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
758 			MUSB_DEV_MODE(musb);
759 			musb_g_disconnect(musb);
760 			break;
761 		case OTG_STATE_A_PERIPHERAL:
762 			musb_hnp_stop(musb);
763 			musb_root_disconnect(musb);
764 			/* FALLTHROUGH */
765 		case OTG_STATE_B_WAIT_ACON:
766 			/* FALLTHROUGH */
767 		case OTG_STATE_B_PERIPHERAL:
768 		case OTG_STATE_B_IDLE:
769 			musb_g_disconnect(musb);
770 			break;
771 		default:
772 			WARNING("unhandled DISCONNECT transition (%s)\n",
773 				otg_state_string(musb->xceiv->state));
774 			break;
775 		}
776 	}
777 
778 	/* mentor saves a bit: bus reset and babble share the same irq.
779 	 * only host sees babble; only peripheral sees bus reset.
780 	 */
781 	if (int_usb & MUSB_INTR_RESET) {
782 		handled = IRQ_HANDLED;
783 		if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
784 			/*
785 			 * Looks like non-HS BABBLE can be ignored, but
786 			 * HS BABBLE is an error condition. For HS the solution
787 			 * is to avoid babble in the first place and fix what
788 			 * caused BABBLE. When HS BABBLE happens we can only
789 			 * stop the session.
790 			 */
791 			if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
792 				dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
793 			else {
794 				ERR("Stopping host session -- babble\n");
795 				musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
796 			}
797 		} else if (is_peripheral_capable()) {
798 			dev_dbg(musb->controller, "BUS RESET as %s\n",
799 				otg_state_string(musb->xceiv->state));
800 			switch (musb->xceiv->state) {
801 			case OTG_STATE_A_SUSPEND:
802 				/* We need to ignore disconnect on suspend
803 				 * otherwise tusb 2.0 won't reconnect after a
804 				 * power cycle, which breaks otg compliance.
805 				 */
806 				musb->ignore_disconnect = 1;
807 				musb_g_reset(musb);
808 				/* FALLTHROUGH */
809 			case OTG_STATE_A_WAIT_BCON:	/* OPT TD.4.7-900ms */
810 				/* never use invalid T(a_wait_bcon) */
811 				dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
812 					otg_state_string(musb->xceiv->state),
813 					TA_WAIT_BCON(musb));
814 				mod_timer(&musb->otg_timer, jiffies
815 					+ msecs_to_jiffies(TA_WAIT_BCON(musb)));
816 				break;
817 			case OTG_STATE_A_PERIPHERAL:
818 				musb->ignore_disconnect = 0;
819 				del_timer(&musb->otg_timer);
820 				musb_g_reset(musb);
821 				break;
822 			case OTG_STATE_B_WAIT_ACON:
823 				dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
824 					otg_state_string(musb->xceiv->state));
825 				musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
826 				musb_g_reset(musb);
827 				break;
828 			case OTG_STATE_B_IDLE:
829 				musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
830 				/* FALLTHROUGH */
831 			case OTG_STATE_B_PERIPHERAL:
832 				musb_g_reset(musb);
833 				break;
834 			default:
835 				dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
836 					otg_state_string(musb->xceiv->state));
837 			}
838 		}
839 	}
840 #endif
841 
842 #if 0
843 /* REVISIT ... this would be for multiplexing periodic endpoints, or
844  * supporting transfer phasing to prevent exceeding ISO bandwidth
845  * limits of a given frame or microframe.
846  *
847  * It's not needed for peripheral side, which dedicates endpoints;
848  * though it _might_ use SOF irqs for other purposes.
849  *
850  * And it's not currently needed for host side, which also dedicates
851  * endpoints, relies on TX/RX interval registers, and isn't claimed
852  * to support ISO transfers yet.
853  */
854 	if (int_usb & MUSB_INTR_SOF) {
855 		void __iomem *mbase = musb->mregs;
856 		struct musb_hw_ep	*ep;
857 		u8 epnum;
858 		u16 frame;
859 
860 		dev_dbg(musb->controller, "START_OF_FRAME\n");
861 		handled = IRQ_HANDLED;
862 
863 		/* start any periodic Tx transfers waiting for current frame */
864 		frame = musb_readw(mbase, MUSB_FRAME);
865 		ep = musb->endpoints;
866 		for (epnum = 1; (epnum < musb->nr_endpoints)
867 					&& (musb->epmask >= (1 << epnum));
868 				epnum++, ep++) {
869 			/*
870 			 * FIXME handle framecounter wraps (12 bits)
871 			 * eliminate duplicated StartUrb logic
872 			 */
873 			if (ep->dwWaitFrame >= frame) {
874 				ep->dwWaitFrame = 0;
875 				pr_debug("SOF --> periodic TX%s on %d\n",
876 					ep->tx_channel ? " DMA" : "",
877 					epnum);
878 				if (!ep->tx_channel)
879 					musb_h_tx_start(musb, epnum);
880 				else
881 					cppi_hostdma_start(musb, epnum);
882 			}
883 		}		/* end of for loop */
884 	}
885 #endif
886 
887 	schedule_work(&musb->irq_work);
888 
889 	return handled;
890 }
891 
892 /*-------------------------------------------------------------------------*/
893 
894 /*
895 * Program the HDRC to start (enable interrupts, dma, etc.).
896 */
897 #ifndef __UBOOT__
musb_start(struct musb * musb)898 void musb_start(struct musb *musb)
899 #else
900 int musb_start(struct musb *musb)
901 #endif
902 {
903 	void __iomem	*regs = musb->mregs;
904 	u8		devctl = musb_readb(regs, MUSB_DEVCTL);
905 #ifdef __UBOOT__
906 	int ret;
907 #endif
908 
909 	dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
910 
911 	/*  Set INT enable registers, enable interrupts */
912 	musb_writew(regs, MUSB_INTRTXE, musb->epmask);
913 	musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
914 	musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
915 
916 	musb_writeb(regs, MUSB_TESTMODE, 0);
917 
918 	/* put into basic highspeed mode and start session */
919 	musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
920 						| MUSB_POWER_HSENAB
921 						/* ENSUSPEND wedges tusb */
922 						/* | MUSB_POWER_ENSUSPEND */
923 						);
924 
925 	musb->is_active = 0;
926 	devctl = musb_readb(regs, MUSB_DEVCTL);
927 	devctl &= ~MUSB_DEVCTL_SESSION;
928 
929 	if (is_otg_enabled(musb)) {
930 #ifndef __UBOOT__
931 		/* session started after:
932 		 * (a) ID-grounded irq, host mode;
933 		 * (b) vbus present/connect IRQ, peripheral mode;
934 		 * (c) peripheral initiates, using SRP
935 		 */
936 		if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
937 			musb->is_active = 1;
938 		else
939 			devctl |= MUSB_DEVCTL_SESSION;
940 #endif
941 
942 	} else if (is_host_enabled(musb)) {
943 		/* assume ID pin is hard-wired to ground */
944 		devctl |= MUSB_DEVCTL_SESSION;
945 
946 	} else /* peripheral is enabled */ {
947 		if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
948 			musb->is_active = 1;
949 	}
950 
951 #ifndef __UBOOT__
952 	musb_platform_enable(musb);
953 #else
954 	ret = musb_platform_enable(musb);
955 	if (ret) {
956 		musb->is_active = 0;
957 		return ret;
958 	}
959 #endif
960 	musb_writeb(regs, MUSB_DEVCTL, devctl);
961 
962 #ifdef __UBOOT__
963 	return 0;
964 #endif
965 }
966 
967 
musb_generic_disable(struct musb * musb)968 static void musb_generic_disable(struct musb *musb)
969 {
970 	void __iomem	*mbase = musb->mregs;
971 	u16	temp;
972 
973 	/* disable interrupts */
974 	musb_writeb(mbase, MUSB_INTRUSBE, 0);
975 	musb_writew(mbase, MUSB_INTRTXE, 0);
976 	musb_writew(mbase, MUSB_INTRRXE, 0);
977 
978 	/* off */
979 	musb_writeb(mbase, MUSB_DEVCTL, 0);
980 
981 	/*  flush pending interrupts */
982 	temp = musb_readb(mbase, MUSB_INTRUSB);
983 	temp = musb_readw(mbase, MUSB_INTRTX);
984 	temp = musb_readw(mbase, MUSB_INTRRX);
985 
986 }
987 
988 /*
989  * Make the HDRC stop (disable interrupts, etc.);
990  * reversible by musb_start
991  * called on gadget driver unregister
992  * with controller locked, irqs blocked
993  * acts as a NOP unless some role activated the hardware
994  */
musb_stop(struct musb * musb)995 void musb_stop(struct musb *musb)
996 {
997 	/* stop IRQs, timers, ... */
998 	musb_platform_disable(musb);
999 	musb_generic_disable(musb);
1000 	dev_dbg(musb->controller, "HDRC disabled\n");
1001 
1002 	/* FIXME
1003 	 *  - mark host and/or peripheral drivers unusable/inactive
1004 	 *  - disable DMA (and enable it in HdrcStart)
1005 	 *  - make sure we can musb_start() after musb_stop(); with
1006 	 *    OTG mode, gadget driver module rmmod/modprobe cycles that
1007 	 *  - ...
1008 	 */
1009 	musb_platform_try_idle(musb, 0);
1010 }
1011 
1012 #ifndef __UBOOT__
musb_shutdown(struct platform_device * pdev)1013 static void musb_shutdown(struct platform_device *pdev)
1014 {
1015 	struct musb	*musb = dev_to_musb(&pdev->dev);
1016 	unsigned long	flags;
1017 
1018 	pm_runtime_get_sync(musb->controller);
1019 
1020 	musb_gadget_cleanup(musb);
1021 
1022 	spin_lock_irqsave(&musb->lock, flags);
1023 	musb_platform_disable(musb);
1024 	musb_generic_disable(musb);
1025 	spin_unlock_irqrestore(&musb->lock, flags);
1026 
1027 	if (!is_otg_enabled(musb) && is_host_enabled(musb))
1028 		usb_remove_hcd(musb_to_hcd(musb));
1029 	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1030 	musb_platform_exit(musb);
1031 
1032 	pm_runtime_put(musb->controller);
1033 	/* FIXME power down */
1034 }
1035 #endif
1036 
1037 
1038 /*-------------------------------------------------------------------------*/
1039 
1040 /*
1041  * The silicon either has hard-wired endpoint configurations, or else
1042  * "dynamic fifo" sizing.  The driver has support for both, though at this
1043  * writing only the dynamic sizing is very well tested.   Since we switched
1044  * away from compile-time hardware parameters, we can no longer rely on
1045  * dead code elimination to leave only the relevant one in the object file.
1046  *
1047  * We don't currently use dynamic fifo setup capability to do anything
1048  * more than selecting one of a bunch of predefined configurations.
1049  */
1050 #if defined(CONFIG_USB_MUSB_TUSB6010)			\
1051 	|| defined(CONFIG_USB_MUSB_TUSB6010_MODULE)	\
1052 	|| defined(CONFIG_USB_MUSB_OMAP2PLUS)		\
1053 	|| defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE)	\
1054 	|| defined(CONFIG_USB_MUSB_AM35X)		\
1055 	|| defined(CONFIG_USB_MUSB_AM35X_MODULE)	\
1056 	|| defined(CONFIG_USB_MUSB_DSPS)		\
1057 	|| defined(CONFIG_USB_MUSB_DSPS_MODULE)
1058 static ushort __devinitdata fifo_mode = 4;
1059 #elif defined(CONFIG_USB_MUSB_UX500)			\
1060 	|| defined(CONFIG_USB_MUSB_UX500_MODULE)
1061 static ushort __devinitdata fifo_mode = 5;
1062 #else
1063 static ushort __devinitdata fifo_mode = 2;
1064 #endif
1065 
1066 /* "modprobe ... fifo_mode=1" etc */
1067 module_param(fifo_mode, ushort, 0);
1068 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1069 
1070 /*
1071  * tables defining fifo_mode values.  define more if you like.
1072  * for host side, make sure both halves of ep1 are set up.
1073  */
1074 
1075 /* mode 0 - fits in 2KB */
1076 static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = {
1077 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
1078 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
1079 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1080 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1081 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1082 };
1083 
1084 /* mode 1 - fits in 4KB */
1085 static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = {
1086 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1087 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1088 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1089 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1090 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1091 };
1092 
1093 /* mode 2 - fits in 4KB */
1094 static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = {
1095 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
1096 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
1097 { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
1098 { .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
1099 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1100 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1101 };
1102 
1103 /* mode 3 - fits in 4KB */
1104 static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = {
1105 { .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1106 { .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, .mode = BUF_DOUBLE, },
1107 { .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
1108 { .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 512, },
1109 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1110 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1111 };
1112 
1113 /* mode 4 - fits in 16KB */
1114 static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = {
1115 { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
1116 { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
1117 { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
1118 { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
1119 { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
1120 { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
1121 { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
1122 { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
1123 { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
1124 { .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 512, },
1125 { .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 512, },
1126 { .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 512, },
1127 { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 512, },
1128 { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 512, },
1129 { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 512, },
1130 { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 512, },
1131 { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 512, },
1132 { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 512, },
1133 { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 256, },
1134 { .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 64, },
1135 { .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 256, },
1136 { .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 64, },
1137 { .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 256, },
1138 { .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 64, },
1139 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1140 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1141 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1142 };
1143 
1144 /* mode 5 - fits in 8KB */
1145 static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = {
1146 { .hw_ep_num =  1, .style = FIFO_TX,   .maxpacket = 512, },
1147 { .hw_ep_num =  1, .style = FIFO_RX,   .maxpacket = 512, },
1148 { .hw_ep_num =  2, .style = FIFO_TX,   .maxpacket = 512, },
1149 { .hw_ep_num =  2, .style = FIFO_RX,   .maxpacket = 512, },
1150 { .hw_ep_num =  3, .style = FIFO_TX,   .maxpacket = 512, },
1151 { .hw_ep_num =  3, .style = FIFO_RX,   .maxpacket = 512, },
1152 { .hw_ep_num =  4, .style = FIFO_TX,   .maxpacket = 512, },
1153 { .hw_ep_num =  4, .style = FIFO_RX,   .maxpacket = 512, },
1154 { .hw_ep_num =  5, .style = FIFO_TX,   .maxpacket = 512, },
1155 { .hw_ep_num =  5, .style = FIFO_RX,   .maxpacket = 512, },
1156 { .hw_ep_num =  6, .style = FIFO_TX,   .maxpacket = 32, },
1157 { .hw_ep_num =  6, .style = FIFO_RX,   .maxpacket = 32, },
1158 { .hw_ep_num =  7, .style = FIFO_TX,   .maxpacket = 32, },
1159 { .hw_ep_num =  7, .style = FIFO_RX,   .maxpacket = 32, },
1160 { .hw_ep_num =  8, .style = FIFO_TX,   .maxpacket = 32, },
1161 { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 32, },
1162 { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 32, },
1163 { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 32, },
1164 { .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 32, },
1165 { .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 32, },
1166 { .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 32, },
1167 { .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 32, },
1168 { .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 32, },
1169 { .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 32, },
1170 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1171 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1172 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1173 };
1174 
1175 /*
1176  * configure a fifo; for non-shared endpoints, this may be called
1177  * once for a tx fifo and once for an rx fifo.
1178  *
1179  * returns negative errno or offset for next fifo.
1180  */
1181 static int __devinit
fifo_setup(struct musb * musb,struct musb_hw_ep * hw_ep,const struct musb_fifo_cfg * cfg,u16 offset)1182 fifo_setup(struct musb *musb, struct musb_hw_ep  *hw_ep,
1183 		const struct musb_fifo_cfg *cfg, u16 offset)
1184 {
1185 	void __iomem	*mbase = musb->mregs;
1186 	int	size = 0;
1187 	u16	maxpacket = cfg->maxpacket;
1188 	u16	c_off = offset >> 3;
1189 	u8	c_size;
1190 
1191 	/* expect hw_ep has already been zero-initialized */
1192 
1193 	size = ffs(max(maxpacket, (u16) 8)) - 1;
1194 	maxpacket = 1 << size;
1195 
1196 	c_size = size - 3;
1197 	if (cfg->mode == BUF_DOUBLE) {
1198 		if ((offset + (maxpacket << 1)) >
1199 				(1 << (musb->config->ram_bits + 2)))
1200 			return -EMSGSIZE;
1201 		c_size |= MUSB_FIFOSZ_DPB;
1202 	} else {
1203 		if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1204 			return -EMSGSIZE;
1205 	}
1206 
1207 	/* configure the FIFO */
1208 	musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1209 
1210 	/* EP0 reserved endpoint for control, bidirectional;
1211 	 * EP1 reserved for bulk, two unidirection halves.
1212 	 */
1213 	if (hw_ep->epnum == 1)
1214 		musb->bulk_ep = hw_ep;
1215 	/* REVISIT error check:  be sure ep0 can both rx and tx ... */
1216 	switch (cfg->style) {
1217 	case FIFO_TX:
1218 		musb_write_txfifosz(mbase, c_size);
1219 		musb_write_txfifoadd(mbase, c_off);
1220 		hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1221 		hw_ep->max_packet_sz_tx = maxpacket;
1222 		break;
1223 	case FIFO_RX:
1224 		musb_write_rxfifosz(mbase, c_size);
1225 		musb_write_rxfifoadd(mbase, c_off);
1226 		hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1227 		hw_ep->max_packet_sz_rx = maxpacket;
1228 		break;
1229 	case FIFO_RXTX:
1230 		musb_write_txfifosz(mbase, c_size);
1231 		musb_write_txfifoadd(mbase, c_off);
1232 		hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1233 		hw_ep->max_packet_sz_rx = maxpacket;
1234 
1235 		musb_write_rxfifosz(mbase, c_size);
1236 		musb_write_rxfifoadd(mbase, c_off);
1237 		hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1238 		hw_ep->max_packet_sz_tx = maxpacket;
1239 
1240 		hw_ep->is_shared_fifo = true;
1241 		break;
1242 	}
1243 
1244 	/* NOTE rx and tx endpoint irqs aren't managed separately,
1245 	 * which happens to be ok
1246 	 */
1247 	musb->epmask |= (1 << hw_ep->epnum);
1248 
1249 	return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1250 }
1251 
1252 static struct musb_fifo_cfg __devinitdata ep0_cfg = {
1253 	.style = FIFO_RXTX, .maxpacket = 64,
1254 };
1255 
ep_config_from_table(struct musb * musb)1256 static int __devinit ep_config_from_table(struct musb *musb)
1257 {
1258 	const struct musb_fifo_cfg	*cfg;
1259 	unsigned		i, n;
1260 	int			offset;
1261 	struct musb_hw_ep	*hw_ep = musb->endpoints;
1262 
1263 	if (musb->config->fifo_cfg) {
1264 		cfg = musb->config->fifo_cfg;
1265 		n = musb->config->fifo_cfg_size;
1266 		goto done;
1267 	}
1268 
1269 	switch (fifo_mode) {
1270 	default:
1271 		fifo_mode = 0;
1272 		/* FALLTHROUGH */
1273 	case 0:
1274 		cfg = mode_0_cfg;
1275 		n = ARRAY_SIZE(mode_0_cfg);
1276 		break;
1277 	case 1:
1278 		cfg = mode_1_cfg;
1279 		n = ARRAY_SIZE(mode_1_cfg);
1280 		break;
1281 	case 2:
1282 		cfg = mode_2_cfg;
1283 		n = ARRAY_SIZE(mode_2_cfg);
1284 		break;
1285 	case 3:
1286 		cfg = mode_3_cfg;
1287 		n = ARRAY_SIZE(mode_3_cfg);
1288 		break;
1289 	case 4:
1290 		cfg = mode_4_cfg;
1291 		n = ARRAY_SIZE(mode_4_cfg);
1292 		break;
1293 	case 5:
1294 		cfg = mode_5_cfg;
1295 		n = ARRAY_SIZE(mode_5_cfg);
1296 		break;
1297 	}
1298 
1299 	pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
1300 
1301 done:
1302 	offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1303 	/* assert(offset > 0) */
1304 
1305 	/* NOTE:  for RTL versions >= 1.400 EPINFO and RAMINFO would
1306 	 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1307 	 */
1308 
1309 	for (i = 0; i < n; i++) {
1310 		u8	epn = cfg->hw_ep_num;
1311 
1312 		if (epn >= musb->config->num_eps) {
1313 			pr_debug("%s: invalid ep %d\n",
1314 					musb_driver_name, epn);
1315 			return -EINVAL;
1316 		}
1317 		offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1318 		if (offset < 0) {
1319 			pr_debug("%s: mem overrun, ep %d\n",
1320 					musb_driver_name, epn);
1321 			return -EINVAL;
1322 		}
1323 		epn++;
1324 		musb->nr_endpoints = max(epn, musb->nr_endpoints);
1325 	}
1326 
1327 	pr_debug("%s: %d/%d max ep, %d/%d memory\n", musb_driver_name, n + 1,
1328 		 musb->config->num_eps * 2 - 1, offset,
1329 		 (1 << (musb->config->ram_bits + 2)));
1330 
1331 	if (!musb->bulk_ep) {
1332 		pr_debug("%s: missing bulk\n", musb_driver_name);
1333 		return -EINVAL;
1334 	}
1335 
1336 	return 0;
1337 }
1338 
1339 
1340 /*
1341  * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1342  * @param musb the controller
1343  */
ep_config_from_hw(struct musb * musb)1344 static int __devinit ep_config_from_hw(struct musb *musb)
1345 {
1346 	u8 epnum = 0;
1347 	struct musb_hw_ep *hw_ep;
1348 	void *mbase = musb->mregs;
1349 	int ret = 0;
1350 
1351 	dev_dbg(musb->controller, "<== static silicon ep config\n");
1352 
1353 	/* FIXME pick up ep0 maxpacket size */
1354 
1355 	for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1356 		musb_ep_select(mbase, epnum);
1357 		hw_ep = musb->endpoints + epnum;
1358 
1359 		ret = musb_read_fifosize(musb, hw_ep, epnum);
1360 		if (ret < 0)
1361 			break;
1362 
1363 		/* FIXME set up hw_ep->{rx,tx}_double_buffered */
1364 
1365 		/* pick an RX/TX endpoint for bulk */
1366 		if (hw_ep->max_packet_sz_tx < 512
1367 				|| hw_ep->max_packet_sz_rx < 512)
1368 			continue;
1369 
1370 		/* REVISIT:  this algorithm is lazy, we should at least
1371 		 * try to pick a double buffered endpoint.
1372 		 */
1373 		if (musb->bulk_ep)
1374 			continue;
1375 		musb->bulk_ep = hw_ep;
1376 	}
1377 
1378 	if (!musb->bulk_ep) {
1379 		pr_debug("%s: missing bulk\n", musb_driver_name);
1380 		return -EINVAL;
1381 	}
1382 
1383 	return 0;
1384 }
1385 
1386 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1387 
1388 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1389  * configure endpoints, or take their config from silicon
1390  */
musb_core_init(u16 musb_type,struct musb * musb)1391 static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
1392 {
1393 	u8 reg;
1394 	char *type;
1395 	char aInfo[90], aRevision[32], aDate[12];
1396 	void __iomem	*mbase = musb->mregs;
1397 	int		status = 0;
1398 	int		i;
1399 
1400 	/* log core options (read using indexed model) */
1401 	reg = musb_read_configdata(mbase);
1402 
1403 	strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1404 	if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1405 		strcat(aInfo, ", dyn FIFOs");
1406 		musb->dyn_fifo = true;
1407 	}
1408 #ifndef CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
1409 	if (reg & MUSB_CONFIGDATA_MPRXE) {
1410 		strcat(aInfo, ", bulk combine");
1411 		musb->bulk_combine = true;
1412 	}
1413 	if (reg & MUSB_CONFIGDATA_MPTXE) {
1414 		strcat(aInfo, ", bulk split");
1415 		musb->bulk_split = true;
1416 	}
1417 #else
1418 	musb->bulk_combine = false;
1419 	musb->bulk_split = false;
1420 #endif
1421 	if (reg & MUSB_CONFIGDATA_HBRXE) {
1422 		strcat(aInfo, ", HB-ISO Rx");
1423 		musb->hb_iso_rx = true;
1424 	}
1425 	if (reg & MUSB_CONFIGDATA_HBTXE) {
1426 		strcat(aInfo, ", HB-ISO Tx");
1427 		musb->hb_iso_tx = true;
1428 	}
1429 	if (reg & MUSB_CONFIGDATA_SOFTCONE)
1430 		strcat(aInfo, ", SoftConn");
1431 
1432 	pr_debug("%s:ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
1433 
1434 	aDate[0] = 0;
1435 	if (MUSB_CONTROLLER_MHDRC == musb_type) {
1436 		musb->is_multipoint = 1;
1437 		type = "M";
1438 	} else {
1439 		musb->is_multipoint = 0;
1440 		type = "";
1441 #ifndef	CONFIG_USB_OTG_BLACKLIST_HUB
1442 		printk(KERN_ERR
1443 			"%s: kernel must blacklist external hubs\n",
1444 			musb_driver_name);
1445 #endif
1446 	}
1447 
1448 	/* log release info */
1449 	musb->hwvers = musb_read_hwvers(mbase);
1450 	snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1451 		MUSB_HWVERS_MINOR(musb->hwvers),
1452 		(musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1453 	pr_debug("%s: %sHDRC RTL version %s %s\n", musb_driver_name, type,
1454 		 aRevision, aDate);
1455 
1456 	/* configure ep0 */
1457 	musb_configure_ep0(musb);
1458 
1459 	/* discover endpoint configuration */
1460 	musb->nr_endpoints = 1;
1461 	musb->epmask = 1;
1462 
1463 	if (musb->dyn_fifo)
1464 		status = ep_config_from_table(musb);
1465 	else
1466 		status = ep_config_from_hw(musb);
1467 
1468 	if (status < 0)
1469 		return status;
1470 
1471 	/* finish init, and print endpoint config */
1472 	for (i = 0; i < musb->nr_endpoints; i++) {
1473 		struct musb_hw_ep	*hw_ep = musb->endpoints + i;
1474 
1475 		hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1476 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1477 		hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1478 		hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1479 		hw_ep->fifo_sync_va =
1480 			musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1481 
1482 		if (i == 0)
1483 			hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1484 		else
1485 			hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1486 #endif
1487 
1488 		hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1489 		hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1490 		hw_ep->rx_reinit = 1;
1491 		hw_ep->tx_reinit = 1;
1492 
1493 		if (hw_ep->max_packet_sz_tx) {
1494 			dev_dbg(musb->controller,
1495 				"%s: hw_ep %d%s, %smax %d\n",
1496 				musb_driver_name, i,
1497 				hw_ep->is_shared_fifo ? "shared" : "tx",
1498 				hw_ep->tx_double_buffered
1499 					? "doublebuffer, " : "",
1500 				hw_ep->max_packet_sz_tx);
1501 		}
1502 		if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1503 			dev_dbg(musb->controller,
1504 				"%s: hw_ep %d%s, %smax %d\n",
1505 				musb_driver_name, i,
1506 				"rx",
1507 				hw_ep->rx_double_buffered
1508 					? "doublebuffer, " : "",
1509 				hw_ep->max_packet_sz_rx);
1510 		}
1511 		if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1512 			dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1513 	}
1514 
1515 	return 0;
1516 }
1517 
1518 /*-------------------------------------------------------------------------*/
1519 
1520 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
1521 	defined(CONFIG_ARCH_OMAP4)
1522 
generic_interrupt(int irq,void * __hci)1523 static irqreturn_t generic_interrupt(int irq, void *__hci)
1524 {
1525 	unsigned long	flags;
1526 	irqreturn_t	retval = IRQ_NONE;
1527 	struct musb	*musb = __hci;
1528 
1529 	spin_lock_irqsave(&musb->lock, flags);
1530 
1531 	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1532 	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1533 	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1534 
1535 	if (musb->int_usb || musb->int_tx || musb->int_rx)
1536 		retval = musb_interrupt(musb);
1537 
1538 	spin_unlock_irqrestore(&musb->lock, flags);
1539 
1540 	return retval;
1541 }
1542 
1543 #else
1544 #define generic_interrupt	NULL
1545 #endif
1546 
1547 /*
1548  * handle all the irqs defined by the HDRC core. for now we expect:  other
1549  * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1550  * will be assigned, and the irq will already have been acked.
1551  *
1552  * called in irq context with spinlock held, irqs blocked
1553  */
musb_interrupt(struct musb * musb)1554 irqreturn_t musb_interrupt(struct musb *musb)
1555 {
1556 	irqreturn_t	retval = IRQ_NONE;
1557 	u8		devctl, power;
1558 	int		ep_num;
1559 	u32		reg;
1560 
1561 	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1562 	power = musb_readb(musb->mregs, MUSB_POWER);
1563 
1564 	dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1565 		(devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1566 		musb->int_usb, musb->int_tx, musb->int_rx);
1567 
1568 	/* the core can interrupt us for multiple reasons; docs have
1569 	 * a generic interrupt flowchart to follow
1570 	 */
1571 	if (musb->int_usb)
1572 		retval |= musb_stage0_irq(musb, musb->int_usb,
1573 				devctl, power);
1574 
1575 	/* "stage 1" is handling endpoint irqs */
1576 
1577 	/* handle endpoint 0 first */
1578 	if (musb->int_tx & 1) {
1579 		if (devctl & MUSB_DEVCTL_HM) {
1580 			if (is_host_capable())
1581 				retval |= musb_h_ep0_irq(musb);
1582 		} else {
1583 			if (is_peripheral_capable())
1584 				retval |= musb_g_ep0_irq(musb);
1585 		}
1586 	}
1587 
1588 	/* RX on endpoints 1-15 */
1589 	reg = musb->int_rx >> 1;
1590 	ep_num = 1;
1591 	while (reg) {
1592 		if (reg & 1) {
1593 			/* musb_ep_select(musb->mregs, ep_num); */
1594 			/* REVISIT just retval = ep->rx_irq(...) */
1595 			retval = IRQ_HANDLED;
1596 			if (devctl & MUSB_DEVCTL_HM) {
1597 				if (is_host_capable())
1598 					musb_host_rx(musb, ep_num);
1599 			} else {
1600 				if (is_peripheral_capable())
1601 					musb_g_rx(musb, ep_num);
1602 			}
1603 		}
1604 
1605 		reg >>= 1;
1606 		ep_num++;
1607 	}
1608 
1609 	/* TX on endpoints 1-15 */
1610 	reg = musb->int_tx >> 1;
1611 	ep_num = 1;
1612 	while (reg) {
1613 		if (reg & 1) {
1614 			/* musb_ep_select(musb->mregs, ep_num); */
1615 			/* REVISIT just retval |= ep->tx_irq(...) */
1616 			retval = IRQ_HANDLED;
1617 			if (devctl & MUSB_DEVCTL_HM) {
1618 				if (is_host_capable())
1619 					musb_host_tx(musb, ep_num);
1620 			} else {
1621 				if (is_peripheral_capable())
1622 					musb_g_tx(musb, ep_num);
1623 			}
1624 		}
1625 		reg >>= 1;
1626 		ep_num++;
1627 	}
1628 
1629 	return retval;
1630 }
1631 EXPORT_SYMBOL_GPL(musb_interrupt);
1632 
1633 #ifndef CONFIG_USB_MUSB_PIO_ONLY
1634 static bool __devinitdata use_dma = 1;
1635 
1636 /* "modprobe ... use_dma=0" etc */
1637 module_param(use_dma, bool, 0);
1638 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1639 
musb_dma_completion(struct musb * musb,u8 epnum,u8 transmit)1640 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1641 {
1642 	u8	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1643 
1644 	/* called with controller lock already held */
1645 
1646 	if (!epnum) {
1647 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1648 		if (!is_cppi_enabled()) {
1649 			/* endpoint 0 */
1650 			if (devctl & MUSB_DEVCTL_HM)
1651 				musb_h_ep0_irq(musb);
1652 			else
1653 				musb_g_ep0_irq(musb);
1654 		}
1655 #endif
1656 	} else {
1657 		/* endpoints 1..15 */
1658 		if (transmit) {
1659 			if (devctl & MUSB_DEVCTL_HM) {
1660 				if (is_host_capable())
1661 					musb_host_tx(musb, epnum);
1662 			} else {
1663 				if (is_peripheral_capable())
1664 					musb_g_tx(musb, epnum);
1665 			}
1666 		} else {
1667 			/* receive */
1668 			if (devctl & MUSB_DEVCTL_HM) {
1669 				if (is_host_capable())
1670 					musb_host_rx(musb, epnum);
1671 			} else {
1672 				if (is_peripheral_capable())
1673 					musb_g_rx(musb, epnum);
1674 			}
1675 		}
1676 	}
1677 }
1678 EXPORT_SYMBOL_GPL(musb_dma_completion);
1679 
1680 #else
1681 #define use_dma			0
1682 #endif
1683 
1684 /*-------------------------------------------------------------------------*/
1685 
1686 #ifdef CONFIG_SYSFS
1687 
1688 static ssize_t
musb_mode_show(struct device * dev,struct device_attribute * attr,char * buf)1689 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1690 {
1691 	struct musb *musb = dev_to_musb(dev);
1692 	unsigned long flags;
1693 	int ret = -EINVAL;
1694 
1695 	spin_lock_irqsave(&musb->lock, flags);
1696 	ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1697 	spin_unlock_irqrestore(&musb->lock, flags);
1698 
1699 	return ret;
1700 }
1701 
1702 static ssize_t
musb_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t n)1703 musb_mode_store(struct device *dev, struct device_attribute *attr,
1704 		const char *buf, size_t n)
1705 {
1706 	struct musb	*musb = dev_to_musb(dev);
1707 	unsigned long	flags;
1708 	int		status;
1709 
1710 	spin_lock_irqsave(&musb->lock, flags);
1711 	if (sysfs_streq(buf, "host"))
1712 		status = musb_platform_set_mode(musb, MUSB_HOST);
1713 	else if (sysfs_streq(buf, "peripheral"))
1714 		status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1715 	else if (sysfs_streq(buf, "otg"))
1716 		status = musb_platform_set_mode(musb, MUSB_OTG);
1717 	else
1718 		status = -EINVAL;
1719 	spin_unlock_irqrestore(&musb->lock, flags);
1720 
1721 	return (status == 0) ? n : status;
1722 }
1723 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1724 
1725 static ssize_t
musb_vbus_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t n)1726 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1727 		const char *buf, size_t n)
1728 {
1729 	struct musb	*musb = dev_to_musb(dev);
1730 	unsigned long	flags;
1731 	unsigned long	val;
1732 
1733 	if (sscanf(buf, "%lu", &val) < 1) {
1734 		dev_err(dev, "Invalid VBUS timeout ms value\n");
1735 		return -EINVAL;
1736 	}
1737 
1738 	spin_lock_irqsave(&musb->lock, flags);
1739 	/* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1740 	musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1741 	if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1742 		musb->is_active = 0;
1743 	musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1744 	spin_unlock_irqrestore(&musb->lock, flags);
1745 
1746 	return n;
1747 }
1748 
1749 static ssize_t
musb_vbus_show(struct device * dev,struct device_attribute * attr,char * buf)1750 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1751 {
1752 	struct musb	*musb = dev_to_musb(dev);
1753 	unsigned long	flags;
1754 	unsigned long	val;
1755 	int		vbus;
1756 
1757 	spin_lock_irqsave(&musb->lock, flags);
1758 	val = musb->a_wait_bcon;
1759 	/* FIXME get_vbus_status() is normally #defined as false...
1760 	 * and is effectively TUSB-specific.
1761 	 */
1762 	vbus = musb_platform_get_vbus_status(musb);
1763 	spin_unlock_irqrestore(&musb->lock, flags);
1764 
1765 	return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1766 			vbus ? "on" : "off", val);
1767 }
1768 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1769 
1770 /* Gadget drivers can't know that a host is connected so they might want
1771  * to start SRP, but users can.  This allows userspace to trigger SRP.
1772  */
1773 static ssize_t
musb_srp_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t n)1774 musb_srp_store(struct device *dev, struct device_attribute *attr,
1775 		const char *buf, size_t n)
1776 {
1777 	struct musb	*musb = dev_to_musb(dev);
1778 	unsigned short	srp;
1779 
1780 	if (sscanf(buf, "%hu", &srp) != 1
1781 			|| (srp != 1)) {
1782 		dev_err(dev, "SRP: Value must be 1\n");
1783 		return -EINVAL;
1784 	}
1785 
1786 	if (srp == 1)
1787 		musb_g_wakeup(musb);
1788 
1789 	return n;
1790 }
1791 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1792 
1793 static struct attribute *musb_attributes[] = {
1794 	&dev_attr_mode.attr,
1795 	&dev_attr_vbus.attr,
1796 	&dev_attr_srp.attr,
1797 	NULL
1798 };
1799 
1800 static const struct attribute_group musb_attr_group = {
1801 	.attrs = musb_attributes,
1802 };
1803 
1804 #endif	/* sysfs */
1805 
1806 #ifndef __UBOOT__
1807 /* Only used to provide driver mode change events */
musb_irq_work(struct work_struct * data)1808 static void musb_irq_work(struct work_struct *data)
1809 {
1810 	struct musb *musb = container_of(data, struct musb, irq_work);
1811 	static int old_state;
1812 
1813 	if (musb->xceiv->state != old_state) {
1814 		old_state = musb->xceiv->state;
1815 		sysfs_notify(&musb->controller->kobj, NULL, "mode");
1816 	}
1817 }
1818 #endif
1819 
1820 /* --------------------------------------------------------------------------
1821  * Init support
1822  */
1823 
1824 static struct musb *__devinit
allocate_instance(struct device * dev,struct musb_hdrc_config * config,void __iomem * mbase)1825 allocate_instance(struct device *dev,
1826 		struct musb_hdrc_config *config, void __iomem *mbase)
1827 {
1828 	struct musb		*musb;
1829 	struct musb_hw_ep	*ep;
1830 	int			epnum;
1831 #ifndef __UBOOT__
1832 	struct usb_hcd	*hcd;
1833 
1834 	hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1835 	if (!hcd)
1836 		return NULL;
1837 	/* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1838 
1839 	musb = hcd_to_musb(hcd);
1840 #else
1841 	musb = calloc(1, sizeof(*musb));
1842 	if (!musb)
1843 		return NULL;
1844 #endif
1845 	INIT_LIST_HEAD(&musb->control);
1846 	INIT_LIST_HEAD(&musb->in_bulk);
1847 	INIT_LIST_HEAD(&musb->out_bulk);
1848 
1849 #ifndef __UBOOT__
1850 	hcd->uses_new_polling = 1;
1851 	hcd->has_tt = 1;
1852 #endif
1853 
1854 	musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1855 	musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1856 	dev_set_drvdata(dev, musb);
1857 	musb->mregs = mbase;
1858 	musb->ctrl_base = mbase;
1859 	musb->nIrq = -ENODEV;
1860 	musb->config = config;
1861 	BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1862 	for (epnum = 0, ep = musb->endpoints;
1863 			epnum < musb->config->num_eps;
1864 			epnum++, ep++) {
1865 		ep->musb = musb;
1866 		ep->epnum = epnum;
1867 	}
1868 
1869 	musb->controller = dev;
1870 
1871 	return musb;
1872 }
1873 
musb_free(struct musb * musb)1874 static void musb_free(struct musb *musb)
1875 {
1876 	/* this has multiple entry modes. it handles fault cleanup after
1877 	 * probe(), where things may be partially set up, as well as rmmod
1878 	 * cleanup after everything's been de-activated.
1879 	 */
1880 
1881 #ifdef CONFIG_SYSFS
1882 	sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1883 #endif
1884 
1885 	if (musb->nIrq >= 0) {
1886 		if (musb->irq_wake)
1887 			disable_irq_wake(musb->nIrq);
1888 		free_irq(musb->nIrq, musb);
1889 	}
1890 	if (is_dma_capable() && musb->dma_controller) {
1891 		struct dma_controller	*c = musb->dma_controller;
1892 
1893 		(void) c->stop(c);
1894 		dma_controller_destroy(c);
1895 	}
1896 
1897 	kfree(musb);
1898 }
1899 
1900 /*
1901  * Perform generic per-controller initialization.
1902  *
1903  * @pDevice: the controller (already clocked, etc)
1904  * @nIrq: irq
1905  * @mregs: virtual address of controller registers,
1906  *	not yet corrected for platform-specific offsets
1907  */
1908 #ifndef __UBOOT__
1909 static int __devinit
musb_init_controller(struct device * dev,int nIrq,void __iomem * ctrl)1910 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1911 #else
1912 struct musb *
1913 musb_init_controller(struct musb_hdrc_platform_data *plat, struct device *dev,
1914 			     void *ctrl)
1915 #endif
1916 {
1917 	int			status;
1918 	struct musb		*musb;
1919 #ifndef __UBOOT__
1920 	struct musb_hdrc_platform_data *plat = dev->platform_data;
1921 #else
1922 	int nIrq = 0;
1923 #endif
1924 
1925 	/* The driver might handle more features than the board; OK.
1926 	 * Fail when the board needs a feature that's not enabled.
1927 	 */
1928 	if (!plat) {
1929 		dev_dbg(dev, "no platform_data?\n");
1930 		status = -ENODEV;
1931 		goto fail0;
1932 	}
1933 
1934 	/* allocate */
1935 	musb = allocate_instance(dev, plat->config, ctrl);
1936 	if (!musb) {
1937 		status = -ENOMEM;
1938 		goto fail0;
1939 	}
1940 
1941 	pm_runtime_use_autosuspend(musb->controller);
1942 	pm_runtime_set_autosuspend_delay(musb->controller, 200);
1943 	pm_runtime_enable(musb->controller);
1944 
1945 	spin_lock_init(&musb->lock);
1946 	musb->board_mode = plat->mode;
1947 	musb->board_set_power = plat->set_power;
1948 	musb->min_power = plat->min_power;
1949 	musb->ops = plat->platform_ops;
1950 
1951 	/* The musb_platform_init() call:
1952 	 *   - adjusts musb->mregs and musb->isr if needed,
1953 	 *   - may initialize an integrated tranceiver
1954 	 *   - initializes musb->xceiv, usually by otg_get_phy()
1955 	 *   - stops powering VBUS
1956 	 *
1957 	 * There are various transceiver configurations.  Blackfin,
1958 	 * DaVinci, TUSB60x0, and others integrate them.  OMAP3 uses
1959 	 * external/discrete ones in various flavors (twl4030 family,
1960 	 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1961 	 */
1962 	musb->isr = generic_interrupt;
1963 	status = musb_platform_init(musb);
1964 	if (status < 0)
1965 		goto fail1;
1966 
1967 	if (!musb->isr) {
1968 		status = -ENODEV;
1969 		goto fail2;
1970 	}
1971 
1972 #ifndef __UBOOT__
1973 	if (!musb->xceiv->io_ops) {
1974 		musb->xceiv->io_dev = musb->controller;
1975 		musb->xceiv->io_priv = musb->mregs;
1976 		musb->xceiv->io_ops = &musb_ulpi_access;
1977 	}
1978 #endif
1979 
1980 	pm_runtime_get_sync(musb->controller);
1981 
1982 #ifndef CONFIG_USB_MUSB_PIO_ONLY
1983 	if (use_dma && dev->dma_mask) {
1984 		struct dma_controller	*c;
1985 
1986 		c = dma_controller_create(musb, musb->mregs);
1987 		musb->dma_controller = c;
1988 		if (c)
1989 			(void) c->start(c);
1990 	}
1991 #endif
1992 #ifndef __UBOOT__
1993 	/* ideally this would be abstracted in platform setup */
1994 	if (!is_dma_capable() || !musb->dma_controller)
1995 		dev->dma_mask = NULL;
1996 #endif
1997 
1998 	/* be sure interrupts are disabled before connecting ISR */
1999 	musb_platform_disable(musb);
2000 	musb_generic_disable(musb);
2001 
2002 	/* setup musb parts of the core (especially endpoints) */
2003 	status = musb_core_init(plat->config->multipoint
2004 			? MUSB_CONTROLLER_MHDRC
2005 			: MUSB_CONTROLLER_HDRC, musb);
2006 	if (status < 0)
2007 		goto fail3;
2008 
2009 	setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2010 
2011 	/* Init IRQ workqueue before request_irq */
2012 	INIT_WORK(&musb->irq_work, musb_irq_work);
2013 
2014 	/* attach to the IRQ */
2015 	if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2016 		dev_err(dev, "request_irq %d failed!\n", nIrq);
2017 		status = -ENODEV;
2018 		goto fail3;
2019 	}
2020 	musb->nIrq = nIrq;
2021 /* FIXME this handles wakeup irqs wrong */
2022 	if (enable_irq_wake(nIrq) == 0) {
2023 		musb->irq_wake = 1;
2024 		device_init_wakeup(dev, 1);
2025 	} else {
2026 		musb->irq_wake = 0;
2027 	}
2028 
2029 #ifndef __UBOOT__
2030 	/* host side needs more setup */
2031 	if (is_host_enabled(musb)) {
2032 		struct usb_hcd	*hcd = musb_to_hcd(musb);
2033 
2034 		otg_set_host(musb->xceiv->otg, &hcd->self);
2035 
2036 		if (is_otg_enabled(musb))
2037 			hcd->self.otg_port = 1;
2038 		musb->xceiv->otg->host = &hcd->self;
2039 		hcd->power_budget = 2 * (plat->power ? : 250);
2040 
2041 		/* program PHY to use external vBus if required */
2042 		if (plat->extvbus) {
2043 			u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2044 			busctl |= MUSB_ULPI_USE_EXTVBUS;
2045 			musb_write_ulpi_buscontrol(musb->mregs, busctl);
2046 		}
2047 	}
2048 #endif
2049 
2050 	/* For the host-only role, we can activate right away.
2051 	 * (We expect the ID pin to be forcibly grounded!!)
2052 	 * Otherwise, wait till the gadget driver hooks up.
2053 	 */
2054 	if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2055 		struct usb_hcd	*hcd = musb_to_hcd(musb);
2056 
2057 		MUSB_HST_MODE(musb);
2058 #ifndef __UBOOT__
2059 		musb->xceiv->otg->default_a = 1;
2060 		musb->xceiv->state = OTG_STATE_A_IDLE;
2061 
2062 		status = usb_add_hcd(musb_to_hcd(musb), 0, 0);
2063 
2064 		hcd->self.uses_pio_for_control = 1;
2065 		dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
2066 			"HOST", status,
2067 			musb_readb(musb->mregs, MUSB_DEVCTL),
2068 			(musb_readb(musb->mregs, MUSB_DEVCTL)
2069 					& MUSB_DEVCTL_BDEVICE
2070 				? 'B' : 'A'));
2071 #endif
2072 
2073 	} else /* peripheral is enabled */ {
2074 		MUSB_DEV_MODE(musb);
2075 #ifndef __UBOOT__
2076 		musb->xceiv->otg->default_a = 0;
2077 		musb->xceiv->state = OTG_STATE_B_IDLE;
2078 #endif
2079 
2080 		if (is_peripheral_capable())
2081 			status = musb_gadget_setup(musb);
2082 
2083 #ifndef __UBOOT__
2084 		dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2085 			is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2086 			status,
2087 			musb_readb(musb->mregs, MUSB_DEVCTL));
2088 #endif
2089 
2090 	}
2091 	if (status < 0)
2092 		goto fail3;
2093 
2094 	status = musb_init_debugfs(musb);
2095 	if (status < 0)
2096 		goto fail4;
2097 
2098 #ifdef CONFIG_SYSFS
2099 	status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2100 	if (status)
2101 		goto fail5;
2102 #endif
2103 
2104 	pm_runtime_put(musb->controller);
2105 
2106 	pr_debug("USB %s mode controller at %p using %s, IRQ %d\n",
2107 			({char *s;
2108 			 switch (musb->board_mode) {
2109 			 case MUSB_HOST:		s = "Host"; break;
2110 			 case MUSB_PERIPHERAL:	s = "Peripheral"; break;
2111 			 default:		s = "OTG"; break;
2112 			 }; s; }),
2113 			ctrl,
2114 			(is_dma_capable() && musb->dma_controller)
2115 			? "DMA" : "PIO",
2116 			musb->nIrq);
2117 
2118 #ifndef __UBOOT__
2119 	return 0;
2120 #else
2121 	return status == 0 ? musb : NULL;
2122 #endif
2123 
2124 fail5:
2125 	musb_exit_debugfs(musb);
2126 
2127 fail4:
2128 #ifndef __UBOOT__
2129 	if (!is_otg_enabled(musb) && is_host_enabled(musb))
2130 		usb_remove_hcd(musb_to_hcd(musb));
2131 	else
2132 #endif
2133 		musb_gadget_cleanup(musb);
2134 
2135 fail3:
2136 	pm_runtime_put_sync(musb->controller);
2137 
2138 fail2:
2139 	if (musb->irq_wake)
2140 		device_init_wakeup(dev, 0);
2141 	musb_platform_exit(musb);
2142 
2143 fail1:
2144 	dev_err(musb->controller,
2145 		"musb_init_controller failed with status %d\n", status);
2146 
2147 	musb_free(musb);
2148 
2149 fail0:
2150 
2151 #ifndef __UBOOT__
2152 	return status;
2153 #else
2154 	return status == 0 ? musb : NULL;
2155 #endif
2156 
2157 }
2158 
2159 /*-------------------------------------------------------------------------*/
2160 
2161 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2162  * bridge to a platform device; this driver then suffices.
2163  */
2164 
2165 #ifndef CONFIG_USB_MUSB_PIO_ONLY
2166 static u64	*orig_dma_mask;
2167 #endif
2168 
2169 #ifndef __UBOOT__
musb_probe(struct platform_device * pdev)2170 static int __devinit musb_probe(struct platform_device *pdev)
2171 {
2172 	struct device	*dev = &pdev->dev;
2173 	int		irq = platform_get_irq_byname(pdev, "mc");
2174 	int		status;
2175 	struct resource	*iomem;
2176 	void __iomem	*base;
2177 
2178 	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2179 	if (!iomem || irq <= 0)
2180 		return -ENODEV;
2181 
2182 	base = ioremap(iomem->start, resource_size(iomem));
2183 	if (!base) {
2184 		dev_err(dev, "ioremap failed\n");
2185 		return -ENOMEM;
2186 	}
2187 
2188 #ifndef CONFIG_USB_MUSB_PIO_ONLY
2189 	/* clobbered by use_dma=n */
2190 	orig_dma_mask = dev->dma_mask;
2191 #endif
2192 	status = musb_init_controller(dev, irq, base);
2193 	if (status < 0)
2194 		iounmap(base);
2195 
2196 	return status;
2197 }
2198 
musb_remove(struct platform_device * pdev)2199 static int __devexit musb_remove(struct platform_device *pdev)
2200 {
2201 	struct musb	*musb = dev_to_musb(&pdev->dev);
2202 	void __iomem	*ctrl_base = musb->ctrl_base;
2203 
2204 	/* this gets called on rmmod.
2205 	 *  - Host mode: host may still be active
2206 	 *  - Peripheral mode: peripheral is deactivated (or never-activated)
2207 	 *  - OTG mode: both roles are deactivated (or never-activated)
2208 	 */
2209 	musb_exit_debugfs(musb);
2210 	musb_shutdown(pdev);
2211 
2212 	musb_free(musb);
2213 	iounmap(ctrl_base);
2214 	device_init_wakeup(&pdev->dev, 0);
2215 #ifndef CONFIG_USB_MUSB_PIO_ONLY
2216 	pdev->dev.dma_mask = orig_dma_mask;
2217 #endif
2218 	return 0;
2219 }
2220 
2221 #ifdef	CONFIG_PM
2222 
musb_save_context(struct musb * musb)2223 static void musb_save_context(struct musb *musb)
2224 {
2225 	int i;
2226 	void __iomem *musb_base = musb->mregs;
2227 	void __iomem *epio;
2228 
2229 	if (is_host_enabled(musb)) {
2230 		musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2231 		musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2232 		musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2233 	}
2234 	musb->context.power = musb_readb(musb_base, MUSB_POWER);
2235 	musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2236 	musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2237 	musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2238 	musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2239 	musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2240 
2241 	for (i = 0; i < musb->config->num_eps; ++i) {
2242 		struct musb_hw_ep	*hw_ep;
2243 
2244 		hw_ep = &musb->endpoints[i];
2245 		if (!hw_ep)
2246 			continue;
2247 
2248 		epio = hw_ep->regs;
2249 		if (!epio)
2250 			continue;
2251 
2252 		musb_writeb(musb_base, MUSB_INDEX, i);
2253 		musb->context.index_regs[i].txmaxp =
2254 			musb_readw(epio, MUSB_TXMAXP);
2255 		musb->context.index_regs[i].txcsr =
2256 			musb_readw(epio, MUSB_TXCSR);
2257 		musb->context.index_regs[i].rxmaxp =
2258 			musb_readw(epio, MUSB_RXMAXP);
2259 		musb->context.index_regs[i].rxcsr =
2260 			musb_readw(epio, MUSB_RXCSR);
2261 
2262 		if (musb->dyn_fifo) {
2263 			musb->context.index_regs[i].txfifoadd =
2264 					musb_read_txfifoadd(musb_base);
2265 			musb->context.index_regs[i].rxfifoadd =
2266 					musb_read_rxfifoadd(musb_base);
2267 			musb->context.index_regs[i].txfifosz =
2268 					musb_read_txfifosz(musb_base);
2269 			musb->context.index_regs[i].rxfifosz =
2270 					musb_read_rxfifosz(musb_base);
2271 		}
2272 		if (is_host_enabled(musb)) {
2273 			musb->context.index_regs[i].txtype =
2274 				musb_readb(epio, MUSB_TXTYPE);
2275 			musb->context.index_regs[i].txinterval =
2276 				musb_readb(epio, MUSB_TXINTERVAL);
2277 			musb->context.index_regs[i].rxtype =
2278 				musb_readb(epio, MUSB_RXTYPE);
2279 			musb->context.index_regs[i].rxinterval =
2280 				musb_readb(epio, MUSB_RXINTERVAL);
2281 
2282 			musb->context.index_regs[i].txfunaddr =
2283 				musb_read_txfunaddr(musb_base, i);
2284 			musb->context.index_regs[i].txhubaddr =
2285 				musb_read_txhubaddr(musb_base, i);
2286 			musb->context.index_regs[i].txhubport =
2287 				musb_read_txhubport(musb_base, i);
2288 
2289 			musb->context.index_regs[i].rxfunaddr =
2290 				musb_read_rxfunaddr(musb_base, i);
2291 			musb->context.index_regs[i].rxhubaddr =
2292 				musb_read_rxhubaddr(musb_base, i);
2293 			musb->context.index_regs[i].rxhubport =
2294 				musb_read_rxhubport(musb_base, i);
2295 		}
2296 	}
2297 }
2298 
musb_restore_context(struct musb * musb)2299 static void musb_restore_context(struct musb *musb)
2300 {
2301 	int i;
2302 	void __iomem *musb_base = musb->mregs;
2303 	void __iomem *ep_target_regs;
2304 	void __iomem *epio;
2305 
2306 	if (is_host_enabled(musb)) {
2307 		musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2308 		musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2309 		musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2310 	}
2311 	musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2312 	musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2313 	musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2314 	musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2315 	musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2316 
2317 	for (i = 0; i < musb->config->num_eps; ++i) {
2318 		struct musb_hw_ep	*hw_ep;
2319 
2320 		hw_ep = &musb->endpoints[i];
2321 		if (!hw_ep)
2322 			continue;
2323 
2324 		epio = hw_ep->regs;
2325 		if (!epio)
2326 			continue;
2327 
2328 		musb_writeb(musb_base, MUSB_INDEX, i);
2329 		musb_writew(epio, MUSB_TXMAXP,
2330 			musb->context.index_regs[i].txmaxp);
2331 		musb_writew(epio, MUSB_TXCSR,
2332 			musb->context.index_regs[i].txcsr);
2333 		musb_writew(epio, MUSB_RXMAXP,
2334 			musb->context.index_regs[i].rxmaxp);
2335 		musb_writew(epio, MUSB_RXCSR,
2336 			musb->context.index_regs[i].rxcsr);
2337 
2338 		if (musb->dyn_fifo) {
2339 			musb_write_txfifosz(musb_base,
2340 				musb->context.index_regs[i].txfifosz);
2341 			musb_write_rxfifosz(musb_base,
2342 				musb->context.index_regs[i].rxfifosz);
2343 			musb_write_txfifoadd(musb_base,
2344 				musb->context.index_regs[i].txfifoadd);
2345 			musb_write_rxfifoadd(musb_base,
2346 				musb->context.index_regs[i].rxfifoadd);
2347 		}
2348 
2349 		if (is_host_enabled(musb)) {
2350 			musb_writeb(epio, MUSB_TXTYPE,
2351 				musb->context.index_regs[i].txtype);
2352 			musb_writeb(epio, MUSB_TXINTERVAL,
2353 				musb->context.index_regs[i].txinterval);
2354 			musb_writeb(epio, MUSB_RXTYPE,
2355 				musb->context.index_regs[i].rxtype);
2356 			musb_writeb(epio, MUSB_RXINTERVAL,
2357 
2358 			musb->context.index_regs[i].rxinterval);
2359 			musb_write_txfunaddr(musb_base, i,
2360 				musb->context.index_regs[i].txfunaddr);
2361 			musb_write_txhubaddr(musb_base, i,
2362 				musb->context.index_regs[i].txhubaddr);
2363 			musb_write_txhubport(musb_base, i,
2364 				musb->context.index_regs[i].txhubport);
2365 
2366 			ep_target_regs =
2367 				musb_read_target_reg_base(i, musb_base);
2368 
2369 			musb_write_rxfunaddr(ep_target_regs,
2370 				musb->context.index_regs[i].rxfunaddr);
2371 			musb_write_rxhubaddr(ep_target_regs,
2372 				musb->context.index_regs[i].rxhubaddr);
2373 			musb_write_rxhubport(ep_target_regs,
2374 				musb->context.index_regs[i].rxhubport);
2375 		}
2376 	}
2377 	musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2378 }
2379 
musb_suspend(struct device * dev)2380 static int musb_suspend(struct device *dev)
2381 {
2382 	struct musb	*musb = dev_to_musb(dev);
2383 	unsigned long	flags;
2384 
2385 	spin_lock_irqsave(&musb->lock, flags);
2386 
2387 	if (is_peripheral_active(musb)) {
2388 		/* FIXME force disconnect unless we know USB will wake
2389 		 * the system up quickly enough to respond ...
2390 		 */
2391 	} else if (is_host_active(musb)) {
2392 		/* we know all the children are suspended; sometimes
2393 		 * they will even be wakeup-enabled.
2394 		 */
2395 	}
2396 
2397 	spin_unlock_irqrestore(&musb->lock, flags);
2398 	return 0;
2399 }
2400 
musb_resume_noirq(struct device * dev)2401 static int musb_resume_noirq(struct device *dev)
2402 {
2403 	/* for static cmos like DaVinci, register values were preserved
2404 	 * unless for some reason the whole soc powered down or the USB
2405 	 * module got reset through the PSC (vs just being disabled).
2406 	 */
2407 	return 0;
2408 }
2409 
musb_runtime_suspend(struct device * dev)2410 static int musb_runtime_suspend(struct device *dev)
2411 {
2412 	struct musb	*musb = dev_to_musb(dev);
2413 
2414 	musb_save_context(musb);
2415 
2416 	return 0;
2417 }
2418 
musb_runtime_resume(struct device * dev)2419 static int musb_runtime_resume(struct device *dev)
2420 {
2421 	struct musb	*musb = dev_to_musb(dev);
2422 	static int	first = 1;
2423 
2424 	/*
2425 	 * When pm_runtime_get_sync called for the first time in driver
2426 	 * init,  some of the structure is still not initialized which is
2427 	 * used in restore function. But clock needs to be
2428 	 * enabled before any register access, so
2429 	 * pm_runtime_get_sync has to be called.
2430 	 * Also context restore without save does not make
2431 	 * any sense
2432 	 */
2433 	if (!first)
2434 		musb_restore_context(musb);
2435 	first = 0;
2436 
2437 	return 0;
2438 }
2439 
2440 static const struct dev_pm_ops musb_dev_pm_ops = {
2441 	.suspend	= musb_suspend,
2442 	.resume_noirq	= musb_resume_noirq,
2443 	.runtime_suspend = musb_runtime_suspend,
2444 	.runtime_resume = musb_runtime_resume,
2445 };
2446 
2447 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2448 #else
2449 #define	MUSB_DEV_PM_OPS	NULL
2450 #endif
2451 
2452 static struct platform_driver musb_driver = {
2453 	.driver = {
2454 		.name		= (char *)musb_driver_name,
2455 		.bus		= &platform_bus_type,
2456 		.owner		= THIS_MODULE,
2457 		.pm		= MUSB_DEV_PM_OPS,
2458 	},
2459 	.probe		= musb_probe,
2460 	.remove		= __devexit_p(musb_remove),
2461 	.shutdown	= musb_shutdown,
2462 };
2463 
2464 /*-------------------------------------------------------------------------*/
2465 
musb_init(void)2466 static int __init musb_init(void)
2467 {
2468 	if (usb_disabled())
2469 		return 0;
2470 
2471 	pr_info("%s: version " MUSB_VERSION ", "
2472 		"?dma?"
2473 		", "
2474 		"otg (peripheral+host)",
2475 		musb_driver_name);
2476 	return platform_driver_register(&musb_driver);
2477 }
2478 module_init(musb_init);
2479 
musb_cleanup(void)2480 static void __exit musb_cleanup(void)
2481 {
2482 	platform_driver_unregister(&musb_driver);
2483 }
2484 module_exit(musb_cleanup);
2485 #endif
2486