1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _DDR3_TRAINING_IP_PRV_IF_H 7 #define _DDR3_TRAINING_IP_PRV_IF_H 8 9 #include "ddr3_training_ip.h" 10 #include "ddr3_training_ip_flow.h" 11 #include "ddr3_training_ip_bist.h" 12 13 enum hws_static_config_type { 14 WRITE_LEVELING_STATIC, 15 READ_LEVELING_STATIC 16 }; 17 18 struct ddr3_device_info { 19 u32 device_id; 20 u32 ck_delay; 21 }; 22 23 typedef int (*HWS_TIP_DUNIT_MUX_SELECT_FUNC_PTR)(u8 dev_num, int enable); 24 typedef int (*HWS_TIP_DUNIT_REG_READ_FUNC_PTR)( 25 u8 dev_num, enum hws_access_type interface_access, u32 if_id, 26 u32 offset, u32 *data, u32 mask); 27 typedef int (*HWS_TIP_DUNIT_REG_WRITE_FUNC_PTR)( 28 u8 dev_num, enum hws_access_type interface_access, u32 if_id, 29 u32 offset, u32 data, u32 mask); 30 typedef int (*HWS_TIP_GET_FREQ_CONFIG_INFO)( 31 u8 dev_num, enum hws_ddr_freq freq, 32 struct hws_tip_freq_config_info *freq_config_info); 33 typedef int (*HWS_TIP_GET_DEVICE_INFO)( 34 u8 dev_num, struct ddr3_device_info *info_ptr); 35 typedef int (*HWS_GET_CS_CONFIG_FUNC_PTR)( 36 u8 dev_num, u32 cs_mask, struct hws_cs_config_info *cs_info); 37 typedef int (*HWS_SET_FREQ_DIVIDER_FUNC_PTR)( 38 u8 dev_num, u32 if_id, enum hws_ddr_freq freq); 39 typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum hws_ddr_freq *freq); 40 typedef int (*HWS_TRAINING_IP_IF_WRITE_FUNC_PTR)( 41 u32 dev_num, enum hws_access_type access_type, u32 dunit_id, 42 u32 reg_addr, u32 data, u32 mask); 43 typedef int (*HWS_TRAINING_IP_IF_READ_FUNC_PTR)( 44 u32 dev_num, enum hws_access_type access_type, u32 dunit_id, 45 u32 reg_addr, u32 *data, u32 mask); 46 typedef int (*HWS_TRAINING_IP_BUS_WRITE_FUNC_PTR)( 47 u32 dev_num, enum hws_access_type dunit_access_type, u32 if_id, 48 enum hws_access_type phy_access_type, u32 phy_id, 49 enum hws_ddr_phy phy_type, u32 reg_addr, u32 data); 50 typedef int (*HWS_TRAINING_IP_BUS_READ_FUNC_PTR)( 51 u32 dev_num, u32 if_id, enum hws_access_type phy_access_type, 52 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr, u32 *data); 53 typedef int (*HWS_TRAINING_IP_ALGO_RUN_FUNC_PTR)( 54 u32 dev_num, enum hws_algo_type algo_type); 55 typedef int (*HWS_TRAINING_IP_SET_FREQ_FUNC_PTR)( 56 u32 dev_num, enum hws_access_type access_type, u32 if_id, 57 enum hws_ddr_freq frequency); 58 typedef int (*HWS_TRAINING_IP_INIT_CONTROLLER_FUNC_PTR)( 59 u32 dev_num, struct init_cntr_param *init_cntr_prm); 60 typedef int (*HWS_TRAINING_IP_PBS_RX_FUNC_PTR)(u32 dev_num); 61 typedef int (*HWS_TRAINING_IP_PBS_TX_FUNC_PTR)(u32 dev_num); 62 typedef int (*HWS_TRAINING_IP_SELECT_CONTROLLER_FUNC_PTR)( 63 u32 dev_num, int enable); 64 typedef int (*HWS_TRAINING_IP_TOPOLOGY_MAP_LOAD_FUNC_PTR)( 65 u32 dev_num, struct mv_ddr_topology_map *tm); 66 typedef int (*HWS_TRAINING_IP_STATIC_CONFIG_FUNC_PTR)( 67 u32 dev_num, enum hws_ddr_freq frequency, 68 enum hws_static_config_type static_config_type, u32 if_id); 69 typedef int (*HWS_TRAINING_IP_EXTERNAL_READ_PTR)( 70 u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data); 71 typedef int (*HWS_TRAINING_IP_EXTERNAL_WRITE_PTR)( 72 u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data); 73 typedef int (*HWS_TRAINING_IP_BIST_ACTIVATE)( 74 u32 dev_num, enum hws_pattern pattern, enum hws_access_type access_type, 75 u32 if_num, enum hws_dir direction, 76 enum hws_stress_jump addr_stress_jump, 77 enum hws_pattern_duration duration, 78 enum hws_bist_operation oper_type, u32 offset, u32 cs_num, 79 u32 pattern_addr_length); 80 typedef int (*HWS_TRAINING_IP_BIST_READ_RESULT)( 81 u32 dev_num, u32 if_id, struct bist_result *pst_bist_result); 82 typedef int (*HWS_TRAINING_IP_LOAD_TOPOLOGY)(u32 dev_num, u32 config_num); 83 typedef int (*HWS_TRAINING_IP_READ_LEVELING)(u32 dev_num, u32 config_num); 84 typedef int (*HWS_TRAINING_IP_WRITE_LEVELING)(u32 dev_num, u32 config_num); 85 typedef u32 (*HWS_TRAINING_IP_GET_TEMP)(u8 dev_num); 86 typedef u8 (*HWS_TRAINING_IP_GET_RATIO)(u32 freq); 87 88 struct hws_tip_config_func_db { 89 HWS_TIP_DUNIT_MUX_SELECT_FUNC_PTR tip_dunit_mux_select_func; 90 void (*mv_ddr_dunit_read)(u32 addr, u32 mask, u32 *data); 91 void (*mv_ddr_dunit_write)(u32 addr, u32 mask, u32 data); 92 HWS_TIP_GET_FREQ_CONFIG_INFO tip_get_freq_config_info_func; 93 HWS_TIP_GET_DEVICE_INFO tip_get_device_info_func; 94 HWS_SET_FREQ_DIVIDER_FUNC_PTR tip_set_freq_divider_func; 95 HWS_GET_CS_CONFIG_FUNC_PTR tip_get_cs_config_info; 96 HWS_TRAINING_IP_GET_TEMP tip_get_temperature; 97 HWS_TRAINING_IP_GET_RATIO tip_get_clock_ratio; 98 HWS_TRAINING_IP_EXTERNAL_READ_PTR tip_external_read; 99 HWS_TRAINING_IP_EXTERNAL_WRITE_PTR tip_external_write; 100 int (*mv_ddr_phy_read)(enum hws_access_type phy_access, 101 u32 phy, enum hws_ddr_phy phy_type, 102 u32 reg_addr, u32 *data); 103 int (*mv_ddr_phy_write)(enum hws_access_type phy_access, 104 u32 phy, enum hws_ddr_phy phy_type, 105 u32 reg_addr, u32 data, 106 enum hws_operation op_type); 107 }; 108 109 int ddr3_tip_init_config_func(u32 dev_num, 110 struct hws_tip_config_func_db *config_func); 111 int ddr3_tip_register_xsb_info(u32 dev_num, 112 struct hws_xsb_info *xsb_info_table); 113 enum hws_result *ddr3_tip_get_result_ptr(u32 stage); 114 int ddr3_set_freq_config_info(struct hws_tip_freq_config_info *table); 115 int print_device_info(u8 dev_num); 116 117 #endif /* _DDR3_TRAINING_IP_PRV_IF_H */ 118