1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <watchdog.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/clock.h>
12 #include <dm/platform_data/serial_mxc.h>
13 #include <serial.h>
14 #include <linux/compiler.h>
15
16 /* UART Control Register Bit Fields.*/
17 #define URXD_CHARRDY (1<<15)
18 #define URXD_ERR (1<<14)
19 #define URXD_OVRRUN (1<<13)
20 #define URXD_FRMERR (1<<12)
21 #define URXD_BRK (1<<11)
22 #define URXD_PRERR (1<<10)
23 #define URXD_RX_DATA (0xFF)
24 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
25 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
26 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
27 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
28 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
29 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
30 #define UCR1_IREN (1<<7) /* Infrared interface enable */
31 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
32 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
33 #define UCR1_SNDBRK (1<<4) /* Send break */
34 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
35 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
36 #define UCR1_DOZE (1<<1) /* Doze */
37 #define UCR1_UARTEN (1<<0) /* UART enabled */
38 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
39 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
40 #define UCR2_CTSC (1<<13) /* CTS pin control */
41 #define UCR2_CTS (1<<12) /* Clear to send */
42 #define UCR2_ESCEN (1<<11) /* Escape enable */
43 #define UCR2_PREN (1<<8) /* Parity enable */
44 #define UCR2_PROE (1<<7) /* Parity odd/even */
45 #define UCR2_STPB (1<<6) /* Stop */
46 #define UCR2_WS (1<<5) /* Word size */
47 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
48 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
49 #define UCR2_RXEN (1<<1) /* Receiver enabled */
50 #define UCR2_SRST (1<<0) /* SW reset */
51 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
52 #define UCR3_PARERREN (1<<12) /* Parity enable */
53 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
54 #define UCR3_DSR (1<<10) /* Data set ready */
55 #define UCR3_DCD (1<<9) /* Data carrier detect */
56 #define UCR3_RI (1<<8) /* Ring indicator */
57 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
58 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
59 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
60 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
61 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
62 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
63 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
64 #define UCR3_BPEN (1<<0) /* Preset registers enable */
65 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
66 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
67 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
68 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
69 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
70 #define UCR4_IRSC (1<<5) /* IR special case */
71 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
72 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
73 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
74 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
75 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
76 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
77 #define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
78 #define RFDIV 4 /* divide input clock by 2 */
79 #define UFCR_DCEDTE (1<<6) /* DTE mode select */
80 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
81 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
82 #define USR1_RTSS (1<<14) /* RTS pin status */
83 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
84 #define USR1_RTSD (1<<12) /* RTS delta */
85 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
86 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
87 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
88 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
89 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
90 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
91 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
92 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
93 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
94 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
95 #define USR2_IDLE (1<<12) /* Idle condition */
96 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
97 #define USR2_WAKE (1<<7) /* Wake */
98 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
99 #define USR2_TXDC (1<<3) /* Transmitter complete */
100 #define USR2_BRCD (1<<2) /* Break condition */
101 #define USR2_ORE (1<<1) /* Overrun error */
102 #define USR2_RDR (1<<0) /* Recv data ready */
103 #define UTS_FRCPERR (1<<13) /* Force parity error */
104 #define UTS_LOOP (1<<12) /* Loop tx and rx */
105 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
106 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
107 #define UTS_TXFULL (1<<4) /* TxFIFO full */
108 #define UTS_RXFULL (1<<3) /* RxFIFO full */
109 #define UTS_SOFTRS (1<<0) /* Software reset */
110 #define TXTL 2 /* reset default */
111 #define RXTL 1 /* reset default */
112
113 DECLARE_GLOBAL_DATA_PTR;
114
115 struct mxc_uart {
116 u32 rxd;
117 u32 spare0[15];
118
119 u32 txd;
120 u32 spare1[15];
121
122 u32 cr1;
123 u32 cr2;
124 u32 cr3;
125 u32 cr4;
126
127 u32 fcr;
128 u32 sr1;
129 u32 sr2;
130 u32 esc;
131
132 u32 tim;
133 u32 bir;
134 u32 bmr;
135 u32 brc;
136
137 u32 onems;
138 u32 ts;
139 };
140
_mxc_serial_init(struct mxc_uart * base)141 static void _mxc_serial_init(struct mxc_uart *base)
142 {
143 writel(0, &base->cr1);
144 writel(0, &base->cr2);
145
146 while (!(readl(&base->cr2) & UCR2_SRST));
147
148 writel(0x704 | UCR3_ADNIMP, &base->cr3);
149 writel(0x8000, &base->cr4);
150 writel(0x2b, &base->esc);
151 writel(0, &base->tim);
152
153 writel(0, &base->ts);
154 }
155
_mxc_serial_setbrg(struct mxc_uart * base,unsigned long clk,unsigned long baudrate,bool use_dte)156 static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk,
157 unsigned long baudrate, bool use_dte)
158 {
159 u32 tmp;
160
161 tmp = RFDIV << UFCR_RFDIV_SHF;
162 if (use_dte)
163 tmp |= UFCR_DCEDTE;
164 else
165 tmp |= (TXTL << UFCR_TXTL_SHF) | (RXTL << UFCR_RXTL_SHF);
166 writel(tmp, &base->fcr);
167
168 writel(0xf, &base->bir);
169 writel(clk / (2 * baudrate), &base->bmr);
170
171 writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
172 &base->cr2);
173 writel(UCR1_UARTEN, &base->cr1);
174 }
175
176 #ifndef CONFIG_DM_SERIAL
177
178 #ifndef CONFIG_MXC_UART_BASE
179 #error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
180 #endif
181
182 #define mxc_base ((struct mxc_uart *)CONFIG_MXC_UART_BASE)
183
mxc_serial_setbrg(void)184 static void mxc_serial_setbrg(void)
185 {
186 u32 clk = imx_get_uartclk();
187
188 if (!gd->baudrate)
189 gd->baudrate = CONFIG_BAUDRATE;
190
191 _mxc_serial_setbrg(mxc_base, clk, gd->baudrate, false);
192 }
193
mxc_serial_getc(void)194 static int mxc_serial_getc(void)
195 {
196 while (readl(&mxc_base->ts) & UTS_RXEMPTY)
197 WATCHDOG_RESET();
198 return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
199 }
200
mxc_serial_putc(const char c)201 static void mxc_serial_putc(const char c)
202 {
203 /* If \n, also do \r */
204 if (c == '\n')
205 serial_putc('\r');
206
207 writel(c, &mxc_base->txd);
208
209 /* wait for transmitter to be ready */
210 while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))
211 WATCHDOG_RESET();
212 }
213
214 /* Test whether a character is in the RX buffer */
mxc_serial_tstc(void)215 static int mxc_serial_tstc(void)
216 {
217 /* If receive fifo is empty, return false */
218 if (readl(&mxc_base->ts) & UTS_RXEMPTY)
219 return 0;
220 return 1;
221 }
222
223 /*
224 * Initialise the serial port with the given baudrate. The settings
225 * are always 8 data bits, no parity, 1 stop bit, no start bits.
226 */
mxc_serial_init(void)227 static int mxc_serial_init(void)
228 {
229 _mxc_serial_init(mxc_base);
230
231 serial_setbrg();
232
233 return 0;
234 }
235
236 static struct serial_device mxc_serial_drv = {
237 .name = "mxc_serial",
238 .start = mxc_serial_init,
239 .stop = NULL,
240 .setbrg = mxc_serial_setbrg,
241 .putc = mxc_serial_putc,
242 .puts = default_serial_puts,
243 .getc = mxc_serial_getc,
244 .tstc = mxc_serial_tstc,
245 };
246
mxc_serial_initialize(void)247 void mxc_serial_initialize(void)
248 {
249 serial_register(&mxc_serial_drv);
250 }
251
default_serial_console(void)252 __weak struct serial_device *default_serial_console(void)
253 {
254 return &mxc_serial_drv;
255 }
256 #endif
257
258 #ifdef CONFIG_DM_SERIAL
259
mxc_serial_setbrg(struct udevice * dev,int baudrate)260 int mxc_serial_setbrg(struct udevice *dev, int baudrate)
261 {
262 struct mxc_serial_platdata *plat = dev->platdata;
263 u32 clk = imx_get_uartclk();
264
265 _mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);
266
267 return 0;
268 }
269
mxc_serial_probe(struct udevice * dev)270 static int mxc_serial_probe(struct udevice *dev)
271 {
272 struct mxc_serial_platdata *plat = dev->platdata;
273
274 _mxc_serial_init(plat->reg);
275
276 return 0;
277 }
278
mxc_serial_getc(struct udevice * dev)279 static int mxc_serial_getc(struct udevice *dev)
280 {
281 struct mxc_serial_platdata *plat = dev->platdata;
282 struct mxc_uart *const uart = plat->reg;
283
284 if (readl(&uart->ts) & UTS_RXEMPTY)
285 return -EAGAIN;
286
287 return readl(&uart->rxd) & URXD_RX_DATA;
288 }
289
mxc_serial_putc(struct udevice * dev,const char ch)290 static int mxc_serial_putc(struct udevice *dev, const char ch)
291 {
292 struct mxc_serial_platdata *plat = dev->platdata;
293 struct mxc_uart *const uart = plat->reg;
294
295 if (!(readl(&uart->ts) & UTS_TXEMPTY))
296 return -EAGAIN;
297
298 writel(ch, &uart->txd);
299
300 return 0;
301 }
302
mxc_serial_pending(struct udevice * dev,bool input)303 static int mxc_serial_pending(struct udevice *dev, bool input)
304 {
305 struct mxc_serial_platdata *plat = dev->platdata;
306 struct mxc_uart *const uart = plat->reg;
307 uint32_t sr2 = readl(&uart->sr2);
308
309 if (input)
310 return sr2 & USR2_RDR ? 1 : 0;
311 else
312 return sr2 & USR2_TXDC ? 0 : 1;
313 }
314
315 static const struct dm_serial_ops mxc_serial_ops = {
316 .putc = mxc_serial_putc,
317 .pending = mxc_serial_pending,
318 .getc = mxc_serial_getc,
319 .setbrg = mxc_serial_setbrg,
320 };
321
322 #if CONFIG_IS_ENABLED(OF_CONTROL)
mxc_serial_ofdata_to_platdata(struct udevice * dev)323 static int mxc_serial_ofdata_to_platdata(struct udevice *dev)
324 {
325 struct mxc_serial_platdata *plat = dev->platdata;
326 fdt_addr_t addr;
327
328 addr = devfdt_get_addr(dev);
329 if (addr == FDT_ADDR_T_NONE)
330 return -EINVAL;
331
332 plat->reg = (struct mxc_uart *)addr;
333
334 plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
335 "fsl,dte-mode");
336 return 0;
337 }
338
339 static const struct udevice_id mxc_serial_ids[] = {
340 { .compatible = "fsl,imx6ul-uart" },
341 { .compatible = "fsl,imx7d-uart" },
342 { }
343 };
344 #endif
345
346 U_BOOT_DRIVER(serial_mxc) = {
347 .name = "serial_mxc",
348 .id = UCLASS_SERIAL,
349 #if CONFIG_IS_ENABLED(OF_CONTROL)
350 .of_match = mxc_serial_ids,
351 .ofdata_to_platdata = mxc_serial_ofdata_to_platdata,
352 .platdata_auto_alloc_size = sizeof(struct mxc_serial_platdata),
353 #endif
354 .probe = mxc_serial_probe,
355 .ops = &mxc_serial_ops,
356 .flags = DM_FLAG_PRE_RELOC,
357 };
358 #endif
359
360 #ifdef CONFIG_DEBUG_UART_MXC
361 #include <debug_uart.h>
362
_debug_uart_init(void)363 static inline void _debug_uart_init(void)
364 {
365 struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
366
367 _mxc_serial_init(base);
368 _mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
369 CONFIG_BAUDRATE, false);
370 }
371
_debug_uart_putc(int ch)372 static inline void _debug_uart_putc(int ch)
373 {
374 struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
375
376 while (!(readl(&base->ts) & UTS_TXEMPTY))
377 WATCHDOG_RESET();
378
379 writel(ch, &base->txd);
380 }
381
382 DEBUG_UART_FUNCS
383
384 #endif
385