1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_vec4_gs_visitor.h"
25
26 namespace brw {
27
28 void
nir_setup_inputs()29 vec4_gs_visitor::nir_setup_inputs()
30 {
31 }
32
33 void
nir_emit_intrinsic(nir_intrinsic_instr * instr)34 vec4_gs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
35 {
36 dst_reg dest;
37 src_reg src;
38
39 switch (instr->intrinsic) {
40 case nir_intrinsic_load_per_vertex_input: {
41 /* The EmitNoIndirectInput flag guarantees our vertex index will
42 * be constant. We should handle indirects someday.
43 */
44 nir_const_value *vertex = nir_src_as_const_value(instr->src[0]);
45 nir_const_value *offset_reg = nir_src_as_const_value(instr->src[1]);
46
47 const unsigned input_array_stride = prog_data->urb_read_length * 2;
48
49 if (nir_dest_bit_size(instr->dest) == 64) {
50 src = src_reg(ATTR, input_array_stride * vertex->u32[0] +
51 instr->const_index[0] + offset_reg->u32[0],
52 glsl_type::dvec4_type);
53
54 dst_reg tmp = dst_reg(this, glsl_type::dvec4_type);
55 shuffle_64bit_data(tmp, src, false);
56
57 src = src_reg(tmp);
58 src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr) / 2);
59
60 /* Write to dst reg taking into account original writemask */
61 dest = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_DF);
62 dest.writemask = brw_writemask_for_size(instr->num_components);
63 emit(MOV(dest, src));
64 } else {
65 /* Make up a type...we have no way of knowing... */
66 const glsl_type *const type = glsl_type::ivec(instr->num_components);
67
68 src = src_reg(ATTR, input_array_stride * vertex->u32[0] +
69 instr->const_index[0] + offset_reg->u32[0],
70 type);
71 src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr));
72
73 dest = get_nir_dest(instr->dest, src.type);
74 dest.writemask = brw_writemask_for_size(instr->num_components);
75 emit(MOV(dest, src));
76 }
77 break;
78 }
79
80 case nir_intrinsic_load_input:
81 unreachable("nir_lower_io should have produced per_vertex intrinsics");
82
83 case nir_intrinsic_emit_vertex_with_counter: {
84 this->vertex_count =
85 retype(get_nir_src(instr->src[0], 1), BRW_REGISTER_TYPE_UD);
86 int stream_id = instr->const_index[0];
87 gs_emit_vertex(stream_id);
88 break;
89 }
90
91 case nir_intrinsic_end_primitive_with_counter:
92 this->vertex_count =
93 retype(get_nir_src(instr->src[0], 1), BRW_REGISTER_TYPE_UD);
94 gs_end_primitive();
95 break;
96
97 case nir_intrinsic_set_vertex_count:
98 this->vertex_count =
99 retype(get_nir_src(instr->src[0], 1), BRW_REGISTER_TYPE_UD);
100 break;
101
102 case nir_intrinsic_load_primitive_id:
103 assert(gs_prog_data->include_primitive_id);
104 dest = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
105 emit(MOV(dest, retype(brw_vec4_grf(1, 0), BRW_REGISTER_TYPE_D)));
106 break;
107
108 case nir_intrinsic_load_invocation_id: {
109 dest = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
110 if (gs_prog_data->invocations > 1)
111 emit(GS_OPCODE_GET_INSTANCE_ID, dest);
112 else
113 emit(MOV(dest, brw_imm_ud(0)));
114 break;
115 }
116
117 default:
118 vec4_visitor::nir_emit_intrinsic(instr);
119 }
120 }
121 }
122