1 /* 2 * Copyright (c) 2010 The WebM project authors. All Rights Reserved. 3 * 4 * Use of this source code is governed by a BSD-style license 5 * that can be found in the LICENSE file in the root of the source 6 * tree. An additional intellectual property rights grant can be found 7 * in the file PATENTS. All contributing project authors may 8 * be found in the AUTHORS file in the root of the source tree. 9 */ 10 11 #include "vp9/common/vp9_common_data.h" 12 #include "vpx_dsp/vpx_dsp_common.h" 13 14 // Log 2 conversion lookup tables for block width and height 15 const uint8_t b_width_log2_lookup[BLOCK_SIZES] = { 0, 0, 1, 1, 1, 2, 2, 16 2, 3, 3, 3, 4, 4 }; 17 const uint8_t b_height_log2_lookup[BLOCK_SIZES] = { 0, 1, 0, 1, 2, 1, 2, 18 3, 2, 3, 4, 3, 4 }; 19 const uint8_t num_4x4_blocks_wide_lookup[BLOCK_SIZES] = { 1, 1, 2, 2, 2, 4, 4, 20 4, 8, 8, 8, 16, 16 }; 21 const uint8_t num_4x4_blocks_high_lookup[BLOCK_SIZES] = { 1, 2, 1, 2, 4, 2, 4, 22 8, 4, 8, 16, 8, 16 }; 23 // Log 2 conversion lookup tables for modeinfo width and height 24 const uint8_t mi_width_log2_lookup[BLOCK_SIZES] = { 0, 0, 0, 0, 0, 1, 1, 25 1, 2, 2, 2, 3, 3 }; 26 const uint8_t num_8x8_blocks_wide_lookup[BLOCK_SIZES] = { 1, 1, 1, 1, 1, 2, 2, 27 2, 4, 4, 4, 8, 8 }; 28 const uint8_t num_8x8_blocks_high_lookup[BLOCK_SIZES] = { 1, 1, 1, 1, 2, 1, 2, 29 4, 2, 4, 8, 4, 8 }; 30 31 // VPXMIN(3, VPXMIN(b_width_log2_lookup(bsize), b_height_log2_lookup(bsize))) 32 const uint8_t size_group_lookup[BLOCK_SIZES] = { 0, 0, 0, 1, 1, 1, 2, 33 2, 2, 3, 3, 3, 3 }; 34 35 const uint8_t num_pels_log2_lookup[BLOCK_SIZES] = { 4, 5, 5, 6, 7, 7, 8, 36 9, 9, 10, 11, 11, 12 }; 37 38 const PARTITION_TYPE partition_lookup[][BLOCK_SIZES] = { 39 { // 4X4 40 // 4X4, 4X8,8X4,8X8,8X16,16X8,16X16,16X32,32X16,32X32,32X64,64X32,64X64 41 PARTITION_NONE, PARTITION_INVALID, PARTITION_INVALID, PARTITION_INVALID, 42 PARTITION_INVALID, PARTITION_INVALID, PARTITION_INVALID, PARTITION_INVALID, 43 PARTITION_INVALID, PARTITION_INVALID, PARTITION_INVALID, PARTITION_INVALID, 44 PARTITION_INVALID }, 45 { // 8X8 46 // 4X4, 4X8,8X4,8X8,8X16,16X8,16X16,16X32,32X16,32X32,32X64,64X32,64X64 47 PARTITION_SPLIT, PARTITION_VERT, PARTITION_HORZ, PARTITION_NONE, 48 PARTITION_INVALID, PARTITION_INVALID, PARTITION_INVALID, PARTITION_INVALID, 49 PARTITION_INVALID, PARTITION_INVALID, PARTITION_INVALID, PARTITION_INVALID, 50 PARTITION_INVALID }, 51 { // 16X16 52 // 4X4, 4X8,8X4,8X8,8X16,16X8,16X16,16X32,32X16,32X32,32X64,64X32,64X64 53 PARTITION_SPLIT, PARTITION_SPLIT, PARTITION_SPLIT, PARTITION_SPLIT, 54 PARTITION_VERT, PARTITION_HORZ, PARTITION_NONE, PARTITION_INVALID, 55 PARTITION_INVALID, PARTITION_INVALID, PARTITION_INVALID, PARTITION_INVALID, 56 PARTITION_INVALID }, 57 { // 32X32 58 // 4X4, 4X8,8X4,8X8,8X16,16X8,16X16,16X32,32X16,32X32,32X64,64X32,64X64 59 PARTITION_SPLIT, PARTITION_SPLIT, PARTITION_SPLIT, PARTITION_SPLIT, 60 PARTITION_SPLIT, PARTITION_SPLIT, PARTITION_SPLIT, PARTITION_VERT, 61 PARTITION_HORZ, PARTITION_NONE, PARTITION_INVALID, PARTITION_INVALID, 62 PARTITION_INVALID }, 63 { // 64X64 64 // 4X4, 4X8,8X4,8X8,8X16,16X8,16X16,16X32,32X16,32X32,32X64,64X32,64X64 65 PARTITION_SPLIT, PARTITION_SPLIT, PARTITION_SPLIT, PARTITION_SPLIT, 66 PARTITION_SPLIT, PARTITION_SPLIT, PARTITION_SPLIT, PARTITION_SPLIT, 67 PARTITION_SPLIT, PARTITION_SPLIT, PARTITION_VERT, PARTITION_HORZ, 68 PARTITION_NONE } 69 }; 70 71 const BLOCK_SIZE subsize_lookup[PARTITION_TYPES][BLOCK_SIZES] = { 72 { // PARTITION_NONE 73 BLOCK_4X4, BLOCK_4X8, BLOCK_8X4, BLOCK_8X8, BLOCK_8X16, BLOCK_16X8, 74 BLOCK_16X16, BLOCK_16X32, BLOCK_32X16, BLOCK_32X32, BLOCK_32X64, 75 BLOCK_64X32, BLOCK_64X64 }, 76 { // PARTITION_HORZ 77 BLOCK_INVALID, BLOCK_INVALID, BLOCK_INVALID, BLOCK_8X4, BLOCK_INVALID, 78 BLOCK_INVALID, BLOCK_16X8, BLOCK_INVALID, BLOCK_INVALID, BLOCK_32X16, 79 BLOCK_INVALID, BLOCK_INVALID, BLOCK_64X32 }, 80 { // PARTITION_VERT 81 BLOCK_INVALID, BLOCK_INVALID, BLOCK_INVALID, BLOCK_4X8, BLOCK_INVALID, 82 BLOCK_INVALID, BLOCK_8X16, BLOCK_INVALID, BLOCK_INVALID, BLOCK_16X32, 83 BLOCK_INVALID, BLOCK_INVALID, BLOCK_32X64 }, 84 { // PARTITION_SPLIT 85 BLOCK_INVALID, BLOCK_INVALID, BLOCK_INVALID, BLOCK_4X4, BLOCK_INVALID, 86 BLOCK_INVALID, BLOCK_8X8, BLOCK_INVALID, BLOCK_INVALID, BLOCK_16X16, 87 BLOCK_INVALID, BLOCK_INVALID, BLOCK_32X32 } 88 }; 89 90 const TX_SIZE max_txsize_lookup[BLOCK_SIZES] = { 91 TX_4X4, TX_4X4, TX_4X4, TX_8X8, TX_8X8, TX_8X8, TX_16X16, 92 TX_16X16, TX_16X16, TX_32X32, TX_32X32, TX_32X32, TX_32X32 93 }; 94 95 const BLOCK_SIZE txsize_to_bsize[TX_SIZES] = { 96 BLOCK_4X4, // TX_4X4 97 BLOCK_8X8, // TX_8X8 98 BLOCK_16X16, // TX_16X16 99 BLOCK_32X32, // TX_32X32 100 }; 101 102 const TX_SIZE tx_mode_to_biggest_tx_size[TX_MODES] = { 103 TX_4X4, // ONLY_4X4 104 TX_8X8, // ALLOW_8X8 105 TX_16X16, // ALLOW_16X16 106 TX_32X32, // ALLOW_32X32 107 TX_32X32, // TX_MODE_SELECT 108 }; 109 110 const BLOCK_SIZE ss_size_lookup[BLOCK_SIZES][2][2] = { 111 // ss_x == 0 ss_x == 0 ss_x == 1 ss_x == 1 112 // ss_y == 0 ss_y == 1 ss_y == 0 ss_y == 1 113 { { BLOCK_4X4, BLOCK_INVALID }, { BLOCK_INVALID, BLOCK_INVALID } }, 114 { { BLOCK_4X8, BLOCK_4X4 }, { BLOCK_INVALID, BLOCK_INVALID } }, 115 { { BLOCK_8X4, BLOCK_INVALID }, { BLOCK_4X4, BLOCK_INVALID } }, 116 { { BLOCK_8X8, BLOCK_8X4 }, { BLOCK_4X8, BLOCK_4X4 } }, 117 { { BLOCK_8X16, BLOCK_8X8 }, { BLOCK_INVALID, BLOCK_4X8 } }, 118 { { BLOCK_16X8, BLOCK_INVALID }, { BLOCK_8X8, BLOCK_8X4 } }, 119 { { BLOCK_16X16, BLOCK_16X8 }, { BLOCK_8X16, BLOCK_8X8 } }, 120 { { BLOCK_16X32, BLOCK_16X16 }, { BLOCK_INVALID, BLOCK_8X16 } }, 121 { { BLOCK_32X16, BLOCK_INVALID }, { BLOCK_16X16, BLOCK_16X8 } }, 122 { { BLOCK_32X32, BLOCK_32X16 }, { BLOCK_16X32, BLOCK_16X16 } }, 123 { { BLOCK_32X64, BLOCK_32X32 }, { BLOCK_INVALID, BLOCK_16X32 } }, 124 { { BLOCK_64X32, BLOCK_INVALID }, { BLOCK_32X32, BLOCK_32X16 } }, 125 { { BLOCK_64X64, BLOCK_64X32 }, { BLOCK_32X64, BLOCK_32X32 } }, 126 }; 127 128 const TX_SIZE uv_txsize_lookup[BLOCK_SIZES][TX_SIZES][2][2] = { 129 // ss_x == 0 ss_x == 0 ss_x == 1 ss_x == 1 130 // ss_y == 0 ss_y == 1 ss_y == 0 ss_y == 1 131 { 132 // BLOCK_4X4 133 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 134 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 135 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 136 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 137 }, 138 { 139 // BLOCK_4X8 140 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 141 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 142 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 143 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 144 }, 145 { 146 // BLOCK_8X4 147 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 148 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 149 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 150 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 151 }, 152 { 153 // BLOCK_8X8 154 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 155 { { TX_8X8, TX_4X4 }, { TX_4X4, TX_4X4 } }, 156 { { TX_8X8, TX_4X4 }, { TX_4X4, TX_4X4 } }, 157 { { TX_8X8, TX_4X4 }, { TX_4X4, TX_4X4 } }, 158 }, 159 { 160 // BLOCK_8X16 161 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 162 { { TX_8X8, TX_8X8 }, { TX_4X4, TX_4X4 } }, 163 { { TX_8X8, TX_8X8 }, { TX_4X4, TX_4X4 } }, 164 { { TX_8X8, TX_8X8 }, { TX_4X4, TX_4X4 } }, 165 }, 166 { 167 // BLOCK_16X8 168 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 169 { { TX_8X8, TX_4X4 }, { TX_8X8, TX_4X4 } }, 170 { { TX_8X8, TX_4X4 }, { TX_8X8, TX_8X8 } }, 171 { { TX_8X8, TX_4X4 }, { TX_8X8, TX_8X8 } }, 172 }, 173 { 174 // BLOCK_16X16 175 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 176 { { TX_8X8, TX_8X8 }, { TX_8X8, TX_8X8 } }, 177 { { TX_16X16, TX_8X8 }, { TX_8X8, TX_8X8 } }, 178 { { TX_16X16, TX_8X8 }, { TX_8X8, TX_8X8 } }, 179 }, 180 { 181 // BLOCK_16X32 182 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 183 { { TX_8X8, TX_8X8 }, { TX_8X8, TX_8X8 } }, 184 { { TX_16X16, TX_16X16 }, { TX_8X8, TX_8X8 } }, 185 { { TX_16X16, TX_16X16 }, { TX_8X8, TX_8X8 } }, 186 }, 187 { 188 // BLOCK_32X16 189 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 190 { { TX_8X8, TX_8X8 }, { TX_8X8, TX_8X8 } }, 191 { { TX_16X16, TX_8X8 }, { TX_16X16, TX_8X8 } }, 192 { { TX_16X16, TX_8X8 }, { TX_16X16, TX_8X8 } }, 193 }, 194 { 195 // BLOCK_32X32 196 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 197 { { TX_8X8, TX_8X8 }, { TX_8X8, TX_8X8 } }, 198 { { TX_16X16, TX_16X16 }, { TX_16X16, TX_16X16 } }, 199 { { TX_32X32, TX_16X16 }, { TX_16X16, TX_16X16 } }, 200 }, 201 { 202 // BLOCK_32X64 203 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 204 { { TX_8X8, TX_8X8 }, { TX_8X8, TX_8X8 } }, 205 { { TX_16X16, TX_16X16 }, { TX_16X16, TX_16X16 } }, 206 { { TX_32X32, TX_32X32 }, { TX_16X16, TX_16X16 } }, 207 }, 208 { 209 // BLOCK_64X32 210 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 211 { { TX_8X8, TX_8X8 }, { TX_8X8, TX_8X8 } }, 212 { { TX_16X16, TX_16X16 }, { TX_16X16, TX_16X16 } }, 213 { { TX_32X32, TX_16X16 }, { TX_32X32, TX_16X16 } }, 214 }, 215 { 216 // BLOCK_64X64 217 { { TX_4X4, TX_4X4 }, { TX_4X4, TX_4X4 } }, 218 { { TX_8X8, TX_8X8 }, { TX_8X8, TX_8X8 } }, 219 { { TX_16X16, TX_16X16 }, { TX_16X16, TX_16X16 } }, 220 { { TX_32X32, TX_32X32 }, { TX_32X32, TX_32X32 } }, 221 }, 222 }; 223 224 // Generates 4 bit field in which each bit set to 1 represents 225 // a blocksize partition 1111 means we split 64x64, 32x32, 16x16 226 // and 8x8. 1000 means we just split the 64x64 to 32x32 227 const struct { 228 PARTITION_CONTEXT above; 229 PARTITION_CONTEXT left; 230 } partition_context_lookup[BLOCK_SIZES] = { 231 { 15, 15 }, // 4X4 - {0b1111, 0b1111} 232 { 15, 14 }, // 4X8 - {0b1111, 0b1110} 233 { 14, 15 }, // 8X4 - {0b1110, 0b1111} 234 { 14, 14 }, // 8X8 - {0b1110, 0b1110} 235 { 14, 12 }, // 8X16 - {0b1110, 0b1100} 236 { 12, 14 }, // 16X8 - {0b1100, 0b1110} 237 { 12, 12 }, // 16X16 - {0b1100, 0b1100} 238 { 12, 8 }, // 16X32 - {0b1100, 0b1000} 239 { 8, 12 }, // 32X16 - {0b1000, 0b1100} 240 { 8, 8 }, // 32X32 - {0b1000, 0b1000} 241 { 8, 0 }, // 32X64 - {0b1000, 0b0000} 242 { 0, 8 }, // 64X32 - {0b0000, 0b1000} 243 { 0, 0 }, // 64X64 - {0b0000, 0b0000} 244 }; 245 246 #if CONFIG_BETTER_HW_COMPATIBILITY && CONFIG_VP9_HIGHBITDEPTH 247 const uint8_t need_top_left[INTRA_MODES] = { 248 0, // DC_PRED 249 0, // V_PRED 250 0, // H_PRED 251 0, // D45_PRED 252 1, // D135_PRED 253 1, // D117_PRED 254 1, // D153_PRED 255 0, // D207_PRED 256 0, // D63_PRED 257 1, // TM_PRED 258 }; 259 #endif // CONFIG_BETTER_HW_COMPATIBILITY && CONFIG_VP9_HIGHBITDEPTH 260