1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdint.h>
24
25 #include "pipe/p_defines.h"
26
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30 #include "util/u_surface.h"
31
32 #include "os/os_thread.h"
33
34 #include "nvc0/nvc0_context.h"
35 #include "nvc0/nvc0_resource.h"
36
37 #include "nv50/g80_defs.xml.h"
38 #include "nv50/g80_texture.xml.h"
39
40 /* these are used in nv50_blit.h */
41 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff9ccfe1cce3ccc9ULL
42 #define NV50_ENG2D_NOCONVERT_FORMATS 0x009cc02000000000ULL
43 #define NV50_ENG2D_LUMINANCE_FORMATS 0x001cc02000000000ULL
44 #define NV50_ENG2D_INTENSITY_FORMATS 0x0080000000000000ULL
45 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000638000ULL
46
47 #define NOUVEAU_DRIVER 0xc0
48 #include "nv50/nv50_blit.h"
49
50 static inline uint8_t
nvc0_2d_format(enum pipe_format format,bool dst,bool dst_src_equal)51 nvc0_2d_format(enum pipe_format format, bool dst, bool dst_src_equal)
52 {
53 uint8_t id = nvc0_format_table[format].rt;
54
55 /* A8_UNORM is treated as I8_UNORM as far as the 2D engine is concerned. */
56 if (!dst && unlikely(format == PIPE_FORMAT_I8_UNORM) && !dst_src_equal)
57 return G80_SURFACE_FORMAT_A8_UNORM;
58
59 /* Hardware values for color formats range from 0xc0 to 0xff,
60 * but the 2D engine doesn't support all of them.
61 */
62 if (nv50_2d_format_supported(format))
63 return id;
64 assert(dst_src_equal);
65
66 switch (util_format_get_blocksize(format)) {
67 case 1:
68 return G80_SURFACE_FORMAT_R8_UNORM;
69 case 2:
70 return G80_SURFACE_FORMAT_RG8_UNORM;
71 case 4:
72 return G80_SURFACE_FORMAT_BGRA8_UNORM;
73 case 8:
74 return G80_SURFACE_FORMAT_RGBA16_UNORM;
75 case 16:
76 return G80_SURFACE_FORMAT_RGBA32_FLOAT;
77 default:
78 assert(0);
79 return 0;
80 }
81 }
82
83 static int
nvc0_2d_texture_set(struct nouveau_pushbuf * push,bool dst,struct nv50_miptree * mt,unsigned level,unsigned layer,enum pipe_format pformat,bool dst_src_pformat_equal)84 nvc0_2d_texture_set(struct nouveau_pushbuf *push, bool dst,
85 struct nv50_miptree *mt, unsigned level, unsigned layer,
86 enum pipe_format pformat, bool dst_src_pformat_equal)
87 {
88 struct nouveau_bo *bo = mt->base.bo;
89 uint32_t width, height, depth;
90 uint32_t format;
91 uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
92 uint32_t offset = mt->level[level].offset;
93
94 format = nvc0_2d_format(pformat, dst, dst_src_pformat_equal);
95 if (!format) {
96 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
97 util_format_name(pformat));
98 return 1;
99 }
100
101 width = u_minify(mt->base.base.width0, level) << mt->ms_x;
102 height = u_minify(mt->base.base.height0, level) << mt->ms_y;
103 depth = u_minify(mt->base.base.depth0, level);
104
105 /* layer has to be < depth, and depth > tile depth / 2 */
106
107 if (!mt->layout_3d) {
108 offset += mt->layer_stride * layer;
109 layer = 0;
110 depth = 1;
111 } else
112 if (!dst) {
113 offset += nvc0_mt_zslice_offset(mt, level, layer);
114 layer = 0;
115 }
116
117 if (!nouveau_bo_memtype(bo)) {
118 BEGIN_NVC0(push, SUBC_2D(mthd), 2);
119 PUSH_DATA (push, format);
120 PUSH_DATA (push, 1);
121 BEGIN_NVC0(push, SUBC_2D(mthd + 0x14), 5);
122 PUSH_DATA (push, mt->level[level].pitch);
123 PUSH_DATA (push, width);
124 PUSH_DATA (push, height);
125 PUSH_DATAh(push, bo->offset + offset);
126 PUSH_DATA (push, bo->offset + offset);
127 } else {
128 BEGIN_NVC0(push, SUBC_2D(mthd), 5);
129 PUSH_DATA (push, format);
130 PUSH_DATA (push, 0);
131 PUSH_DATA (push, mt->level[level].tile_mode);
132 PUSH_DATA (push, depth);
133 PUSH_DATA (push, layer);
134 BEGIN_NVC0(push, SUBC_2D(mthd + 0x18), 4);
135 PUSH_DATA (push, width);
136 PUSH_DATA (push, height);
137 PUSH_DATAh(push, bo->offset + offset);
138 PUSH_DATA (push, bo->offset + offset);
139 }
140
141 #if 0
142 if (dst) {
143 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_CLIP_X), 4);
144 PUSH_DATA (push, 0);
145 PUSH_DATA (push, 0);
146 PUSH_DATA (push, width);
147 PUSH_DATA (push, height);
148 }
149 #endif
150 return 0;
151 }
152
153 static int
nvc0_2d_texture_do_copy(struct nouveau_pushbuf * push,struct nv50_miptree * dst,unsigned dst_level,unsigned dx,unsigned dy,unsigned dz,struct nv50_miptree * src,unsigned src_level,unsigned sx,unsigned sy,unsigned sz,unsigned w,unsigned h)154 nvc0_2d_texture_do_copy(struct nouveau_pushbuf *push,
155 struct nv50_miptree *dst, unsigned dst_level,
156 unsigned dx, unsigned dy, unsigned dz,
157 struct nv50_miptree *src, unsigned src_level,
158 unsigned sx, unsigned sy, unsigned sz,
159 unsigned w, unsigned h)
160 {
161 const enum pipe_format dfmt = dst->base.base.format;
162 const enum pipe_format sfmt = src->base.base.format;
163 int ret;
164 bool eqfmt = dfmt == sfmt;
165
166 if (!PUSH_SPACE(push, 2 * 16 + 32))
167 return PIPE_ERROR;
168
169 ret = nvc0_2d_texture_set(push, true, dst, dst_level, dz, dfmt, eqfmt);
170 if (ret)
171 return ret;
172
173 ret = nvc0_2d_texture_set(push, false, src, src_level, sz, sfmt, eqfmt);
174 if (ret)
175 return ret;
176
177 IMMED_NVC0(push, NVC0_2D(BLIT_CONTROL), 0x00);
178 BEGIN_NVC0(push, NVC0_2D(BLIT_DST_X), 4);
179 PUSH_DATA (push, dx << dst->ms_x);
180 PUSH_DATA (push, dy << dst->ms_y);
181 PUSH_DATA (push, w << dst->ms_x);
182 PUSH_DATA (push, h << dst->ms_y);
183 BEGIN_NVC0(push, NVC0_2D(BLIT_DU_DX_FRACT), 4);
184 PUSH_DATA (push, 0);
185 PUSH_DATA (push, 1);
186 PUSH_DATA (push, 0);
187 PUSH_DATA (push, 1);
188 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_X_FRACT), 4);
189 PUSH_DATA (push, 0);
190 PUSH_DATA (push, sx << src->ms_x);
191 PUSH_DATA (push, 0);
192 PUSH_DATA (push, sy << src->ms_y);
193
194 return 0;
195 }
196
197 static void
nvc0_resource_copy_region(struct pipe_context * pipe,struct pipe_resource * dst,unsigned dst_level,unsigned dstx,unsigned dsty,unsigned dstz,struct pipe_resource * src,unsigned src_level,const struct pipe_box * src_box)198 nvc0_resource_copy_region(struct pipe_context *pipe,
199 struct pipe_resource *dst, unsigned dst_level,
200 unsigned dstx, unsigned dsty, unsigned dstz,
201 struct pipe_resource *src, unsigned src_level,
202 const struct pipe_box *src_box)
203 {
204 struct nvc0_context *nvc0 = nvc0_context(pipe);
205 int ret;
206 bool m2mf;
207 unsigned dst_layer = dstz, src_layer = src_box->z;
208
209 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
210 nouveau_copy_buffer(&nvc0->base,
211 nv04_resource(dst), dstx,
212 nv04_resource(src), src_box->x, src_box->width);
213 NOUVEAU_DRV_STAT(&nvc0->screen->base, buf_copy_bytes, src_box->width);
214 return;
215 }
216 NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_copy_count, 1);
217
218 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
219 assert((src->nr_samples | 1) == (dst->nr_samples | 1));
220
221 m2mf = (src->format == dst->format) ||
222 (util_format_get_blocksizebits(src->format) ==
223 util_format_get_blocksizebits(dst->format));
224
225 nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
226
227 if (m2mf) {
228 struct nv50_miptree *src_mt = nv50_miptree(src);
229 struct nv50_miptree *dst_mt = nv50_miptree(dst);
230 struct nv50_m2mf_rect drect, srect;
231 unsigned i;
232 unsigned nx = util_format_get_nblocksx(src->format, src_box->width)
233 << src_mt->ms_x;
234 unsigned ny = util_format_get_nblocksy(src->format, src_box->height)
235 << src_mt->ms_y;
236
237 nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
238 nv50_m2mf_rect_setup(&srect, src, src_level,
239 src_box->x, src_box->y, src_box->z);
240
241 for (i = 0; i < src_box->depth; ++i) {
242 nvc0->m2mf_copy_rect(nvc0, &drect, &srect, nx, ny);
243
244 if (dst_mt->layout_3d)
245 drect.z++;
246 else
247 drect.base += dst_mt->layer_stride;
248
249 if (src_mt->layout_3d)
250 srect.z++;
251 else
252 srect.base += src_mt->layer_stride;
253 }
254 return;
255 }
256
257 assert(nv50_2d_dst_format_faithful(dst->format));
258 assert(nv50_2d_src_format_faithful(src->format));
259
260 BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(src), RD);
261 BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(dst), WR);
262 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx);
263 nouveau_pushbuf_validate(nvc0->base.pushbuf);
264
265 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
266 ret = nvc0_2d_texture_do_copy(nvc0->base.pushbuf,
267 nv50_miptree(dst), dst_level,
268 dstx, dsty, dst_layer,
269 nv50_miptree(src), src_level,
270 src_box->x, src_box->y, src_layer,
271 src_box->width, src_box->height);
272 if (ret)
273 break;
274 }
275 nouveau_bufctx_reset(nvc0->bufctx, 0);
276 }
277
278 static void
nvc0_clear_render_target(struct pipe_context * pipe,struct pipe_surface * dst,const union pipe_color_union * color,unsigned dstx,unsigned dsty,unsigned width,unsigned height,bool render_condition_enabled)279 nvc0_clear_render_target(struct pipe_context *pipe,
280 struct pipe_surface *dst,
281 const union pipe_color_union *color,
282 unsigned dstx, unsigned dsty,
283 unsigned width, unsigned height,
284 bool render_condition_enabled)
285 {
286 struct nvc0_context *nvc0 = nvc0_context(pipe);
287 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
288 struct nv50_surface *sf = nv50_surface(dst);
289 struct nv04_resource *res = nv04_resource(sf->base.texture);
290 unsigned z;
291
292 assert(dst->texture->target != PIPE_BUFFER);
293
294 if (!PUSH_SPACE(push, 32 + sf->depth))
295 return;
296
297 PUSH_REFN (push, res->bo, res->domain | NOUVEAU_BO_WR);
298
299 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
300 PUSH_DATAf(push, color->f[0]);
301 PUSH_DATAf(push, color->f[1]);
302 PUSH_DATAf(push, color->f[2]);
303 PUSH_DATAf(push, color->f[3]);
304
305 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
306 PUSH_DATA (push, ( width << 16) | dstx);
307 PUSH_DATA (push, (height << 16) | dsty);
308
309 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
310 PUSH_DATA (push, 1);
311 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
312 PUSH_DATAh(push, res->address + sf->offset);
313 PUSH_DATA (push, res->address + sf->offset);
314 if (likely(nouveau_bo_memtype(res->bo))) {
315 struct nv50_miptree *mt = nv50_miptree(dst->texture);
316
317 PUSH_DATA(push, sf->width);
318 PUSH_DATA(push, sf->height);
319 PUSH_DATA(push, nvc0_format_table[dst->format].rt);
320 PUSH_DATA(push, (mt->layout_3d << 16) |
321 mt->level[sf->base.u.tex.level].tile_mode);
322 PUSH_DATA(push, dst->u.tex.first_layer + sf->depth);
323 PUSH_DATA(push, mt->layer_stride >> 2);
324 PUSH_DATA(push, dst->u.tex.first_layer);
325 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), mt->ms_mode);
326 } else {
327 if (res->base.target == PIPE_BUFFER) {
328 PUSH_DATA(push, 262144);
329 PUSH_DATA(push, 1);
330 } else {
331 PUSH_DATA(push, nv50_miptree(&res->base)->level[0].pitch);
332 PUSH_DATA(push, sf->height);
333 }
334 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
335 PUSH_DATA(push, 1 << 12);
336 PUSH_DATA(push, 1);
337 PUSH_DATA(push, 0);
338 PUSH_DATA(push, 0);
339
340 IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0);
341 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 0);
342
343 /* tiled textures don't have to be fenced, they're not mapped directly */
344 nvc0_resource_fence(res, NOUVEAU_BO_WR);
345 }
346
347 if (!render_condition_enabled)
348 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
349
350 BEGIN_NIC0(push, NVC0_3D(CLEAR_BUFFERS), sf->depth);
351 for (z = 0; z < sf->depth; ++z) {
352 PUSH_DATA (push, 0x3c |
353 (z << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
354 }
355
356 if (!render_condition_enabled)
357 IMMED_NVC0(push, NVC0_3D(COND_MODE), nvc0->cond_condmode);
358
359 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER;
360 }
361
362 static void
nvc0_clear_buffer_push_nvc0(struct pipe_context * pipe,struct pipe_resource * res,unsigned offset,unsigned size,const void * data,int data_size)363 nvc0_clear_buffer_push_nvc0(struct pipe_context *pipe,
364 struct pipe_resource *res,
365 unsigned offset, unsigned size,
366 const void *data, int data_size)
367 {
368 struct nvc0_context *nvc0 = nvc0_context(pipe);
369 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
370 struct nv04_resource *buf = nv04_resource(res);
371 unsigned i;
372
373 nouveau_bufctx_refn(nvc0->bufctx, 0, buf->bo, buf->domain | NOUVEAU_BO_WR);
374 nouveau_pushbuf_bufctx(push, nvc0->bufctx);
375 nouveau_pushbuf_validate(push);
376
377 unsigned count = (size + 3) / 4;
378 unsigned data_words = data_size / 4;
379
380 while (count) {
381 unsigned nr_data = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN) / data_words;
382 unsigned nr = nr_data * data_words;
383
384 if (!PUSH_SPACE(push, nr + 9))
385 break;
386
387 BEGIN_NVC0(push, NVC0_M2MF(OFFSET_OUT_HIGH), 2);
388 PUSH_DATAh(push, buf->address + offset);
389 PUSH_DATA (push, buf->address + offset);
390 BEGIN_NVC0(push, NVC0_M2MF(LINE_LENGTH_IN), 2);
391 PUSH_DATA (push, MIN2(size, nr * 4));
392 PUSH_DATA (push, 1);
393 BEGIN_NVC0(push, NVC0_M2MF(EXEC), 1);
394 PUSH_DATA (push, 0x100111);
395
396 /* must not be interrupted (trap on QUERY fence, 0x50 works however) */
397 BEGIN_NIC0(push, NVC0_M2MF(DATA), nr);
398 for (i = 0; i < nr_data; i++)
399 PUSH_DATAp(push, data, data_words);
400
401 count -= nr;
402 offset += nr * 4;
403 size -= nr * 4;
404 }
405
406 if (buf->mm) {
407 nouveau_fence_ref(nvc0->screen->base.fence.current, &buf->fence);
408 nouveau_fence_ref(nvc0->screen->base.fence.current, &buf->fence_wr);
409 }
410
411 nouveau_bufctx_reset(nvc0->bufctx, 0);
412 }
413
414 static void
nvc0_clear_buffer_push_nve4(struct pipe_context * pipe,struct pipe_resource * res,unsigned offset,unsigned size,const void * data,int data_size)415 nvc0_clear_buffer_push_nve4(struct pipe_context *pipe,
416 struct pipe_resource *res,
417 unsigned offset, unsigned size,
418 const void *data, int data_size)
419 {
420 struct nvc0_context *nvc0 = nvc0_context(pipe);
421 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
422 struct nv04_resource *buf = nv04_resource(res);
423 unsigned i;
424
425 nouveau_bufctx_refn(nvc0->bufctx, 0, buf->bo, buf->domain | NOUVEAU_BO_WR);
426 nouveau_pushbuf_bufctx(push, nvc0->bufctx);
427 nouveau_pushbuf_validate(push);
428
429 unsigned count = (size + 3) / 4;
430 unsigned data_words = data_size / 4;
431
432 while (count) {
433 unsigned nr_data = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN) / data_words;
434 unsigned nr = nr_data * data_words;
435
436 if (!PUSH_SPACE(push, nr + 10))
437 break;
438
439 BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_DST_ADDRESS_HIGH), 2);
440 PUSH_DATAh(push, buf->address + offset);
441 PUSH_DATA (push, buf->address + offset);
442 BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_LINE_LENGTH_IN), 2);
443 PUSH_DATA (push, MIN2(size, nr * 4));
444 PUSH_DATA (push, 1);
445 /* must not be interrupted (trap on QUERY fence, 0x50 works however) */
446 BEGIN_1IC0(push, NVE4_P2MF(UPLOAD_EXEC), nr + 1);
447 PUSH_DATA (push, 0x1001);
448 for (i = 0; i < nr_data; i++)
449 PUSH_DATAp(push, data, data_words);
450
451 count -= nr;
452 offset += nr * 4;
453 size -= nr * 4;
454 }
455
456 if (buf->mm) {
457 nouveau_fence_ref(nvc0->screen->base.fence.current, &buf->fence);
458 nouveau_fence_ref(nvc0->screen->base.fence.current, &buf->fence_wr);
459 }
460
461 nouveau_bufctx_reset(nvc0->bufctx, 0);
462 }
463
464 static void
nvc0_clear_buffer_push(struct pipe_context * pipe,struct pipe_resource * res,unsigned offset,unsigned size,const void * data,int data_size)465 nvc0_clear_buffer_push(struct pipe_context *pipe,
466 struct pipe_resource *res,
467 unsigned offset, unsigned size,
468 const void *data, int data_size)
469 {
470 struct nvc0_context *nvc0 = nvc0_context(pipe);
471 unsigned tmp;
472
473 if (data_size == 1) {
474 tmp = *(unsigned char *)data;
475 tmp = (tmp << 24) | (tmp << 16) | (tmp << 8) | tmp;
476 data = &tmp;
477 data_size = 4;
478 } else if (data_size == 2) {
479 tmp = *(unsigned short *)data;
480 tmp = (tmp << 16) | tmp;
481 data = &tmp;
482 data_size = 4;
483 }
484
485 if (nvc0->screen->base.class_3d < NVE4_3D_CLASS)
486 nvc0_clear_buffer_push_nvc0(pipe, res, offset, size, data, data_size);
487 else
488 nvc0_clear_buffer_push_nve4(pipe, res, offset, size, data, data_size);
489 }
490
491 static void
nvc0_clear_buffer(struct pipe_context * pipe,struct pipe_resource * res,unsigned offset,unsigned size,const void * data,int data_size)492 nvc0_clear_buffer(struct pipe_context *pipe,
493 struct pipe_resource *res,
494 unsigned offset, unsigned size,
495 const void *data, int data_size)
496 {
497 struct nvc0_context *nvc0 = nvc0_context(pipe);
498 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
499 struct nv04_resource *buf = nv04_resource(res);
500 union pipe_color_union color;
501 enum pipe_format dst_fmt;
502 unsigned width, height, elements;
503
504 assert(res->target == PIPE_BUFFER);
505 assert(nouveau_bo_memtype(buf->bo) == 0);
506
507 switch (data_size) {
508 case 16:
509 dst_fmt = PIPE_FORMAT_R32G32B32A32_UINT;
510 memcpy(&color.ui, data, 16);
511 break;
512 case 12:
513 /* RGB32 is not a valid RT format. This will be handled by the pushbuf
514 * uploader.
515 */
516 break;
517 case 8:
518 dst_fmt = PIPE_FORMAT_R32G32_UINT;
519 memcpy(&color.ui, data, 8);
520 memset(&color.ui[2], 0, 8);
521 break;
522 case 4:
523 dst_fmt = PIPE_FORMAT_R32_UINT;
524 memcpy(&color.ui, data, 4);
525 memset(&color.ui[1], 0, 12);
526 break;
527 case 2:
528 dst_fmt = PIPE_FORMAT_R16_UINT;
529 color.ui[0] = util_cpu_to_le32(
530 util_le16_to_cpu(*(unsigned short *)data));
531 memset(&color.ui[1], 0, 12);
532 break;
533 case 1:
534 dst_fmt = PIPE_FORMAT_R8_UINT;
535 color.ui[0] = util_cpu_to_le32(*(unsigned char *)data);
536 memset(&color.ui[1], 0, 12);
537 break;
538 default:
539 assert(!"Unsupported element size");
540 return;
541 }
542
543 assert(size % data_size == 0);
544
545 if (data_size == 12) {
546 nvc0_clear_buffer_push(pipe, res, offset, size, data, data_size);
547 return;
548 }
549
550 if (offset & 0xff) {
551 unsigned fixup_size = MIN2(size, align(offset, 0x100) - offset);
552 assert(fixup_size % data_size == 0);
553 nvc0_clear_buffer_push(pipe, res, offset, fixup_size, data, data_size);
554 offset += fixup_size;
555 size -= fixup_size;
556 if (!size)
557 return;
558 }
559
560 elements = size / data_size;
561 height = (elements + 16383) / 16384;
562 width = elements / height;
563 if (height > 1)
564 width &= ~0xff;
565 assert(width > 0);
566
567 if (!PUSH_SPACE(push, 40))
568 return;
569
570 PUSH_REFN (push, buf->bo, buf->domain | NOUVEAU_BO_WR);
571
572 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
573 PUSH_DATAf(push, color.f[0]);
574 PUSH_DATAf(push, color.f[1]);
575 PUSH_DATAf(push, color.f[2]);
576 PUSH_DATAf(push, color.f[3]);
577 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
578 PUSH_DATA (push, width << 16);
579 PUSH_DATA (push, height << 16);
580
581 IMMED_NVC0(push, NVC0_3D(RT_CONTROL), 1);
582
583 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
584 PUSH_DATAh(push, buf->address + offset);
585 PUSH_DATA (push, buf->address + offset);
586 PUSH_DATA (push, align(width * data_size, 0x100));
587 PUSH_DATA (push, height);
588 PUSH_DATA (push, nvc0_format_table[dst_fmt].rt);
589 PUSH_DATA (push, NVC0_3D_RT_TILE_MODE_LINEAR);
590 PUSH_DATA (push, 1);
591 PUSH_DATA (push, 0);
592 PUSH_DATA (push, 0);
593
594 IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0);
595 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 0);
596
597 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
598
599 IMMED_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 0x3c);
600
601 IMMED_NVC0(push, NVC0_3D(COND_MODE), nvc0->cond_condmode);
602
603 if (buf->mm) {
604 nouveau_fence_ref(nvc0->screen->base.fence.current, &buf->fence);
605 nouveau_fence_ref(nvc0->screen->base.fence.current, &buf->fence_wr);
606 }
607
608 if (width * height != elements) {
609 offset += width * height * data_size;
610 width = elements - width * height;
611 nvc0_clear_buffer_push(pipe, res, offset, width * data_size,
612 data, data_size);
613 }
614
615 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER;
616 }
617
618 static void
nvc0_clear_depth_stencil(struct pipe_context * pipe,struct pipe_surface * dst,unsigned clear_flags,double depth,unsigned stencil,unsigned dstx,unsigned dsty,unsigned width,unsigned height,bool render_condition_enabled)619 nvc0_clear_depth_stencil(struct pipe_context *pipe,
620 struct pipe_surface *dst,
621 unsigned clear_flags,
622 double depth,
623 unsigned stencil,
624 unsigned dstx, unsigned dsty,
625 unsigned width, unsigned height,
626 bool render_condition_enabled)
627 {
628 struct nvc0_context *nvc0 = nvc0_context(pipe);
629 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
630 struct nv50_miptree *mt = nv50_miptree(dst->texture);
631 struct nv50_surface *sf = nv50_surface(dst);
632 uint32_t mode = 0;
633 int unk = mt->base.base.target == PIPE_TEXTURE_2D;
634 unsigned z;
635
636 assert(dst->texture->target != PIPE_BUFFER);
637
638 if (!PUSH_SPACE(push, 32 + sf->depth))
639 return;
640
641 PUSH_REFN (push, mt->base.bo, mt->base.domain | NOUVEAU_BO_WR);
642
643 if (clear_flags & PIPE_CLEAR_DEPTH) {
644 BEGIN_NVC0(push, NVC0_3D(CLEAR_DEPTH), 1);
645 PUSH_DATAf(push, depth);
646 mode |= NVC0_3D_CLEAR_BUFFERS_Z;
647 }
648
649 if (clear_flags & PIPE_CLEAR_STENCIL) {
650 BEGIN_NVC0(push, NVC0_3D(CLEAR_STENCIL), 1);
651 PUSH_DATA (push, stencil & 0xff);
652 mode |= NVC0_3D_CLEAR_BUFFERS_S;
653 }
654
655 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
656 PUSH_DATA (push, ( width << 16) | dstx);
657 PUSH_DATA (push, (height << 16) | dsty);
658
659 BEGIN_NVC0(push, NVC0_3D(ZETA_ADDRESS_HIGH), 5);
660 PUSH_DATAh(push, mt->base.address + sf->offset);
661 PUSH_DATA (push, mt->base.address + sf->offset);
662 PUSH_DATA (push, nvc0_format_table[dst->format].rt);
663 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
664 PUSH_DATA (push, mt->layer_stride >> 2);
665 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
666 PUSH_DATA (push, 1);
667 BEGIN_NVC0(push, NVC0_3D(ZETA_HORIZ), 3);
668 PUSH_DATA (push, sf->width);
669 PUSH_DATA (push, sf->height);
670 PUSH_DATA (push, (unk << 16) | (dst->u.tex.first_layer + sf->depth));
671 BEGIN_NVC0(push, NVC0_3D(ZETA_BASE_LAYER), 1);
672 PUSH_DATA (push, dst->u.tex.first_layer);
673 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), mt->ms_mode);
674
675 if (!render_condition_enabled)
676 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
677
678 BEGIN_NIC0(push, NVC0_3D(CLEAR_BUFFERS), sf->depth);
679 for (z = 0; z < sf->depth; ++z) {
680 PUSH_DATA (push, mode |
681 (z << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
682 }
683
684 if (!render_condition_enabled)
685 IMMED_NVC0(push, NVC0_3D(COND_MODE), nvc0->cond_condmode);
686
687 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER;
688 }
689
690 void
nvc0_clear(struct pipe_context * pipe,unsigned buffers,const union pipe_color_union * color,double depth,unsigned stencil)691 nvc0_clear(struct pipe_context *pipe, unsigned buffers,
692 const union pipe_color_union *color,
693 double depth, unsigned stencil)
694 {
695 struct nvc0_context *nvc0 = nvc0_context(pipe);
696 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
697 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
698 unsigned i, j, k;
699 uint32_t mode = 0;
700
701 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
702 if (!nvc0_state_validate_3d(nvc0, NVC0_NEW_3D_FRAMEBUFFER))
703 return;
704
705 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
706 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
707 PUSH_DATAf(push, color->f[0]);
708 PUSH_DATAf(push, color->f[1]);
709 PUSH_DATAf(push, color->f[2]);
710 PUSH_DATAf(push, color->f[3]);
711 if (buffers & PIPE_CLEAR_COLOR0)
712 mode =
713 NVC0_3D_CLEAR_BUFFERS_R | NVC0_3D_CLEAR_BUFFERS_G |
714 NVC0_3D_CLEAR_BUFFERS_B | NVC0_3D_CLEAR_BUFFERS_A;
715 }
716
717 if (buffers & PIPE_CLEAR_DEPTH) {
718 BEGIN_NVC0(push, NVC0_3D(CLEAR_DEPTH), 1);
719 PUSH_DATA (push, fui(depth));
720 mode |= NVC0_3D_CLEAR_BUFFERS_Z;
721 }
722
723 if (buffers & PIPE_CLEAR_STENCIL) {
724 BEGIN_NVC0(push, NVC0_3D(CLEAR_STENCIL), 1);
725 PUSH_DATA (push, stencil & 0xff);
726 mode |= NVC0_3D_CLEAR_BUFFERS_S;
727 }
728
729 if (mode) {
730 int zs_layers = 0, color0_layers = 0;
731 if (fb->cbufs[0] && (mode & 0x3c))
732 color0_layers = fb->cbufs[0]->u.tex.last_layer -
733 fb->cbufs[0]->u.tex.first_layer + 1;
734 if (fb->zsbuf && (mode & ~0x3c))
735 zs_layers = fb->zsbuf->u.tex.last_layer -
736 fb->zsbuf->u.tex.first_layer + 1;
737
738 for (j = 0; j < MIN2(zs_layers, color0_layers); j++) {
739 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
740 PUSH_DATA(push, mode | (j << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
741 }
742 for (k = j; k < zs_layers; k++) {
743 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
744 PUSH_DATA(push, (mode & ~0x3c) | (k << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
745 }
746 for (k = j; k < color0_layers; k++) {
747 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
748 PUSH_DATA(push, (mode & 0x3c) | (k << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
749 }
750 }
751
752 for (i = 1; i < fb->nr_cbufs; i++) {
753 struct pipe_surface *sf = fb->cbufs[i];
754 if (!sf || !(buffers & (PIPE_CLEAR_COLOR0 << i)))
755 continue;
756 for (j = 0; j <= sf->u.tex.last_layer - sf->u.tex.first_layer; j++) {
757 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
758 PUSH_DATA (push, (i << 6) | 0x3c |
759 (j << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
760 }
761 }
762 }
763
764
765 /* =============================== BLIT CODE ===================================
766 */
767
768 struct nvc0_blitter
769 {
770 struct nvc0_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
771 struct nvc0_program vp;
772
773 struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
774
775 mtx_t mutex;
776
777 struct nvc0_screen *screen;
778 };
779
780 struct nvc0_blitctx
781 {
782 struct nvc0_context *nvc0;
783 struct nvc0_program *fp;
784 uint8_t mode;
785 uint16_t color_mask;
786 uint8_t filter;
787 uint8_t render_condition_enable;
788 enum pipe_texture_target target;
789 struct {
790 struct pipe_framebuffer_state fb;
791 struct nvc0_window_rect_stateobj window_rect;
792 struct nvc0_rasterizer_stateobj *rast;
793 struct nvc0_program *vp;
794 struct nvc0_program *tcp;
795 struct nvc0_program *tep;
796 struct nvc0_program *gp;
797 struct nvc0_program *fp;
798 unsigned num_textures[5];
799 unsigned num_samplers[5];
800 struct pipe_sampler_view *texture[2];
801 struct nv50_tsc_entry *sampler[2];
802 unsigned min_samples;
803 uint32_t dirty_3d;
804 } saved;
805 struct nvc0_rasterizer_stateobj rast;
806 };
807
808 static void
nvc0_blitter_make_vp(struct nvc0_blitter * blit)809 nvc0_blitter_make_vp(struct nvc0_blitter *blit)
810 {
811 static const uint32_t code_nvc0[] =
812 {
813 0xfff11c26, 0x06000080, /* vfetch b64 $r4:$r5 a[0x80] */
814 0xfff01c46, 0x06000090, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
815 0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
816 0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
817 0x00001de7, 0x80000000, /* exit */
818 };
819 static const uint32_t code_nve4[] =
820 {
821 0x00000007, 0x20000000, /* sched */
822 0xfff11c26, 0x06000080, /* vfetch b64 $r4:$r5 a[0x80] */
823 0xfff01c46, 0x06000090, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
824 0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
825 0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
826 0x00001de7, 0x80000000, /* exit */
827 };
828 static const uint32_t code_gk110[] =
829 {
830 0x00000000, 0x08000000, /* sched */
831 0x401ffc12, 0x7ec7fc00, /* ld b64 $r4d a[0x80] 0x0 0x0 */
832 0x481ffc02, 0x7ecbfc00, /* ld b96 $r0t a[0x90] 0x0 0x0 */
833 0x381ffc12, 0x7f07fc00, /* st b64 a[0x70] $r4d 0x0 0x0 */
834 0x401ffc02, 0x7f0bfc00, /* st b96 a[0x80] $r0t 0x0 0x0 */
835 0x001c003c, 0x18000000, /* exit */
836 };
837 static const uint32_t code_gm107[] =
838 {
839 0xe4200701, 0x001d0400, /* sched (st 0x1 wr 0x0) (st 0x1 wr 0x1) (st 0x1 wr 0x2) */
840 0x0807ff00, 0xefd87f80, /* ld b32 $r0 a[0x80] 0x0 */
841 0x0847ff01, 0xefd87f80, /* ld b32 $r1 a[0x84] 0x0 */
842 0x0907ff02, 0xefd87f80, /* ld b32 $r2 a[0x90] 0x0 */
843 0xf0200761, 0x003f8400, /* sched (st 0x1 wr 0x3) (st 0x1 wr 0x4) (st 0x1 wt 0x1) */
844 0x0947ff03, 0xefd87f80, /* ld b32 $r3 a[0x94] 0x0 */
845 0x0987ff04, 0xefd87f80, /* ld b32 $r4 a[0x98] 0x0 */
846 0x0707ff00, 0xeff07f80, /* st b32 a[0x70] $r0 0x0 */
847 0xfc2017e1, 0x011f8404, /* sched (st 0x1 wt 0x2) (st 0x1 wt 0x4) (st 0x1 wt 0x8) */
848 0x0747ff01, 0xeff07f80, /* st b32 a[0x74] $r1 0x0 */
849 0x0807ff02, 0xeff07f80, /* st b32 a[0x80] $r2 0x0 */
850 0x0847ff03, 0xeff07f80, /* st b32 a[0x84] $r3 0x0 */
851 0xfde087e1, 0x001f8000, /* sched (st 0x1 wt 0x10) (st 0xf) (st 0x0) */
852 0x0887ff04, 0xeff07f80, /* st b32 a[0x88] $r4 0x0 */
853 0x0007000f, 0xe3000000, /* exit */
854 };
855
856 blit->vp.type = PIPE_SHADER_VERTEX;
857 blit->vp.translated = true;
858 if (blit->screen->base.class_3d >= GM107_3D_CLASS) {
859 blit->vp.code = (uint32_t *)code_gm107; /* const_cast */
860 blit->vp.code_size = sizeof(code_gm107);
861 } else
862 if (blit->screen->base.class_3d >= NVF0_3D_CLASS) {
863 blit->vp.code = (uint32_t *)code_gk110; /* const_cast */
864 blit->vp.code_size = sizeof(code_gk110);
865 } else
866 if (blit->screen->base.class_3d >= NVE4_3D_CLASS) {
867 blit->vp.code = (uint32_t *)code_nve4; /* const_cast */
868 blit->vp.code_size = sizeof(code_nve4);
869 } else {
870 blit->vp.code = (uint32_t *)code_nvc0; /* const_cast */
871 blit->vp.code_size = sizeof(code_nvc0);
872 }
873 blit->vp.num_gprs = 6;
874 blit->vp.vp.edgeflag = PIPE_MAX_ATTRIBS;
875
876 blit->vp.hdr[0] = 0x00020461; /* vertprog magic */
877 blit->vp.hdr[4] = 0x000ff000; /* no outputs read */
878 blit->vp.hdr[6] = 0x00000073; /* a[0x80].xy, a[0x90].xyz */
879 blit->vp.hdr[13] = 0x00073000; /* o[0x70].xy, o[0x80].xyz */
880 }
881
882 static void
nvc0_blitter_make_sampler(struct nvc0_blitter * blit)883 nvc0_blitter_make_sampler(struct nvc0_blitter *blit)
884 {
885 /* clamp to edge, min/max lod = 0, nearest filtering */
886
887 blit->sampler[0].id = -1;
888
889 blit->sampler[0].tsc[0] = G80_TSC_0_SRGB_CONVERSION |
890 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_U__SHIFT) |
891 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_V__SHIFT) |
892 (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_P__SHIFT);
893 blit->sampler[0].tsc[1] =
894 G80_TSC_1_MAG_FILTER_NEAREST |
895 G80_TSC_1_MIN_FILTER_NEAREST |
896 G80_TSC_1_MIP_FILTER_NONE;
897
898 /* clamp to edge, min/max lod = 0, bilinear filtering */
899
900 blit->sampler[1].id = -1;
901
902 blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
903 blit->sampler[1].tsc[1] =
904 G80_TSC_1_MAG_FILTER_LINEAR |
905 G80_TSC_1_MIN_FILTER_LINEAR |
906 G80_TSC_1_MIP_FILTER_NONE;
907 }
908
909 static void
nvc0_blit_select_fp(struct nvc0_blitctx * ctx,const struct pipe_blit_info * info)910 nvc0_blit_select_fp(struct nvc0_blitctx *ctx, const struct pipe_blit_info *info)
911 {
912 struct nvc0_blitter *blitter = ctx->nvc0->screen->blitter;
913
914 const enum pipe_texture_target ptarg =
915 nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
916
917 const unsigned targ = nv50_blit_texture_type(ptarg);
918 const unsigned mode = ctx->mode;
919
920 if (!blitter->fp[targ][mode]) {
921 mtx_lock(&blitter->mutex);
922 if (!blitter->fp[targ][mode])
923 blitter->fp[targ][mode] =
924 nv50_blitter_make_fp(&ctx->nvc0->base.pipe, mode, ptarg);
925 mtx_unlock(&blitter->mutex);
926 }
927 ctx->fp = blitter->fp[targ][mode];
928 }
929
930 static void
nvc0_blit_set_dst(struct nvc0_blitctx * ctx,struct pipe_resource * res,unsigned level,unsigned layer,enum pipe_format format)931 nvc0_blit_set_dst(struct nvc0_blitctx *ctx,
932 struct pipe_resource *res, unsigned level, unsigned layer,
933 enum pipe_format format)
934 {
935 struct nvc0_context *nvc0 = ctx->nvc0;
936 struct pipe_context *pipe = &nvc0->base.pipe;
937 struct pipe_surface templ;
938
939 if (util_format_is_depth_or_stencil(format))
940 templ.format = nv50_blit_zeta_to_colour_format(format);
941 else
942 templ.format = format;
943
944 templ.u.tex.level = level;
945 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
946
947 if (layer == -1) {
948 templ.u.tex.first_layer = 0;
949 templ.u.tex.last_layer =
950 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
951 }
952
953 nvc0->framebuffer.cbufs[0] = nvc0_miptree_surface_new(pipe, res, &templ);
954 nvc0->framebuffer.nr_cbufs = 1;
955 nvc0->framebuffer.zsbuf = NULL;
956 nvc0->framebuffer.width = nvc0->framebuffer.cbufs[0]->width;
957 nvc0->framebuffer.height = nvc0->framebuffer.cbufs[0]->height;
958 }
959
960 static void
nvc0_blit_set_src(struct nvc0_blitctx * ctx,struct pipe_resource * res,unsigned level,unsigned layer,enum pipe_format format,const uint8_t filter)961 nvc0_blit_set_src(struct nvc0_blitctx *ctx,
962 struct pipe_resource *res, unsigned level, unsigned layer,
963 enum pipe_format format, const uint8_t filter)
964 {
965 struct nvc0_context *nvc0 = ctx->nvc0;
966 struct pipe_context *pipe = &nvc0->base.pipe;
967 struct pipe_sampler_view templ;
968 uint32_t flags;
969 unsigned s;
970 enum pipe_texture_target target;
971
972 target = nv50_blit_reinterpret_pipe_texture_target(res->target);
973
974 templ.format = format;
975 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
976 templ.u.tex.first_level = templ.u.tex.last_level = level;
977 templ.swizzle_r = PIPE_SWIZZLE_X;
978 templ.swizzle_g = PIPE_SWIZZLE_Y;
979 templ.swizzle_b = PIPE_SWIZZLE_Z;
980 templ.swizzle_a = PIPE_SWIZZLE_W;
981
982 if (layer == -1) {
983 templ.u.tex.first_layer = 0;
984 templ.u.tex.last_layer =
985 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
986 }
987
988 flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
989 flags |= NV50_TEXVIEW_ACCESS_RESOLVE;
990 if (filter && res->nr_samples == 8)
991 flags |= NV50_TEXVIEW_FILTER_MSAA8;
992
993 nvc0->textures[4][0] = nvc0_create_texture_view(
994 pipe, res, &templ, flags, target);
995 nvc0->textures[4][1] = NULL;
996
997 for (s = 0; s <= 3; ++s)
998 nvc0->num_textures[s] = 0;
999 nvc0->num_textures[4] = 1;
1000
1001 templ.format = nv50_zs_to_s_format(format);
1002 if (templ.format != format) {
1003 nvc0->textures[4][1] = nvc0_create_texture_view(
1004 pipe, res, &templ, flags, target);
1005 nvc0->num_textures[4] = 2;
1006 }
1007 }
1008
1009 static void
nvc0_blitctx_prepare_state(struct nvc0_blitctx * blit)1010 nvc0_blitctx_prepare_state(struct nvc0_blitctx *blit)
1011 {
1012 struct nouveau_pushbuf *push = blit->nvc0->base.pushbuf;
1013
1014 /* TODO: maybe make this a MACRO (if we need more logic) ? */
1015
1016 if (blit->nvc0->cond_query && !blit->render_condition_enable)
1017 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
1018
1019 /* blend state */
1020 BEGIN_NVC0(push, NVC0_3D(COLOR_MASK(0)), 1);
1021 PUSH_DATA (push, blit->color_mask);
1022 IMMED_NVC0(push, NVC0_3D(BLEND_ENABLE(0)), 0);
1023 IMMED_NVC0(push, NVC0_3D(LOGIC_OP_ENABLE), 0);
1024
1025 /* rasterizer state */
1026 IMMED_NVC0(push, NVC0_3D(FRAG_COLOR_CLAMP_EN), 0);
1027 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 0);
1028 BEGIN_NVC0(push, NVC0_3D(MSAA_MASK(0)), 4);
1029 PUSH_DATA (push, 0xffff);
1030 PUSH_DATA (push, 0xffff);
1031 PUSH_DATA (push, 0xffff);
1032 PUSH_DATA (push, 0xffff);
1033 BEGIN_NVC0(push, NVC0_3D(MACRO_POLYGON_MODE_FRONT), 1);
1034 PUSH_DATA (push, NVC0_3D_MACRO_POLYGON_MODE_FRONT_FILL);
1035 BEGIN_NVC0(push, NVC0_3D(MACRO_POLYGON_MODE_BACK), 1);
1036 PUSH_DATA (push, NVC0_3D_MACRO_POLYGON_MODE_BACK_FILL);
1037 IMMED_NVC0(push, NVC0_3D(POLYGON_SMOOTH_ENABLE), 0);
1038 IMMED_NVC0(push, NVC0_3D(POLYGON_OFFSET_FILL_ENABLE), 0);
1039 IMMED_NVC0(push, NVC0_3D(POLYGON_STIPPLE_ENABLE), 0);
1040 IMMED_NVC0(push, NVC0_3D(CULL_FACE_ENABLE), 0);
1041
1042 /* zsa state */
1043 IMMED_NVC0(push, NVC0_3D(DEPTH_TEST_ENABLE), 0);
1044 IMMED_NVC0(push, NVC0_3D(DEPTH_BOUNDS_EN), 0);
1045 IMMED_NVC0(push, NVC0_3D(STENCIL_ENABLE), 0);
1046 IMMED_NVC0(push, NVC0_3D(ALPHA_TEST_ENABLE), 0);
1047
1048 /* disable transform feedback */
1049 IMMED_NVC0(push, NVC0_3D(TFB_ENABLE), 0);
1050 }
1051
1052 static void
nvc0_blitctx_pre_blit(struct nvc0_blitctx * ctx,const struct pipe_blit_info * info)1053 nvc0_blitctx_pre_blit(struct nvc0_blitctx *ctx,
1054 const struct pipe_blit_info *info)
1055 {
1056 struct nvc0_context *nvc0 = ctx->nvc0;
1057 struct nvc0_blitter *blitter = nvc0->screen->blitter;
1058 int s;
1059
1060 ctx->saved.fb.width = nvc0->framebuffer.width;
1061 ctx->saved.fb.height = nvc0->framebuffer.height;
1062 ctx->saved.fb.samples = nvc0->framebuffer.samples;
1063 ctx->saved.fb.layers = nvc0->framebuffer.layers;
1064 ctx->saved.fb.nr_cbufs = nvc0->framebuffer.nr_cbufs;
1065 ctx->saved.fb.cbufs[0] = nvc0->framebuffer.cbufs[0];
1066 ctx->saved.fb.zsbuf = nvc0->framebuffer.zsbuf;
1067
1068 ctx->saved.rast = nvc0->rast;
1069
1070 ctx->saved.vp = nvc0->vertprog;
1071 ctx->saved.tcp = nvc0->tctlprog;
1072 ctx->saved.tep = nvc0->tevlprog;
1073 ctx->saved.gp = nvc0->gmtyprog;
1074 ctx->saved.fp = nvc0->fragprog;
1075
1076 ctx->saved.min_samples = nvc0->min_samples;
1077 ctx->saved.window_rect = nvc0->window_rect;
1078
1079 nvc0->rast = &ctx->rast;
1080
1081 nvc0->vertprog = &blitter->vp;
1082 nvc0->tctlprog = NULL;
1083 nvc0->tevlprog = NULL;
1084 nvc0->gmtyprog = NULL;
1085 nvc0->fragprog = ctx->fp;
1086
1087 nvc0->window_rect.rects =
1088 MIN2(info->num_window_rectangles, NVC0_MAX_WINDOW_RECTANGLES);
1089 nvc0->window_rect.inclusive = info->window_rectangle_include;
1090 if (nvc0->window_rect.rects)
1091 memcpy(nvc0->window_rect.rect, info->window_rectangles,
1092 sizeof(struct pipe_scissor_state) * nvc0->window_rect.rects);
1093
1094 for (s = 0; s <= 4; ++s) {
1095 ctx->saved.num_textures[s] = nvc0->num_textures[s];
1096 ctx->saved.num_samplers[s] = nvc0->num_samplers[s];
1097 nvc0->textures_dirty[s] = (1 << nvc0->num_textures[s]) - 1;
1098 nvc0->samplers_dirty[s] = (1 << nvc0->num_samplers[s]) - 1;
1099 }
1100 ctx->saved.texture[0] = nvc0->textures[4][0];
1101 ctx->saved.texture[1] = nvc0->textures[4][1];
1102 ctx->saved.sampler[0] = nvc0->samplers[4][0];
1103 ctx->saved.sampler[1] = nvc0->samplers[4][1];
1104
1105 nvc0->samplers[4][0] = &blitter->sampler[ctx->filter];
1106 nvc0->samplers[4][1] = &blitter->sampler[ctx->filter];
1107
1108 for (s = 0; s <= 3; ++s)
1109 nvc0->num_samplers[s] = 0;
1110 nvc0->num_samplers[4] = 2;
1111
1112 nvc0->min_samples = 1;
1113
1114 ctx->saved.dirty_3d = nvc0->dirty_3d;
1115
1116 nvc0->textures_dirty[4] |= 3;
1117 nvc0->samplers_dirty[4] |= 3;
1118
1119 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
1120 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(4, 0));
1121 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(4, 1));
1122
1123 nvc0->dirty_3d = NVC0_NEW_3D_FRAMEBUFFER | NVC0_NEW_3D_MIN_SAMPLES |
1124 NVC0_NEW_3D_VERTPROG | NVC0_NEW_3D_FRAGPROG |
1125 NVC0_NEW_3D_TCTLPROG | NVC0_NEW_3D_TEVLPROG | NVC0_NEW_3D_GMTYPROG |
1126 NVC0_NEW_3D_TEXTURES | NVC0_NEW_3D_SAMPLERS | NVC0_NEW_3D_WINDOW_RECTS;
1127 }
1128
1129 static void
nvc0_blitctx_post_blit(struct nvc0_blitctx * blit)1130 nvc0_blitctx_post_blit(struct nvc0_blitctx *blit)
1131 {
1132 struct nvc0_context *nvc0 = blit->nvc0;
1133 int s;
1134
1135 pipe_surface_reference(&nvc0->framebuffer.cbufs[0], NULL);
1136
1137 nvc0->framebuffer.width = blit->saved.fb.width;
1138 nvc0->framebuffer.height = blit->saved.fb.height;
1139 nvc0->framebuffer.samples = blit->saved.fb.samples;
1140 nvc0->framebuffer.layers = blit->saved.fb.layers;
1141 nvc0->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
1142 nvc0->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
1143 nvc0->framebuffer.zsbuf = blit->saved.fb.zsbuf;
1144
1145 nvc0->rast = blit->saved.rast;
1146
1147 nvc0->vertprog = blit->saved.vp;
1148 nvc0->tctlprog = blit->saved.tcp;
1149 nvc0->tevlprog = blit->saved.tep;
1150 nvc0->gmtyprog = blit->saved.gp;
1151 nvc0->fragprog = blit->saved.fp;
1152
1153 nvc0->min_samples = blit->saved.min_samples;
1154 nvc0->window_rect = blit->saved.window_rect;
1155
1156 pipe_sampler_view_reference(&nvc0->textures[4][0], NULL);
1157 pipe_sampler_view_reference(&nvc0->textures[4][1], NULL);
1158
1159 for (s = 0; s <= 4; ++s) {
1160 nvc0->num_textures[s] = blit->saved.num_textures[s];
1161 nvc0->num_samplers[s] = blit->saved.num_samplers[s];
1162 nvc0->textures_dirty[s] = (1 << nvc0->num_textures[s]) - 1;
1163 nvc0->samplers_dirty[s] = (1 << nvc0->num_samplers[s]) - 1;
1164 }
1165 nvc0->textures[4][0] = blit->saved.texture[0];
1166 nvc0->textures[4][1] = blit->saved.texture[1];
1167 nvc0->samplers[4][0] = blit->saved.sampler[0];
1168 nvc0->samplers[4][1] = blit->saved.sampler[1];
1169
1170 nvc0->textures_dirty[4] |= 3;
1171 nvc0->samplers_dirty[4] |= 3;
1172
1173 if (nvc0->cond_query && !blit->render_condition_enable)
1174 nvc0->base.pipe.render_condition(&nvc0->base.pipe, nvc0->cond_query,
1175 nvc0->cond_cond, nvc0->cond_mode);
1176
1177 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX_TMP);
1178 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
1179 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(4, 0));
1180 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(4, 1));
1181 nouveau_scratch_done(&nvc0->base);
1182
1183 nvc0->dirty_3d = blit->saved.dirty_3d |
1184 (NVC0_NEW_3D_FRAMEBUFFER | NVC0_NEW_3D_SCISSOR | NVC0_NEW_3D_SAMPLE_MASK |
1185 NVC0_NEW_3D_RASTERIZER | NVC0_NEW_3D_ZSA | NVC0_NEW_3D_BLEND |
1186 NVC0_NEW_3D_VIEWPORT | NVC0_NEW_3D_WINDOW_RECTS |
1187 NVC0_NEW_3D_TEXTURES | NVC0_NEW_3D_SAMPLERS |
1188 NVC0_NEW_3D_VERTPROG | NVC0_NEW_3D_FRAGPROG |
1189 NVC0_NEW_3D_TCTLPROG | NVC0_NEW_3D_TEVLPROG | NVC0_NEW_3D_GMTYPROG |
1190 NVC0_NEW_3D_TFB_TARGETS | NVC0_NEW_3D_VERTEX | NVC0_NEW_3D_ARRAYS);
1191 nvc0->scissors_dirty |= 1;
1192 nvc0->viewports_dirty |= 1;
1193
1194 nvc0->base.pipe.set_min_samples(&nvc0->base.pipe, blit->saved.min_samples);
1195 }
1196
1197 static void
nvc0_blit_3d(struct nvc0_context * nvc0,const struct pipe_blit_info * info)1198 nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
1199 {
1200 struct nvc0_blitctx *blit = nvc0->blit;
1201 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1202 struct pipe_resource *src = info->src.resource;
1203 struct pipe_resource *dst = info->dst.resource;
1204 struct nouveau_bo *vtxbuf_bo;
1205 uint32_t stride, length, *vbuf;
1206 uint64_t vtxbuf;
1207 int32_t minx, maxx, miny, maxy;
1208 int32_t i, n;
1209 float x0, x1, y0, y1, z;
1210 float dz;
1211 float x_range, y_range;
1212
1213 blit->mode = nv50_blit_select_mode(info);
1214 blit->color_mask = nv50_blit_derive_color_mask(info);
1215 blit->filter = nv50_blit_get_filter(info);
1216 blit->render_condition_enable = info->render_condition_enable;
1217
1218 nvc0_blit_select_fp(blit, info);
1219 nvc0_blitctx_pre_blit(blit, info);
1220
1221 nvc0_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
1222 nvc0_blit_set_src(blit, src, info->src.level, -1, info->src.format,
1223 blit->filter);
1224
1225 nvc0_blitctx_prepare_state(blit);
1226
1227 nvc0_state_validate_3d(nvc0, ~0);
1228
1229 x_range = (float)info->src.box.width / (float)info->dst.box.width;
1230 y_range = (float)info->src.box.height / (float)info->dst.box.height;
1231
1232 x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
1233 y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
1234
1235 x1 = x0 + 32768.0f * x_range;
1236 y1 = y0 + 32768.0f * y_range;
1237
1238 x0 *= (float)(1 << nv50_miptree(src)->ms_x);
1239 x1 *= (float)(1 << nv50_miptree(src)->ms_x);
1240 y0 *= (float)(1 << nv50_miptree(src)->ms_y);
1241 y1 *= (float)(1 << nv50_miptree(src)->ms_y);
1242
1243 dz = (float)info->src.box.depth / (float)info->dst.box.depth;
1244 z = (float)info->src.box.z;
1245 if (nv50_miptree(src)->layout_3d)
1246 z += 0.5f * dz;
1247
1248 if (src->last_level > 0) {
1249 /* If there are mip maps, GPU always assumes normalized coordinates. */
1250 const unsigned l = info->src.level;
1251 const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
1252 const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
1253 x0 /= fh;
1254 x1 /= fh;
1255 y0 /= fv;
1256 y1 /= fv;
1257 if (nv50_miptree(src)->layout_3d) {
1258 z /= u_minify(src->depth0, l);
1259 dz /= u_minify(src->depth0, l);
1260 }
1261 }
1262
1263 IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 0);
1264 IMMED_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 0x2 |
1265 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_RANGE_0_1);
1266 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
1267 PUSH_DATA (push, nvc0->framebuffer.width << 16);
1268 PUSH_DATA (push, nvc0->framebuffer.height << 16);
1269
1270 /* Draw a large triangle in screen coordinates covering the whole
1271 * render target, with scissors defining the destination region.
1272 * The vertex is supplied with non-normalized texture coordinates
1273 * arranged in a way to yield the desired offset and scale.
1274 */
1275
1276 minx = info->dst.box.x;
1277 maxx = info->dst.box.x + info->dst.box.width;
1278 miny = info->dst.box.y;
1279 maxy = info->dst.box.y + info->dst.box.height;
1280 if (info->scissor_enable) {
1281 minx = MAX2(minx, info->scissor.minx);
1282 maxx = MIN2(maxx, info->scissor.maxx);
1283 miny = MAX2(miny, info->scissor.miny);
1284 maxy = MIN2(maxy, info->scissor.maxy);
1285 }
1286 BEGIN_NVC0(push, NVC0_3D(SCISSOR_HORIZ(0)), 2);
1287 PUSH_DATA (push, (maxx << 16) | minx);
1288 PUSH_DATA (push, (maxy << 16) | miny);
1289
1290 stride = (3 + 2) * 4;
1291 length = stride * 3 * info->dst.box.depth;
1292
1293 vbuf = nouveau_scratch_get(&nvc0->base, length, &vtxbuf, &vtxbuf_bo);
1294 if (!vbuf) {
1295 assert(vbuf);
1296 return;
1297 }
1298
1299 BCTX_REFN_bo(nvc0->bufctx_3d, 3D_VTX_TMP,
1300 NOUVEAU_BO_GART | NOUVEAU_BO_RD, vtxbuf_bo);
1301 nouveau_pushbuf_validate(push);
1302
1303 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(0)), 4);
1304 PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | stride <<
1305 NVC0_3D_VERTEX_ARRAY_FETCH_STRIDE__SHIFT);
1306 PUSH_DATAh(push, vtxbuf);
1307 PUSH_DATA (push, vtxbuf);
1308 PUSH_DATA (push, 0);
1309 BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(0)), 2);
1310 PUSH_DATAh(push, vtxbuf + length - 1);
1311 PUSH_DATA (push, vtxbuf + length - 1);
1312
1313 n = MAX2(2, nvc0->state.num_vtxelts);
1314
1315 BEGIN_NVC0(push, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n);
1316 PUSH_DATA (push, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |
1317 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32_32 | 0x00 <<
1318 NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT);
1319 PUSH_DATA (push, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |
1320 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32_32_32 | 0x08 <<
1321 NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT);
1322 for (i = 2; i < n; i++) {
1323 PUSH_DATA(push, NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |
1324 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 |
1325 NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST);
1326 }
1327 for (i = 1; i < n; ++i)
1328 IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
1329 if (nvc0->state.instance_elts) {
1330 nvc0->state.instance_elts = 0;
1331 BEGIN_NVC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_PER_INSTANCE), 2);
1332 PUSH_DATA (push, n);
1333 PUSH_DATA (push, 0);
1334 }
1335 nvc0->state.num_vtxelts = 2;
1336
1337 if (nvc0->state.prim_restart) {
1338 IMMED_NVC0(push, NVC0_3D(PRIM_RESTART_ENABLE), 0);
1339 nvc0->state.prim_restart = 0;
1340 }
1341
1342 if (nvc0->state.index_bias) {
1343 IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
1344 IMMED_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 0);
1345 nvc0->state.index_bias = 0;
1346 }
1347
1348 for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
1349 if (info->dst.box.z + i) {
1350 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1351 PUSH_DATA (push, info->dst.box.z + i);
1352 }
1353
1354 *(vbuf++) = fui(0.0f);
1355 *(vbuf++) = fui(0.0f);
1356 *(vbuf++) = fui(x0);
1357 *(vbuf++) = fui(y0);
1358 *(vbuf++) = fui(z);
1359
1360 *(vbuf++) = fui(32768 << nv50_miptree(dst)->ms_x);
1361 *(vbuf++) = fui(0.0f);
1362 *(vbuf++) = fui(x1);
1363 *(vbuf++) = fui(y0);
1364 *(vbuf++) = fui(z);
1365
1366 *(vbuf++) = fui(0.0f);
1367 *(vbuf++) = fui(32768 << nv50_miptree(dst)->ms_y);
1368 *(vbuf++) = fui(x0);
1369 *(vbuf++) = fui(y1);
1370 *(vbuf++) = fui(z);
1371
1372 IMMED_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL),
1373 NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
1374 BEGIN_NVC0(push, NVC0_3D(VERTEX_BUFFER_FIRST), 2);
1375 PUSH_DATA (push, i * 3);
1376 PUSH_DATA (push, 3);
1377 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
1378 }
1379 if (info->dst.box.z + info->dst.box.depth - 1)
1380 IMMED_NVC0(push, NVC0_3D(LAYER), 0);
1381
1382 nvc0_blitctx_post_blit(blit);
1383
1384 /* restore viewport transform */
1385 IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1386 }
1387
1388 static void
nvc0_blit_eng2d(struct nvc0_context * nvc0,const struct pipe_blit_info * info)1389 nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
1390 {
1391 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1392 struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
1393 struct nv50_miptree *src = nv50_miptree(info->src.resource);
1394 const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
1395 const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
1396 const int dz = info->dst.box.z;
1397 const int sz = info->src.box.z;
1398 uint32_t dstw, dsth;
1399 int32_t dstx, dsty;
1400 int64_t srcx, srcy;
1401 int64_t du_dx, dv_dy;
1402 int i;
1403 uint32_t mode;
1404 uint32_t mask = nv50_blit_eng2d_get_mask(info);
1405 bool b;
1406
1407 mode = nv50_blit_get_filter(info) ?
1408 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR :
1409 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
1410 mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
1411 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER : NV50_2D_BLIT_CONTROL_ORIGIN_CENTER;
1412
1413 du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
1414 dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
1415
1416 b = info->dst.format == info->src.format;
1417 nvc0_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format, b);
1418 nvc0_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format, b);
1419
1420 if (info->scissor_enable) {
1421 BEGIN_NVC0(push, NVC0_2D(CLIP_X), 5);
1422 PUSH_DATA (push, info->scissor.minx << dst->ms_x);
1423 PUSH_DATA (push, info->scissor.miny << dst->ms_y);
1424 PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
1425 PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
1426 PUSH_DATA (push, 1); /* enable */
1427 }
1428
1429 if (nvc0->cond_query && info->render_condition_enable)
1430 IMMED_NVC0(push, NVC0_2D(COND_MODE), nvc0->cond_condmode);
1431
1432 if (mask != 0xffffffff) {
1433 IMMED_NVC0(push, NVC0_2D(ROP), 0xca); /* DPSDxax */
1434 IMMED_NVC0(push, NVC0_2D(PATTERN_COLOR_FORMAT),
1435 NV50_2D_PATTERN_COLOR_FORMAT_A8R8G8B8);
1436 BEGIN_NVC0(push, NVC0_2D(PATTERN_BITMAP_COLOR(0)), 4);
1437 PUSH_DATA (push, 0x00000000);
1438 PUSH_DATA (push, mask);
1439 PUSH_DATA (push, 0xffffffff);
1440 PUSH_DATA (push, 0xffffffff);
1441 IMMED_NVC0(push, NVC0_2D(OPERATION), NV50_2D_OPERATION_ROP);
1442 } else
1443 if (info->src.format != info->dst.format) {
1444 if (info->src.format == PIPE_FORMAT_R8_UNORM ||
1445 info->src.format == PIPE_FORMAT_R8_SNORM ||
1446 info->src.format == PIPE_FORMAT_R16_UNORM ||
1447 info->src.format == PIPE_FORMAT_R16_SNORM ||
1448 info->src.format == PIPE_FORMAT_R16_FLOAT ||
1449 info->src.format == PIPE_FORMAT_R32_FLOAT) {
1450 mask = 0xffff0000; /* also makes condition for OPERATION reset true */
1451 BEGIN_NVC0(push, NVC0_2D(BETA4), 2);
1452 PUSH_DATA (push, mask);
1453 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1454 } else
1455 if (info->src.format == PIPE_FORMAT_A8_UNORM) {
1456 mask = 0xff000000;
1457 BEGIN_NVC0(push, NVC0_2D(BETA4), 2);
1458 PUSH_DATA (push, mask);
1459 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1460 }
1461 }
1462
1463 if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
1464 /* ms_x is always >= ms_y */
1465 du_dx <<= src->ms_x - dst->ms_x;
1466 dv_dy <<= src->ms_y - dst->ms_y;
1467 } else {
1468 du_dx >>= dst->ms_x - src->ms_x;
1469 dv_dy >>= dst->ms_y - src->ms_y;
1470 }
1471
1472 srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1473 srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1474
1475 if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1476 /* center src coorinates for proper MS resolve filtering */
1477 srcx += (int64_t)1 << (src->ms_x + 31);
1478 srcy += (int64_t)1 << (src->ms_y + 31);
1479 }
1480
1481 dstx = info->dst.box.x << dst->ms_x;
1482 dsty = info->dst.box.y << dst->ms_y;
1483
1484 dstw = info->dst.box.width << dst->ms_x;
1485 dsth = info->dst.box.height << dst->ms_y;
1486
1487 if (dstx < 0) {
1488 dstw += dstx;
1489 srcx -= du_dx * dstx;
1490 dstx = 0;
1491 }
1492 if (dsty < 0) {
1493 dsth += dsty;
1494 srcy -= dv_dy * dsty;
1495 dsty = 0;
1496 }
1497
1498 IMMED_NVC0(push, NVC0_2D(BLIT_CONTROL), mode);
1499 BEGIN_NVC0(push, NVC0_2D(BLIT_DST_X), 4);
1500 PUSH_DATA (push, dstx);
1501 PUSH_DATA (push, dsty);
1502 PUSH_DATA (push, dstw);
1503 PUSH_DATA (push, dsth);
1504 BEGIN_NVC0(push, NVC0_2D(BLIT_DU_DX_FRACT), 4);
1505 PUSH_DATA (push, du_dx);
1506 PUSH_DATA (push, du_dx >> 32);
1507 PUSH_DATA (push, dv_dy);
1508 PUSH_DATA (push, dv_dy >> 32);
1509
1510 BCTX_REFN(nvc0->bufctx, 2D, &dst->base, WR);
1511 BCTX_REFN(nvc0->bufctx, 2D, &src->base, RD);
1512 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx);
1513 if (nouveau_pushbuf_validate(nvc0->base.pushbuf))
1514 return;
1515
1516 for (i = 0; i < info->dst.box.depth; ++i) {
1517 if (i > 0) {
1518 /* no scaling in z-direction possible for eng2d blits */
1519 if (dst->layout_3d) {
1520 BEGIN_NVC0(push, NVC0_2D(DST_LAYER), 1);
1521 PUSH_DATA (push, info->dst.box.z + i);
1522 } else {
1523 const unsigned z = info->dst.box.z + i;
1524 const uint64_t address = dst->base.address +
1525 dst->level[info->dst.level].offset +
1526 z * dst->layer_stride;
1527 BEGIN_NVC0(push, NVC0_2D(DST_ADDRESS_HIGH), 2);
1528 PUSH_DATAh(push, address);
1529 PUSH_DATA (push, address);
1530 }
1531 if (src->layout_3d) {
1532 /* not possible because of depth tiling */
1533 assert(0);
1534 } else {
1535 const unsigned z = info->src.box.z + i;
1536 const uint64_t address = src->base.address +
1537 src->level[info->src.level].offset +
1538 z * src->layer_stride;
1539 BEGIN_NVC0(push, NVC0_2D(SRC_ADDRESS_HIGH), 2);
1540 PUSH_DATAh(push, address);
1541 PUSH_DATA (push, address);
1542 }
1543 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1544 PUSH_DATA (push, srcy >> 32);
1545 } else {
1546 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_X_FRACT), 4);
1547 PUSH_DATA (push, srcx);
1548 PUSH_DATA (push, srcx >> 32);
1549 PUSH_DATA (push, srcy);
1550 PUSH_DATA (push, srcy >> 32);
1551 }
1552 }
1553 nvc0_resource_validate(&dst->base, NOUVEAU_BO_WR);
1554 nvc0_resource_validate(&src->base, NOUVEAU_BO_RD);
1555
1556 nouveau_bufctx_reset(nvc0->bufctx, NVC0_BIND_2D);
1557
1558 if (info->scissor_enable)
1559 IMMED_NVC0(push, NVC0_2D(CLIP_ENABLE), 0);
1560 if (mask != 0xffffffff)
1561 IMMED_NVC0(push, NVC0_2D(OPERATION), NV50_2D_OPERATION_SRCCOPY);
1562 if (nvc0->cond_query && info->render_condition_enable)
1563 IMMED_NVC0(push, NVC0_2D(COND_MODE), NV50_2D_COND_MODE_ALWAYS);
1564 }
1565
1566 static void
nvc0_blit(struct pipe_context * pipe,const struct pipe_blit_info * info)1567 nvc0_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1568 {
1569 struct nvc0_context *nvc0 = nvc0_context(pipe);
1570 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
1571 bool eng3d = false;
1572
1573 if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1574 if (!(info->mask & PIPE_MASK_ZS))
1575 return;
1576 if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1577 info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1578 eng3d = true;
1579 if (info->filter != PIPE_TEX_FILTER_NEAREST)
1580 eng3d = true;
1581 } else {
1582 if (!(info->mask & PIPE_MASK_RGBA))
1583 return;
1584 if (info->mask != PIPE_MASK_RGBA)
1585 eng3d = true;
1586 }
1587
1588 if (nv50_miptree(info->src.resource)->layout_3d) {
1589 eng3d = true;
1590 } else
1591 if (info->src.box.depth != info->dst.box.depth) {
1592 eng3d = true;
1593 debug_printf("blit: cannot filter array or cube textures in z direction");
1594 }
1595
1596 if (!eng3d && info->dst.format != info->src.format) {
1597 if (!nv50_2d_dst_format_faithful(info->dst.format)) {
1598 eng3d = true;
1599 } else
1600 if (!nv50_2d_src_format_faithful(info->src.format)) {
1601 if (!util_format_is_luminance(info->src.format)) {
1602 if (!nv50_2d_dst_format_ops_supported(info->dst.format))
1603 eng3d = true;
1604 else
1605 if (util_format_is_intensity(info->src.format))
1606 eng3d = info->src.format != PIPE_FORMAT_I8_UNORM;
1607 else
1608 if (util_format_is_alpha(info->src.format))
1609 eng3d = info->src.format != PIPE_FORMAT_A8_UNORM;
1610 else
1611 eng3d = !nv50_2d_format_supported(info->src.format);
1612 }
1613 } else
1614 if (util_format_is_luminance_alpha(info->src.format))
1615 eng3d = true;
1616 }
1617
1618 if (info->src.resource->nr_samples == 8 &&
1619 info->dst.resource->nr_samples <= 1)
1620 eng3d = true;
1621 #if 0
1622 /* FIXME: can't make this work with eng2d anymore, at least not on nv50 */
1623 if (info->src.resource->nr_samples > 1 ||
1624 info->dst.resource->nr_samples > 1)
1625 eng3d = true;
1626 #endif
1627 /* FIXME: find correct src coordinates adjustments */
1628 if ((info->src.box.width != info->dst.box.width &&
1629 info->src.box.width != -info->dst.box.width) ||
1630 (info->src.box.height != info->dst.box.height &&
1631 info->src.box.height != -info->dst.box.height))
1632 eng3d = true;
1633
1634 if (info->num_window_rectangles > 0 || info->window_rectangle_include)
1635 eng3d = true;
1636
1637 if (nvc0->screen->num_occlusion_queries_active)
1638 IMMED_NVC0(push, NVC0_3D(SAMPLECNT_ENABLE), 0);
1639
1640 if (!eng3d)
1641 nvc0_blit_eng2d(nvc0, info);
1642 else
1643 nvc0_blit_3d(nvc0, info);
1644
1645 if (nvc0->screen->num_occlusion_queries_active)
1646 IMMED_NVC0(push, NVC0_3D(SAMPLECNT_ENABLE), 1);
1647
1648 NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_blit_count, 1);
1649 }
1650
1651 static void
nvc0_flush_resource(struct pipe_context * ctx,struct pipe_resource * resource)1652 nvc0_flush_resource(struct pipe_context *ctx,
1653 struct pipe_resource *resource)
1654 {
1655 }
1656
1657 bool
nvc0_blitter_create(struct nvc0_screen * screen)1658 nvc0_blitter_create(struct nvc0_screen *screen)
1659 {
1660 screen->blitter = CALLOC_STRUCT(nvc0_blitter);
1661 if (!screen->blitter) {
1662 NOUVEAU_ERR("failed to allocate blitter struct\n");
1663 return false;
1664 }
1665 screen->blitter->screen = screen;
1666
1667 (void) mtx_init(&screen->blitter->mutex, mtx_plain);
1668
1669 nvc0_blitter_make_vp(screen->blitter);
1670 nvc0_blitter_make_sampler(screen->blitter);
1671
1672 return true;
1673 }
1674
1675 void
nvc0_blitter_destroy(struct nvc0_screen * screen)1676 nvc0_blitter_destroy(struct nvc0_screen *screen)
1677 {
1678 struct nvc0_blitter *blitter = screen->blitter;
1679 unsigned i, m;
1680
1681 for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1682 for (m = 0; m < NV50_BLIT_MODES; ++m) {
1683 struct nvc0_program *prog = blitter->fp[i][m];
1684 if (prog) {
1685 nvc0_program_destroy(NULL, prog);
1686 FREE((void *)prog->pipe.tokens);
1687 FREE(prog);
1688 }
1689 }
1690 }
1691
1692 mtx_destroy(&blitter->mutex);
1693 FREE(blitter);
1694 }
1695
1696 bool
nvc0_blitctx_create(struct nvc0_context * nvc0)1697 nvc0_blitctx_create(struct nvc0_context *nvc0)
1698 {
1699 nvc0->blit = CALLOC_STRUCT(nvc0_blitctx);
1700 if (!nvc0->blit) {
1701 NOUVEAU_ERR("failed to allocate blit context\n");
1702 return false;
1703 }
1704
1705 nvc0->blit->nvc0 = nvc0;
1706
1707 nvc0->blit->rast.pipe.half_pixel_center = 1;
1708
1709 return true;
1710 }
1711
1712 void
nvc0_blitctx_destroy(struct nvc0_context * nvc0)1713 nvc0_blitctx_destroy(struct nvc0_context *nvc0)
1714 {
1715 FREE(nvc0->blit);
1716 }
1717
1718 void
nvc0_init_surface_functions(struct nvc0_context * nvc0)1719 nvc0_init_surface_functions(struct nvc0_context *nvc0)
1720 {
1721 struct pipe_context *pipe = &nvc0->base.pipe;
1722
1723 pipe->resource_copy_region = nvc0_resource_copy_region;
1724 pipe->blit = nvc0_blit;
1725 pipe->flush_resource = nvc0_flush_resource;
1726 pipe->clear_render_target = nvc0_clear_render_target;
1727 pipe->clear_depth_stencil = nvc0_clear_depth_stencil;
1728 pipe->clear_texture = nv50_clear_texture;
1729 pipe->clear_buffer = nvc0_clear_buffer;
1730 }
1731