1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.
4 *
5 * Interrupt support is added. Now, it has been tested
6 * on ULI1575 chip and works well with USB keyboard.
7 *
8 * (C) Copyright 2007
9 * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>
10 *
11 * (C) Copyright 2003
12 * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
13 *
14 * Note: Much of this code has been derived from Linux 2.4
15 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
16 * (C) Copyright 2000-2002 David Brownell
17 *
18 * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
19 * ebenard@eukrea.com - based on s3c24x0's driver
20 */
21 /*
22 * IMPORTANT NOTES
23 * 1 - Read doc/README.generic_usb_ohci
24 * 2 - this driver is intended for use with USB Mass Storage Devices
25 * (BBB) and USB keyboard. There is NO support for Isochronous pipes!
26 * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
27 * to activate workaround for bug #41 or this driver will NOT work!
28 */
29
30 #include <common.h>
31 #include <asm/byteorder.h>
32 #include <dm.h>
33 #include <errno.h>
34
35 #if defined(CONFIG_PCI_OHCI)
36 # include <pci.h>
37 #if !defined(CONFIG_PCI_OHCI_DEVNO)
38 #define CONFIG_PCI_OHCI_DEVNO 0
39 #endif
40 #endif
41
42 #include <malloc.h>
43 #include <memalign.h>
44 #include <usb.h>
45
46 #include "ohci.h"
47
48 #ifdef CONFIG_AT91RM9200
49 #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */
50 #endif
51
52 #if defined(CONFIG_CPU_ARM920T) || \
53 defined(CONFIG_PCI_OHCI) || \
54 defined(CONFIG_SYS_OHCI_USE_NPS)
55 # define OHCI_USE_NPS /* force NoPowerSwitching mode */
56 #endif
57
58 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
59 #undef DEBUG
60 #undef SHOW_INFO
61 #undef OHCI_FILL_TRACE
62
63 /* For initializing controller (mask in an HCFS mode too) */
64 #define OHCI_CONTROL_INIT \
65 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
66
67 #ifdef CONFIG_PCI_OHCI
68 static struct pci_device_id ohci_pci_ids[] = {
69 {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
70 {0x1033, 0x0035}, /* NEC PCI OHCI module ids */
71 {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */
72 /* Please add supported PCI OHCI controller ids here */
73 {0, 0}
74 };
75 #endif
76
77 #ifdef CONFIG_PCI_EHCI_DEVNO
78 static struct pci_device_id ehci_pci_ids[] = {
79 {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */
80 /* Please add supported PCI EHCI controller ids here */
81 {0, 0}
82 };
83 #endif
84
85 #ifdef DEBUG
86 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
87 #else
88 #define dbg(format, arg...) do {} while (0)
89 #endif /* DEBUG */
90 #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
91 #ifdef SHOW_INFO
92 #define info(format, arg...) printf("INFO: " format "\n", ## arg)
93 #else
94 #define info(format, arg...) do {} while (0)
95 #endif
96
97 #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER
98 # define m16_swap(x) cpu_to_be16(x)
99 # define m32_swap(x) cpu_to_be32(x)
100 #else
101 # define m16_swap(x) cpu_to_le16(x)
102 # define m32_swap(x) cpu_to_le32(x)
103 #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */
104
105 /* We really should do proper cache flushing everywhere */
106 #define flush_dcache_buffer(addr, size) \
107 flush_dcache_range((unsigned long)(addr), \
108 ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN))
109 #define invalidate_dcache_buffer(addr, size) \
110 invalidate_dcache_range((unsigned long)(addr), \
111 ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN))
112
113 /* Do not use sizeof(ed / td) as our ed / td structs contain extra members */
114 #define flush_dcache_ed(addr) flush_dcache_buffer(addr, 16)
115 #define flush_dcache_td(addr) flush_dcache_buffer(addr, 16)
116 #define flush_dcache_iso_td(addr) flush_dcache_buffer(addr, 32)
117 #define flush_dcache_hcca(addr) flush_dcache_buffer(addr, 256)
118 #define invalidate_dcache_ed(addr) invalidate_dcache_buffer(addr, 16)
119 #define invalidate_dcache_td(addr) invalidate_dcache_buffer(addr, 16)
120 #define invalidate_dcache_iso_td(addr) invalidate_dcache_buffer(addr, 32)
121 #define invalidate_dcache_hcca(addr) invalidate_dcache_buffer(addr, 256)
122
123 #ifdef CONFIG_DM_USB
124 /*
125 * The various ohci_mdelay(1) calls in the code seem unnecessary. We keep
126 * them around when building for older boards not yet converted to the dm
127 * just in case (to avoid regressions), for dm this turns them into nops.
128 */
129 #define ohci_mdelay(x)
130 #else
131 #define ohci_mdelay(x) mdelay(x)
132 #endif
133
134 #ifndef CONFIG_DM_USB
135 /* global ohci_t */
136 static ohci_t gohci;
137 /* this must be aligned to a 256 byte boundary */
138 struct ohci_hcca ghcca[1];
139 #endif
140
141 /* mapping of the OHCI CC status to error codes */
142 static int cc_to_error[16] = {
143 /* No Error */ 0,
144 /* CRC Error */ USB_ST_CRC_ERR,
145 /* Bit Stuff */ USB_ST_BIT_ERR,
146 /* Data Togg */ USB_ST_CRC_ERR,
147 /* Stall */ USB_ST_STALLED,
148 /* DevNotResp */ -1,
149 /* PIDCheck */ USB_ST_BIT_ERR,
150 /* UnExpPID */ USB_ST_BIT_ERR,
151 /* DataOver */ USB_ST_BUF_ERR,
152 /* DataUnder */ USB_ST_BUF_ERR,
153 /* reservd */ -1,
154 /* reservd */ -1,
155 /* BufferOver */ USB_ST_BUF_ERR,
156 /* BuffUnder */ USB_ST_BUF_ERR,
157 /* Not Access */ -1,
158 /* Not Access */ -1
159 };
160
161 static const char *cc_to_string[16] = {
162 "No Error",
163 "CRC: Last data packet from endpoint contained a CRC error.",
164 "BITSTUFFING: Last data packet from endpoint contained a bit " \
165 "stuffing violation",
166 "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \
167 "that did not match the expected value.",
168 "STALL: TD was moved to the Done Queue because the endpoint returned" \
169 " a STALL PID",
170 "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \
171 "not provide a handshake (OUT)",
172 "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\
173 "(IN) or handshake (OUT)",
174 "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \
175 "value is not defined.",
176 "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \
177 "either the size of the maximum data packet allowed\n" \
178 "from the endpoint (found in MaximumPacketSize field\n" \
179 "of ED) or the remaining buffer size.",
180 "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \
181 "and that amount was not sufficient to fill the\n" \
182 "specified buffer",
183 "reserved1",
184 "reserved2",
185 "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \
186 "than it could be written to system memory",
187 "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \
188 "system memory fast enough to keep up with data USB " \
189 "data rate.",
190 "NOT ACCESSED: This code is set by software before the TD is placed" \
191 "on a list to be processed by the HC.(1)",
192 "NOT ACCESSED: This code is set by software before the TD is placed" \
193 "on a list to be processed by the HC.(2)",
194 };
195
roothub_a(struct ohci * hc)196 static inline u32 roothub_a(struct ohci *hc)
197 { return ohci_readl(&hc->regs->roothub.a); }
roothub_b(struct ohci * hc)198 static inline u32 roothub_b(struct ohci *hc)
199 { return ohci_readl(&hc->regs->roothub.b); }
roothub_status(struct ohci * hc)200 static inline u32 roothub_status(struct ohci *hc)
201 { return ohci_readl(&hc->regs->roothub.status); }
roothub_portstatus(struct ohci * hc,int i)202 static inline u32 roothub_portstatus(struct ohci *hc, int i)
203 { return ohci_readl(&hc->regs->roothub.portstatus[i]); }
204
205 /* forward declaration */
206 static int hc_interrupt(ohci_t *ohci);
207 static void td_submit_job(ohci_t *ohci, struct usb_device *dev,
208 unsigned long pipe, void *buffer, int transfer_len,
209 struct devrequest *setup, urb_priv_t *urb,
210 int interval);
211 static int ep_link(ohci_t * ohci, ed_t * ed);
212 static int ep_unlink(ohci_t * ohci, ed_t * ed);
213 static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev,
214 unsigned long pipe, int interval, int load);
215
216 /*-------------------------------------------------------------------------*/
217
218 /* TDs ... */
td_alloc(ohci_dev_t * ohci_dev,struct usb_device * usb_dev)219 static struct td *td_alloc(ohci_dev_t *ohci_dev, struct usb_device *usb_dev)
220 {
221 int i;
222 struct td *td;
223
224 td = NULL;
225 for (i = 0; i < NUM_TD; i++)
226 {
227 if (ohci_dev->tds[i].usb_dev == NULL)
228 {
229 td = &ohci_dev->tds[i];
230 td->usb_dev = usb_dev;
231 break;
232 }
233 }
234
235 return td;
236 }
237
ed_free(struct ed * ed)238 static inline void ed_free(struct ed *ed)
239 {
240 ed->usb_dev = NULL;
241 }
242
243 /*-------------------------------------------------------------------------*
244 * URB support functions
245 *-------------------------------------------------------------------------*/
246
247 /* free HCD-private data associated with this URB */
248
urb_free_priv(urb_priv_t * urb)249 static void urb_free_priv(urb_priv_t *urb)
250 {
251 int i;
252 int last;
253 struct td *td;
254
255 last = urb->length - 1;
256 if (last >= 0) {
257 for (i = 0; i <= last; i++) {
258 td = urb->td[i];
259 if (td) {
260 td->usb_dev = NULL;
261 urb->td[i] = NULL;
262 }
263 }
264 }
265 free(urb);
266 }
267
268 /*-------------------------------------------------------------------------*/
269
270 #ifdef DEBUG
271 static int sohci_get_current_frame_number(ohci_t *ohci);
272
273 /* debug| print the main components of an URB
274 * small: 0) header + data packets 1) just header */
275
pkt_print(ohci_t * ohci,urb_priv_t * purb,struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * setup,char * str,int small)276 static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev,
277 unsigned long pipe, void *buffer, int transfer_len,
278 struct devrequest *setup, char *str, int small)
279 {
280 dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx",
281 str,
282 sohci_get_current_frame_number(ohci),
283 usb_pipedevice(pipe),
284 usb_pipeendpoint(pipe),
285 usb_pipeout(pipe)? 'O': 'I',
286 usb_pipetype(pipe) < 2 ? \
287 (usb_pipeint(pipe)? "INTR": "ISOC"): \
288 (usb_pipecontrol(pipe)? "CTRL": "BULK"),
289 (purb ? purb->actual_length : 0),
290 transfer_len, dev->status);
291 #ifdef OHCI_VERBOSE_DEBUG
292 if (!small) {
293 int i, len;
294
295 if (usb_pipecontrol(pipe)) {
296 printf(__FILE__ ": cmd(8):");
297 for (i = 0; i < 8 ; i++)
298 printf(" %02x", ((__u8 *) setup) [i]);
299 printf("\n");
300 }
301 if (transfer_len > 0 && buffer) {
302 printf(__FILE__ ": data(%d/%d):",
303 (purb ? purb->actual_length : 0),
304 transfer_len);
305 len = usb_pipeout(pipe)? transfer_len:
306 (purb ? purb->actual_length : 0);
307 for (i = 0; i < 16 && i < len; i++)
308 printf(" %02x", ((__u8 *) buffer) [i]);
309 printf("%s\n", i < len? "...": "");
310 }
311 }
312 #endif
313 }
314
315 /* just for debugging; prints non-empty branches of the int ed tree
316 * inclusive iso eds */
ep_print_int_eds(ohci_t * ohci,char * str)317 void ep_print_int_eds(ohci_t *ohci, char *str)
318 {
319 int i, j;
320 __u32 *ed_p;
321 for (i = 0; i < 32; i++) {
322 j = 5;
323 ed_p = &(ohci->hcca->int_table [i]);
324 if (*ed_p == 0)
325 continue;
326 invalidate_dcache_ed(ed_p);
327 printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
328 while (*ed_p != 0 && j--) {
329 ed_t *ed = (ed_t *)m32_swap(ed_p);
330 invalidate_dcache_ed(ed);
331 printf(" ed: %4x;", ed->hwINFO);
332 ed_p = &ed->hwNextED;
333 }
334 printf("\n");
335 }
336 }
337
ohci_dump_intr_mask(char * label,__u32 mask)338 static void ohci_dump_intr_mask(char *label, __u32 mask)
339 {
340 dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
341 label,
342 mask,
343 (mask & OHCI_INTR_MIE) ? " MIE" : "",
344 (mask & OHCI_INTR_OC) ? " OC" : "",
345 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
346 (mask & OHCI_INTR_FNO) ? " FNO" : "",
347 (mask & OHCI_INTR_UE) ? " UE" : "",
348 (mask & OHCI_INTR_RD) ? " RD" : "",
349 (mask & OHCI_INTR_SF) ? " SF" : "",
350 (mask & OHCI_INTR_WDH) ? " WDH" : "",
351 (mask & OHCI_INTR_SO) ? " SO" : ""
352 );
353 }
354
maybe_print_eds(char * label,__u32 value)355 static void maybe_print_eds(char *label, __u32 value)
356 {
357 ed_t *edp = (ed_t *)value;
358
359 if (value) {
360 dbg("%s %08x", label, value);
361 invalidate_dcache_ed(edp);
362 dbg("%08x", edp->hwINFO);
363 dbg("%08x", edp->hwTailP);
364 dbg("%08x", edp->hwHeadP);
365 dbg("%08x", edp->hwNextED);
366 }
367 }
368
hcfs2string(int state)369 static char *hcfs2string(int state)
370 {
371 switch (state) {
372 case OHCI_USB_RESET: return "reset";
373 case OHCI_USB_RESUME: return "resume";
374 case OHCI_USB_OPER: return "operational";
375 case OHCI_USB_SUSPEND: return "suspend";
376 }
377 return "?";
378 }
379
380 /* dump control and status registers */
ohci_dump_status(ohci_t * controller)381 static void ohci_dump_status(ohci_t *controller)
382 {
383 struct ohci_regs *regs = controller->regs;
384 __u32 temp;
385
386 temp = ohci_readl(®s->revision) & 0xff;
387 if (temp != 0x10)
388 dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
389
390 temp = ohci_readl(®s->control);
391 dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
392 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
393 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
394 (temp & OHCI_CTRL_IR) ? " IR" : "",
395 hcfs2string(temp & OHCI_CTRL_HCFS),
396 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
397 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
398 (temp & OHCI_CTRL_IE) ? " IE" : "",
399 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
400 temp & OHCI_CTRL_CBSR
401 );
402
403 temp = ohci_readl(®s->cmdstatus);
404 dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
405 (temp & OHCI_SOC) >> 16,
406 (temp & OHCI_OCR) ? " OCR" : "",
407 (temp & OHCI_BLF) ? " BLF" : "",
408 (temp & OHCI_CLF) ? " CLF" : "",
409 (temp & OHCI_HCR) ? " HCR" : ""
410 );
411
412 ohci_dump_intr_mask("intrstatus", ohci_readl(®s->intrstatus));
413 ohci_dump_intr_mask("intrenable", ohci_readl(®s->intrenable));
414
415 maybe_print_eds("ed_periodcurrent",
416 ohci_readl(®s->ed_periodcurrent));
417
418 maybe_print_eds("ed_controlhead", ohci_readl(®s->ed_controlhead));
419 maybe_print_eds("ed_controlcurrent",
420 ohci_readl(®s->ed_controlcurrent));
421
422 maybe_print_eds("ed_bulkhead", ohci_readl(®s->ed_bulkhead));
423 maybe_print_eds("ed_bulkcurrent", ohci_readl(®s->ed_bulkcurrent));
424
425 maybe_print_eds("donehead", ohci_readl(®s->donehead));
426 }
427
ohci_dump_roothub(ohci_t * controller,int verbose)428 static void ohci_dump_roothub(ohci_t *controller, int verbose)
429 {
430 __u32 temp, ndp, i;
431
432 temp = roothub_a(controller);
433 ndp = (temp & RH_A_NDP);
434 #ifdef CONFIG_AT91C_PQFP_UHPBUG
435 ndp = (ndp == 2) ? 1:0;
436 #endif
437 if (verbose) {
438 dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
439 ((temp & RH_A_POTPGT) >> 24) & 0xff,
440 (temp & RH_A_NOCP) ? " NOCP" : "",
441 (temp & RH_A_OCPM) ? " OCPM" : "",
442 (temp & RH_A_DT) ? " DT" : "",
443 (temp & RH_A_NPS) ? " NPS" : "",
444 (temp & RH_A_PSM) ? " PSM" : "",
445 ndp
446 );
447 temp = roothub_b(controller);
448 dbg("roothub.b: %08x PPCM=%04x DR=%04x",
449 temp,
450 (temp & RH_B_PPCM) >> 16,
451 (temp & RH_B_DR)
452 );
453 temp = roothub_status(controller);
454 dbg("roothub.status: %08x%s%s%s%s%s%s",
455 temp,
456 (temp & RH_HS_CRWE) ? " CRWE" : "",
457 (temp & RH_HS_OCIC) ? " OCIC" : "",
458 (temp & RH_HS_LPSC) ? " LPSC" : "",
459 (temp & RH_HS_DRWE) ? " DRWE" : "",
460 (temp & RH_HS_OCI) ? " OCI" : "",
461 (temp & RH_HS_LPS) ? " LPS" : ""
462 );
463 }
464
465 for (i = 0; i < ndp; i++) {
466 temp = roothub_portstatus(controller, i);
467 dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
468 i,
469 temp,
470 (temp & RH_PS_PRSC) ? " PRSC" : "",
471 (temp & RH_PS_OCIC) ? " OCIC" : "",
472 (temp & RH_PS_PSSC) ? " PSSC" : "",
473 (temp & RH_PS_PESC) ? " PESC" : "",
474 (temp & RH_PS_CSC) ? " CSC" : "",
475
476 (temp & RH_PS_LSDA) ? " LSDA" : "",
477 (temp & RH_PS_PPS) ? " PPS" : "",
478 (temp & RH_PS_PRS) ? " PRS" : "",
479 (temp & RH_PS_POCI) ? " POCI" : "",
480 (temp & RH_PS_PSS) ? " PSS" : "",
481
482 (temp & RH_PS_PES) ? " PES" : "",
483 (temp & RH_PS_CCS) ? " CCS" : ""
484 );
485 }
486 }
487
ohci_dump(ohci_t * controller,int verbose)488 static void ohci_dump(ohci_t *controller, int verbose)
489 {
490 dbg("OHCI controller usb-%s state", controller->slot_name);
491
492 /* dumps some of the state we know about */
493 ohci_dump_status(controller);
494 if (verbose)
495 ep_print_int_eds(controller, "hcca");
496 invalidate_dcache_hcca(controller->hcca);
497 dbg("hcca frame #%04x", controller->hcca->frame_no);
498 ohci_dump_roothub(controller, 1);
499 }
500 #endif /* DEBUG */
501
502 /*-------------------------------------------------------------------------*
503 * Interface functions (URB)
504 *-------------------------------------------------------------------------*/
505
506 /* get a transfer request */
507
sohci_submit_job(ohci_t * ohci,ohci_dev_t * ohci_dev,urb_priv_t * urb,struct devrequest * setup)508 int sohci_submit_job(ohci_t *ohci, ohci_dev_t *ohci_dev, urb_priv_t *urb,
509 struct devrequest *setup)
510 {
511 ed_t *ed;
512 urb_priv_t *purb_priv = urb;
513 int i, size = 0;
514 struct usb_device *dev = urb->dev;
515 unsigned long pipe = urb->pipe;
516 void *buffer = urb->transfer_buffer;
517 int transfer_len = urb->transfer_buffer_length;
518 int interval = urb->interval;
519
520 /* when controller's hung, permit only roothub cleanup attempts
521 * such as powering down ports */
522 if (ohci->disabled) {
523 err("sohci_submit_job: EPIPE");
524 return -1;
525 }
526
527 /* we're about to begin a new transaction here so mark the
528 * URB unfinished */
529 urb->finished = 0;
530
531 /* every endpoint has a ed, locate and fill it */
532 ed = ep_add_ed(ohci_dev, dev, pipe, interval, 1);
533 if (!ed) {
534 err("sohci_submit_job: ENOMEM");
535 return -1;
536 }
537
538 /* for the private part of the URB we need the number of TDs (size) */
539 switch (usb_pipetype(pipe)) {
540 case PIPE_BULK: /* one TD for every 4096 Byte */
541 size = (transfer_len - 1) / 4096 + 1;
542 break;
543 case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
544 size = (transfer_len == 0)? 2:
545 (transfer_len - 1) / 4096 + 3;
546 break;
547 case PIPE_INTERRUPT: /* 1 TD */
548 size = 1;
549 break;
550 }
551
552 ed->purb = urb;
553
554 if (size >= (N_URB_TD - 1)) {
555 err("need %d TDs, only have %d", size, N_URB_TD);
556 return -1;
557 }
558 purb_priv->pipe = pipe;
559
560 /* fill the private part of the URB */
561 purb_priv->length = size;
562 purb_priv->ed = ed;
563 purb_priv->actual_length = 0;
564
565 /* allocate the TDs */
566 /* note that td[0] was allocated in ep_add_ed */
567 for (i = 0; i < size; i++) {
568 purb_priv->td[i] = td_alloc(ohci_dev, dev);
569 if (!purb_priv->td[i]) {
570 purb_priv->length = i;
571 urb_free_priv(purb_priv);
572 err("sohci_submit_job: ENOMEM");
573 return -1;
574 }
575 }
576
577 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
578 urb_free_priv(purb_priv);
579 err("sohci_submit_job: EINVAL");
580 return -1;
581 }
582
583 /* link the ed into a chain if is not already */
584 if (ed->state != ED_OPER)
585 ep_link(ohci, ed);
586
587 /* fill the TDs and link it to the ed */
588 td_submit_job(ohci, dev, pipe, buffer, transfer_len,
589 setup, purb_priv, interval);
590
591 return 0;
592 }
593
594 /*-------------------------------------------------------------------------*/
595
596 #ifdef DEBUG
597 /* tell us the current USB frame number */
sohci_get_current_frame_number(ohci_t * ohci)598 static int sohci_get_current_frame_number(ohci_t *ohci)
599 {
600 invalidate_dcache_hcca(ohci->hcca);
601 return m16_swap(ohci->hcca->frame_no);
602 }
603 #endif
604
605 /*-------------------------------------------------------------------------*
606 * ED handling functions
607 *-------------------------------------------------------------------------*/
608
609 /* search for the right branch to insert an interrupt ed into the int tree
610 * do some load ballancing;
611 * returns the branch and
612 * sets the interval to interval = 2^integer (ld (interval)) */
613
ep_int_ballance(ohci_t * ohci,int interval,int load)614 static int ep_int_ballance(ohci_t *ohci, int interval, int load)
615 {
616 int i, branch = 0;
617
618 /* search for the least loaded interrupt endpoint
619 * branch of all 32 branches
620 */
621 for (i = 0; i < 32; i++)
622 if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])
623 branch = i;
624
625 branch = branch % interval;
626 for (i = branch; i < 32; i += interval)
627 ohci->ohci_int_load [i] += load;
628
629 return branch;
630 }
631
632 /*-------------------------------------------------------------------------*/
633
634 /* 2^int( ld (inter)) */
635
ep_2_n_interval(int inter)636 static int ep_2_n_interval(int inter)
637 {
638 int i;
639 for (i = 0; ((inter >> i) > 1) && (i < 5); i++);
640 return 1 << i;
641 }
642
643 /*-------------------------------------------------------------------------*/
644
645 /* the int tree is a binary tree
646 * in order to process it sequentially the indexes of the branches have to
647 * be mapped the mapping reverses the bits of a word of num_bits length */
ep_rev(int num_bits,int word)648 static int ep_rev(int num_bits, int word)
649 {
650 int i, wout = 0;
651
652 for (i = 0; i < num_bits; i++)
653 wout |= (((word >> i) & 1) << (num_bits - i - 1));
654 return wout;
655 }
656
657 /*-------------------------------------------------------------------------*
658 * ED handling functions
659 *-------------------------------------------------------------------------*/
660
661 /* link an ed into one of the HC chains */
662
ep_link(ohci_t * ohci,ed_t * edi)663 static int ep_link(ohci_t *ohci, ed_t *edi)
664 {
665 volatile ed_t *ed = edi;
666 int int_branch;
667 int i;
668 int inter;
669 int interval;
670 int load;
671 __u32 *ed_p;
672
673 ed->state = ED_OPER;
674 ed->int_interval = 0;
675
676 switch (ed->type) {
677 case PIPE_CONTROL:
678 ed->hwNextED = 0;
679 flush_dcache_ed(ed);
680 if (ohci->ed_controltail == NULL)
681 ohci_writel((uintptr_t)ed, &ohci->regs->ed_controlhead);
682 else
683 ohci->ed_controltail->hwNextED =
684 m32_swap((unsigned long)ed);
685
686 ed->ed_prev = ohci->ed_controltail;
687 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
688 !ohci->ed_rm_list[1] && !ohci->sleeping) {
689 ohci->hc_control |= OHCI_CTRL_CLE;
690 ohci_writel(ohci->hc_control, &ohci->regs->control);
691 }
692 ohci->ed_controltail = edi;
693 break;
694
695 case PIPE_BULK:
696 ed->hwNextED = 0;
697 flush_dcache_ed(ed);
698 if (ohci->ed_bulktail == NULL)
699 ohci_writel((uintptr_t)ed, &ohci->regs->ed_bulkhead);
700 else
701 ohci->ed_bulktail->hwNextED =
702 m32_swap((unsigned long)ed);
703
704 ed->ed_prev = ohci->ed_bulktail;
705 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
706 !ohci->ed_rm_list[1] && !ohci->sleeping) {
707 ohci->hc_control |= OHCI_CTRL_BLE;
708 ohci_writel(ohci->hc_control, &ohci->regs->control);
709 }
710 ohci->ed_bulktail = edi;
711 break;
712
713 case PIPE_INTERRUPT:
714 load = ed->int_load;
715 interval = ep_2_n_interval(ed->int_period);
716 ed->int_interval = interval;
717 int_branch = ep_int_ballance(ohci, interval, load);
718 ed->int_branch = int_branch;
719
720 for (i = 0; i < ep_rev(6, interval); i += inter) {
721 inter = 1;
722 for (ed_p = &(ohci->hcca->int_table[\
723 ep_rev(5, i) + int_branch]);
724 (*ed_p != 0) &&
725 (((ed_t *)ed_p)->int_interval >= interval);
726 ed_p = &(((ed_t *)ed_p)->hwNextED))
727 inter = ep_rev(6,
728 ((ed_t *)ed_p)->int_interval);
729 ed->hwNextED = *ed_p;
730 flush_dcache_ed(ed);
731 *ed_p = m32_swap((unsigned long)ed);
732 flush_dcache_hcca(ohci->hcca);
733 }
734 break;
735 }
736 return 0;
737 }
738
739 /*-------------------------------------------------------------------------*/
740
741 /* scan the periodic table to find and unlink this ED */
periodic_unlink(struct ohci * ohci,volatile struct ed * ed,unsigned index,unsigned period)742 static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed,
743 unsigned index, unsigned period)
744 {
745 __maybe_unused unsigned long aligned_ed_p;
746
747 for (; index < NUM_INTS; index += period) {
748 __u32 *ed_p = &ohci->hcca->int_table [index];
749
750 /* ED might have been unlinked through another path */
751 while (*ed_p != 0) {
752 if (((struct ed *)(uintptr_t)
753 m32_swap((unsigned long)ed_p)) == ed) {
754 *ed_p = ed->hwNextED;
755 aligned_ed_p = (unsigned long)ed_p;
756 aligned_ed_p &= ~(ARCH_DMA_MINALIGN - 1);
757 flush_dcache_range(aligned_ed_p,
758 aligned_ed_p + ARCH_DMA_MINALIGN);
759 break;
760 }
761 ed_p = &(((struct ed *)(uintptr_t)
762 m32_swap((unsigned long)ed_p))->hwNextED);
763 }
764 }
765 }
766
767 /* unlink an ed from one of the HC chains.
768 * just the link to the ed is unlinked.
769 * the link from the ed still points to another operational ed or 0
770 * so the HC can eventually finish the processing of the unlinked ed */
771
ep_unlink(ohci_t * ohci,ed_t * edi)772 static int ep_unlink(ohci_t *ohci, ed_t *edi)
773 {
774 volatile ed_t *ed = edi;
775 int i;
776
777 ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
778 flush_dcache_ed(ed);
779
780 switch (ed->type) {
781 case PIPE_CONTROL:
782 if (ed->ed_prev == NULL) {
783 if (!ed->hwNextED) {
784 ohci->hc_control &= ~OHCI_CTRL_CLE;
785 ohci_writel(ohci->hc_control,
786 &ohci->regs->control);
787 }
788 ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
789 &ohci->regs->ed_controlhead);
790 } else {
791 ed->ed_prev->hwNextED = ed->hwNextED;
792 flush_dcache_ed(ed->ed_prev);
793 }
794 if (ohci->ed_controltail == ed) {
795 ohci->ed_controltail = ed->ed_prev;
796 } else {
797 ((ed_t *)(uintptr_t)m32_swap(
798 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
799 }
800 break;
801
802 case PIPE_BULK:
803 if (ed->ed_prev == NULL) {
804 if (!ed->hwNextED) {
805 ohci->hc_control &= ~OHCI_CTRL_BLE;
806 ohci_writel(ohci->hc_control,
807 &ohci->regs->control);
808 }
809 ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
810 &ohci->regs->ed_bulkhead);
811 } else {
812 ed->ed_prev->hwNextED = ed->hwNextED;
813 flush_dcache_ed(ed->ed_prev);
814 }
815 if (ohci->ed_bulktail == ed) {
816 ohci->ed_bulktail = ed->ed_prev;
817 } else {
818 ((ed_t *)(uintptr_t)m32_swap(
819 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
820 }
821 break;
822
823 case PIPE_INTERRUPT:
824 periodic_unlink(ohci, ed, 0, 1);
825 for (i = ed->int_branch; i < 32; i += ed->int_interval)
826 ohci->ohci_int_load[i] -= ed->int_load;
827 break;
828 }
829 ed->state = ED_UNLINK;
830 return 0;
831 }
832
833 /*-------------------------------------------------------------------------*/
834
835 /* add/reinit an endpoint; this should be done once at the
836 * usb_set_configuration command, but the USB stack is a little bit
837 * stateless so we do it at every transaction if the state of the ed
838 * is ED_NEW then a dummy td is added and the state is changed to
839 * ED_UNLINK in all other cases the state is left unchanged the ed
840 * info fields are setted anyway even though most of them should not
841 * change
842 */
ep_add_ed(ohci_dev_t * ohci_dev,struct usb_device * usb_dev,unsigned long pipe,int interval,int load)843 static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev,
844 unsigned long pipe, int interval, int load)
845 {
846 td_t *td;
847 ed_t *ed_ret;
848 volatile ed_t *ed;
849
850 ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) |
851 (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))];
852
853 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
854 err("ep_add_ed: pending delete");
855 /* pending delete request */
856 return NULL;
857 }
858
859 if (ed->state == ED_NEW) {
860 /* dummy td; end of td list for ed */
861 td = td_alloc(ohci_dev, usb_dev);
862 ed->hwTailP = m32_swap((unsigned long)td);
863 ed->hwHeadP = ed->hwTailP;
864 ed->state = ED_UNLINK;
865 ed->type = usb_pipetype(pipe);
866 ohci_dev->ed_cnt++;
867 }
868
869 ed->hwINFO = m32_swap(usb_pipedevice(pipe)
870 | usb_pipeendpoint(pipe) << 7
871 | (usb_pipeisoc(pipe)? 0x8000: 0)
872 | (usb_pipecontrol(pipe)? 0: \
873 (usb_pipeout(pipe)? 0x800: 0x1000))
874 | (usb_dev->speed == USB_SPEED_LOW) << 13
875 | usb_maxpacket(usb_dev, pipe) << 16);
876
877 if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {
878 ed->int_period = interval;
879 ed->int_load = load;
880 }
881
882 flush_dcache_ed(ed);
883
884 return ed_ret;
885 }
886
887 /*-------------------------------------------------------------------------*
888 * TD handling functions
889 *-------------------------------------------------------------------------*/
890
891 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
892
td_fill(ohci_t * ohci,unsigned int info,void * data,int len,struct usb_device * dev,int index,urb_priv_t * urb_priv)893 static void td_fill(ohci_t *ohci, unsigned int info,
894 void *data, int len,
895 struct usb_device *dev, int index, urb_priv_t *urb_priv)
896 {
897 volatile td_t *td, *td_pt;
898 #ifdef OHCI_FILL_TRACE
899 int i;
900 #endif
901
902 if (index > urb_priv->length) {
903 err("index > length");
904 return;
905 }
906 /* use this td as the next dummy */
907 td_pt = urb_priv->td [index];
908 td_pt->hwNextTD = 0;
909 flush_dcache_td(td_pt);
910
911 /* fill the old dummy TD */
912 td = urb_priv->td [index] =
913 (td_t *)(uintptr_t)
914 (m32_swap(urb_priv->ed->hwTailP) & ~0xf);
915
916 td->ed = urb_priv->ed;
917 td->next_dl_td = NULL;
918 td->index = index;
919 td->data = (uintptr_t)data;
920 #ifdef OHCI_FILL_TRACE
921 if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
922 for (i = 0; i < len; i++)
923 printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]);
924 printf("\n");
925 }
926 #endif
927 if (!len)
928 data = 0;
929
930 td->hwINFO = m32_swap(info);
931 td->hwCBP = m32_swap((unsigned long)data);
932 if (data)
933 td->hwBE = m32_swap((unsigned long)(data + len - 1));
934 else
935 td->hwBE = 0;
936
937 td->hwNextTD = m32_swap((unsigned long)td_pt);
938 flush_dcache_td(td);
939
940 /* append to queue */
941 td->ed->hwTailP = td->hwNextTD;
942 flush_dcache_ed(td->ed);
943 }
944
945 /*-------------------------------------------------------------------------*/
946
947 /* prepare all TDs of a transfer */
948
td_submit_job(ohci_t * ohci,struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * setup,urb_priv_t * urb,int interval)949 static void td_submit_job(ohci_t *ohci, struct usb_device *dev,
950 unsigned long pipe, void *buffer, int transfer_len,
951 struct devrequest *setup, urb_priv_t *urb,
952 int interval)
953 {
954 int data_len = transfer_len;
955 void *data;
956 int cnt = 0;
957 __u32 info = 0;
958 unsigned int toggle = 0;
959
960 flush_dcache_buffer(buffer, data_len);
961
962 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle
963 * bits for resetting */
964 if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
965 toggle = TD_T_TOGGLE;
966 } else {
967 toggle = TD_T_DATA0;
968 usb_settoggle(dev, usb_pipeendpoint(pipe),
969 usb_pipeout(pipe), 1);
970 }
971 urb->td_cnt = 0;
972 if (data_len)
973 data = buffer;
974 else
975 data = 0;
976
977 switch (usb_pipetype(pipe)) {
978 case PIPE_BULK:
979 info = usb_pipeout(pipe)?
980 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
981 while (data_len > 4096) {
982 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle),
983 data, 4096, dev, cnt, urb);
984 data += 4096; data_len -= 4096; cnt++;
985 }
986 info = usb_pipeout(pipe)?
987 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
988 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data,
989 data_len, dev, cnt, urb);
990 cnt++;
991
992 if (!ohci->sleeping) {
993 /* start bulk list */
994 ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus);
995 }
996 break;
997
998 case PIPE_CONTROL:
999 /* Setup phase */
1000 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
1001 flush_dcache_buffer(setup, 8);
1002 td_fill(ohci, info, setup, 8, dev, cnt++, urb);
1003
1004 /* Optional Data phase */
1005 if (data_len > 0) {
1006 info = usb_pipeout(pipe)?
1007 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
1008 TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
1009 /* NOTE: mishandles transfers >8K, some >4K */
1010 td_fill(ohci, info, data, data_len, dev, cnt++, urb);
1011 }
1012
1013 /* Status phase */
1014 info = (usb_pipeout(pipe) || data_len == 0) ?
1015 TD_CC | TD_DP_IN | TD_T_DATA1:
1016 TD_CC | TD_DP_OUT | TD_T_DATA1;
1017 td_fill(ohci, info, data, 0, dev, cnt++, urb);
1018
1019 if (!ohci->sleeping) {
1020 /* start Control list */
1021 ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus);
1022 }
1023 break;
1024
1025 case PIPE_INTERRUPT:
1026 info = usb_pipeout(urb->pipe)?
1027 TD_CC | TD_DP_OUT | toggle:
1028 TD_CC | TD_R | TD_DP_IN | toggle;
1029 td_fill(ohci, info, data, data_len, dev, cnt++, urb);
1030 break;
1031 }
1032 if (urb->length != cnt)
1033 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
1034 }
1035
1036 /*-------------------------------------------------------------------------*
1037 * Done List handling functions
1038 *-------------------------------------------------------------------------*/
1039
1040 /* calculate the transfer length and update the urb */
1041
dl_transfer_length(td_t * td)1042 static void dl_transfer_length(td_t *td)
1043 {
1044 __u32 tdBE, tdCBP;
1045 urb_priv_t *lurb_priv = td->ed->purb;
1046
1047 tdBE = m32_swap(td->hwBE);
1048 tdCBP = m32_swap(td->hwCBP);
1049
1050 if (!(usb_pipecontrol(lurb_priv->pipe) &&
1051 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
1052 if (tdBE != 0) {
1053 if (td->hwCBP == 0)
1054 lurb_priv->actual_length += tdBE - td->data + 1;
1055 else
1056 lurb_priv->actual_length += tdCBP - td->data;
1057 }
1058 }
1059 }
1060
1061 /*-------------------------------------------------------------------------*/
check_status(td_t * td_list)1062 static void check_status(td_t *td_list)
1063 {
1064 urb_priv_t *lurb_priv = td_list->ed->purb;
1065 int urb_len = lurb_priv->length;
1066 __u32 *phwHeadP = &td_list->ed->hwHeadP;
1067 int cc;
1068
1069 cc = TD_CC_GET(m32_swap(td_list->hwINFO));
1070 if (cc) {
1071 err(" USB-error: %s (%x)", cc_to_string[cc], cc);
1072
1073 invalidate_dcache_ed(td_list->ed);
1074 if (*phwHeadP & m32_swap(0x1)) {
1075 if (lurb_priv &&
1076 ((td_list->index + 1) < urb_len)) {
1077 *phwHeadP =
1078 (lurb_priv->td[urb_len - 1]->hwNextTD &\
1079 m32_swap(0xfffffff0)) |
1080 (*phwHeadP & m32_swap(0x2));
1081
1082 lurb_priv->td_cnt += urb_len -
1083 td_list->index - 1;
1084 } else
1085 *phwHeadP &= m32_swap(0xfffffff2);
1086 flush_dcache_ed(td_list->ed);
1087 }
1088 }
1089 }
1090
1091 /* replies to the request have to be on a FIFO basis so
1092 * we reverse the reversed done-list */
dl_reverse_done_list(ohci_t * ohci)1093 static td_t *dl_reverse_done_list(ohci_t *ohci)
1094 {
1095 uintptr_t td_list_hc;
1096 td_t *td_rev = NULL;
1097 td_t *td_list = NULL;
1098
1099 invalidate_dcache_hcca(ohci->hcca);
1100 td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
1101 ohci->hcca->done_head = 0;
1102 flush_dcache_hcca(ohci->hcca);
1103
1104 while (td_list_hc) {
1105 td_list = (td_t *)td_list_hc;
1106 invalidate_dcache_td(td_list);
1107 check_status(td_list);
1108 td_list->next_dl_td = td_rev;
1109 td_rev = td_list;
1110 td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
1111 }
1112 return td_list;
1113 }
1114
1115 /*-------------------------------------------------------------------------*/
1116 /*-------------------------------------------------------------------------*/
1117
finish_urb(ohci_t * ohci,urb_priv_t * urb,int status)1118 static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status)
1119 {
1120 if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL))
1121 urb->finished = 1;
1122 else
1123 dbg("finish_urb: strange.., ED state %x, \n", status);
1124 }
1125
1126 /*
1127 * Used to take back a TD from the host controller. This would normally be
1128 * called from within dl_done_list, however it may be called directly if the
1129 * HC no longer sees the TD and it has not appeared on the donelist (after
1130 * two frames). This bug has been observed on ZF Micro systems.
1131 */
takeback_td(ohci_t * ohci,td_t * td_list)1132 static int takeback_td(ohci_t *ohci, td_t *td_list)
1133 {
1134 ed_t *ed;
1135 int cc;
1136 int stat = 0;
1137 /* urb_t *urb; */
1138 urb_priv_t *lurb_priv;
1139 __u32 tdINFO, edHeadP, edTailP;
1140
1141 invalidate_dcache_td(td_list);
1142 tdINFO = m32_swap(td_list->hwINFO);
1143
1144 ed = td_list->ed;
1145 lurb_priv = ed->purb;
1146
1147 dl_transfer_length(td_list);
1148
1149 lurb_priv->td_cnt++;
1150
1151 /* error code of transfer */
1152 cc = TD_CC_GET(tdINFO);
1153 if (cc) {
1154 err("USB-error: %s (%x)", cc_to_string[cc], cc);
1155 stat = cc_to_error[cc];
1156 }
1157
1158 /* see if this done list makes for all TD's of current URB,
1159 * and mark the URB finished if so */
1160 if (lurb_priv->td_cnt == lurb_priv->length)
1161 finish_urb(ohci, lurb_priv, ed->state);
1162
1163 dbg("dl_done_list: processing TD %x, len %x\n",
1164 lurb_priv->td_cnt, lurb_priv->length);
1165
1166 if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) {
1167 invalidate_dcache_ed(ed);
1168 edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
1169 edTailP = m32_swap(ed->hwTailP);
1170
1171 /* unlink eds if they are not busy */
1172 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
1173 ep_unlink(ohci, ed);
1174 }
1175 return stat;
1176 }
1177
dl_done_list(ohci_t * ohci)1178 static int dl_done_list(ohci_t *ohci)
1179 {
1180 int stat = 0;
1181 td_t *td_list = dl_reverse_done_list(ohci);
1182
1183 while (td_list) {
1184 td_t *td_next = td_list->next_dl_td;
1185 stat = takeback_td(ohci, td_list);
1186 td_list = td_next;
1187 }
1188 return stat;
1189 }
1190
1191 /*-------------------------------------------------------------------------*
1192 * Virtual Root Hub
1193 *-------------------------------------------------------------------------*/
1194
1195 #include <usbroothubdes.h>
1196
1197 /* Hub class-specific descriptor is constructed dynamically */
1198
1199 /*-------------------------------------------------------------------------*/
1200
1201 #define OK(x) len = (x); break
1202 #ifdef DEBUG
1203 #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \
1204 &ohci->regs->roothub.status); }
1205 #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \
1206 (x)); ohci_writel((x), &ohci->regs->roothub.portstatus[wIndex-1]); }
1207 #else
1208 #define WR_RH_STAT(x) ohci_writel((x), &ohci->regs->roothub.status)
1209 #define WR_RH_PORTSTAT(x) ohci_writel((x), \
1210 &ohci->regs->roothub.portstatus[wIndex-1])
1211 #endif
1212 #define RD_RH_STAT roothub_status(ohci)
1213 #define RD_RH_PORTSTAT roothub_portstatus(ohci, wIndex-1)
1214
1215 /* request to virtual root hub */
1216
rh_check_port_status(ohci_t * controller)1217 int rh_check_port_status(ohci_t *controller)
1218 {
1219 __u32 temp, ndp, i;
1220 int res;
1221
1222 res = -1;
1223 temp = roothub_a(controller);
1224 ndp = (temp & RH_A_NDP);
1225 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1226 ndp = (ndp == 2) ? 1:0;
1227 #endif
1228 for (i = 0; i < ndp; i++) {
1229 temp = roothub_portstatus(controller, i);
1230 /* check for a device disconnect */
1231 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
1232 (RH_PS_PESC | RH_PS_CSC)) &&
1233 ((temp & RH_PS_CCS) == 0)) {
1234 res = i;
1235 break;
1236 }
1237 }
1238 return res;
1239 }
1240
ohci_submit_rh_msg(ohci_t * ohci,struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * cmd)1241 static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev,
1242 unsigned long pipe, void *buffer, int transfer_len,
1243 struct devrequest *cmd)
1244 {
1245 void *data = buffer;
1246 int leni = transfer_len;
1247 int len = 0;
1248 int stat = 0;
1249 __u16 bmRType_bReq;
1250 __u16 wValue;
1251 __u16 wIndex;
1252 __u16 wLength;
1253 ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32));
1254
1255 #ifdef DEBUG
1256 pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len,
1257 cmd, "SUB(rh)", usb_pipein(pipe));
1258 #else
1259 ohci_mdelay(1);
1260 #endif
1261 if (usb_pipeint(pipe)) {
1262 info("Root-Hub submit IRQ: NOT implemented");
1263 return 0;
1264 }
1265
1266 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
1267 wValue = le16_to_cpu(cmd->value);
1268 wIndex = le16_to_cpu(cmd->index);
1269 wLength = le16_to_cpu(cmd->length);
1270
1271 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1272 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1273
1274 switch (bmRType_bReq) {
1275 /* Request Destination:
1276 without flags: Device,
1277 RH_INTERFACE: interface,
1278 RH_ENDPOINT: endpoint,
1279 RH_CLASS means HUB here,
1280 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
1281 */
1282
1283 case RH_GET_STATUS:
1284 *(u16 *)databuf = cpu_to_le16(1);
1285 OK(2);
1286 case RH_GET_STATUS | RH_INTERFACE:
1287 *(u16 *)databuf = cpu_to_le16(0);
1288 OK(2);
1289 case RH_GET_STATUS | RH_ENDPOINT:
1290 *(u16 *)databuf = cpu_to_le16(0);
1291 OK(2);
1292 case RH_GET_STATUS | RH_CLASS:
1293 *(u32 *)databuf = cpu_to_le32(
1294 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
1295 OK(4);
1296 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
1297 *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT);
1298 OK(4);
1299
1300 case RH_CLEAR_FEATURE | RH_ENDPOINT:
1301 switch (wValue) {
1302 case (RH_ENDPOINT_STALL):
1303 OK(0);
1304 }
1305 break;
1306
1307 case RH_CLEAR_FEATURE | RH_CLASS:
1308 switch (wValue) {
1309 case RH_C_HUB_LOCAL_POWER:
1310 OK(0);
1311 case (RH_C_HUB_OVER_CURRENT):
1312 WR_RH_STAT(RH_HS_OCIC);
1313 OK(0);
1314 }
1315 break;
1316
1317 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1318 switch (wValue) {
1319 case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0);
1320 case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0);
1321 case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0);
1322 case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0);
1323 case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0);
1324 case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0);
1325 case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0);
1326 case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0);
1327 }
1328 break;
1329
1330 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1331 switch (wValue) {
1332 case (RH_PORT_SUSPEND):
1333 WR_RH_PORTSTAT(RH_PS_PSS); OK(0);
1334 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1335 if (RD_RH_PORTSTAT & RH_PS_CCS)
1336 WR_RH_PORTSTAT(RH_PS_PRS);
1337 OK(0);
1338 case (RH_PORT_POWER):
1339 WR_RH_PORTSTAT(RH_PS_PPS);
1340 OK(0);
1341 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1342 if (RD_RH_PORTSTAT & RH_PS_CCS)
1343 WR_RH_PORTSTAT(RH_PS_PES);
1344 OK(0);
1345 }
1346 break;
1347
1348 case RH_SET_ADDRESS:
1349 ohci->rh.devnum = wValue;
1350 OK(0);
1351
1352 case RH_GET_DESCRIPTOR:
1353 switch ((wValue & 0xff00) >> 8) {
1354 case (0x01): /* device descriptor */
1355 len = min_t(unsigned int,
1356 leni,
1357 min_t(unsigned int,
1358 sizeof(root_hub_dev_des),
1359 wLength));
1360 databuf = root_hub_dev_des; OK(len);
1361 case (0x02): /* configuration descriptor */
1362 len = min_t(unsigned int,
1363 leni,
1364 min_t(unsigned int,
1365 sizeof(root_hub_config_des),
1366 wLength));
1367 databuf = root_hub_config_des; OK(len);
1368 case (0x03): /* string descriptors */
1369 if (wValue == 0x0300) {
1370 len = min_t(unsigned int,
1371 leni,
1372 min_t(unsigned int,
1373 sizeof(root_hub_str_index0),
1374 wLength));
1375 databuf = root_hub_str_index0;
1376 OK(len);
1377 }
1378 if (wValue == 0x0301) {
1379 len = min_t(unsigned int,
1380 leni,
1381 min_t(unsigned int,
1382 sizeof(root_hub_str_index1),
1383 wLength));
1384 databuf = root_hub_str_index1;
1385 OK(len);
1386 }
1387 default:
1388 stat = USB_ST_STALLED;
1389 }
1390 break;
1391
1392 case RH_GET_DESCRIPTOR | RH_CLASS:
1393 {
1394 __u32 temp = roothub_a(ohci);
1395
1396 databuf[0] = 9; /* min length; */
1397 databuf[1] = 0x29;
1398 databuf[2] = temp & RH_A_NDP;
1399 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1400 databuf[2] = (databuf[2] == 2) ? 1 : 0;
1401 #endif
1402 databuf[3] = 0;
1403 if (temp & RH_A_PSM) /* per-port power switching? */
1404 databuf[3] |= 0x1;
1405 if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1406 databuf[3] |= 0x10;
1407 else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */
1408 databuf[3] |= 0x8;
1409
1410 databuf[4] = 0;
1411 databuf[5] = (temp & RH_A_POTPGT) >> 24;
1412 databuf[6] = 0;
1413 temp = roothub_b(ohci);
1414 databuf[7] = temp & RH_B_DR;
1415 if (databuf[2] < 7) {
1416 databuf[8] = 0xff;
1417 } else {
1418 databuf[0] += 2;
1419 databuf[8] = (temp & RH_B_DR) >> 8;
1420 databuf[10] = databuf[9] = 0xff;
1421 }
1422
1423 len = min_t(unsigned int, leni,
1424 min_t(unsigned int, databuf[0], wLength));
1425 OK(len);
1426 }
1427
1428 case RH_GET_CONFIGURATION:
1429 databuf[0] = 0x01;
1430 OK(1);
1431
1432 case RH_SET_CONFIGURATION:
1433 WR_RH_STAT(0x10000);
1434 OK(0);
1435
1436 default:
1437 dbg("unsupported root hub command");
1438 stat = USB_ST_STALLED;
1439 }
1440
1441 #ifdef DEBUG
1442 ohci_dump_roothub(ohci, 1);
1443 #else
1444 ohci_mdelay(1);
1445 #endif
1446
1447 len = min_t(int, len, leni);
1448 if (data != databuf)
1449 memcpy(data, databuf, len);
1450 dev->act_len = len;
1451 dev->status = stat;
1452
1453 #ifdef DEBUG
1454 pkt_print(ohci, NULL, dev, pipe, buffer,
1455 transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
1456 #else
1457 ohci_mdelay(1);
1458 #endif
1459
1460 return stat;
1461 }
1462
1463 /*-------------------------------------------------------------------------*/
1464
ohci_get_ohci_dev(ohci_t * ohci,int devnum,int intr)1465 static ohci_dev_t *ohci_get_ohci_dev(ohci_t *ohci, int devnum, int intr)
1466 {
1467 int i;
1468
1469 if (!intr)
1470 return &ohci->ohci_dev;
1471
1472 /* First see if we already have an ohci_dev for this dev. */
1473 for (i = 0; i < NUM_INT_DEVS; i++) {
1474 if (ohci->int_dev[i].devnum == devnum)
1475 return &ohci->int_dev[i];
1476 }
1477
1478 /* If not then find a free one. */
1479 for (i = 0; i < NUM_INT_DEVS; i++) {
1480 if (ohci->int_dev[i].devnum == -1) {
1481 ohci->int_dev[i].devnum = devnum;
1482 return &ohci->int_dev[i];
1483 }
1484 }
1485
1486 printf("ohci: Error out of ohci_devs for interrupt endpoints\n");
1487 return NULL;
1488 }
1489
1490 /* common code for handling submit messages - used for all but root hub */
1491 /* accesses. */
ohci_alloc_urb(struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,int interval)1492 static urb_priv_t *ohci_alloc_urb(struct usb_device *dev, unsigned long pipe,
1493 void *buffer, int transfer_len, int interval)
1494 {
1495 urb_priv_t *urb;
1496
1497 urb = calloc(1, sizeof(urb_priv_t));
1498 if (!urb) {
1499 printf("ohci: Error out of memory allocating urb\n");
1500 return NULL;
1501 }
1502
1503 urb->dev = dev;
1504 urb->pipe = pipe;
1505 urb->transfer_buffer = buffer;
1506 urb->transfer_buffer_length = transfer_len;
1507 urb->interval = interval;
1508
1509 return urb;
1510 }
1511
submit_common_msg(ohci_t * ohci,struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * setup,int interval)1512 static int submit_common_msg(ohci_t *ohci, struct usb_device *dev,
1513 unsigned long pipe, void *buffer, int transfer_len,
1514 struct devrequest *setup, int interval)
1515 {
1516 int stat = 0;
1517 int maxsize = usb_maxpacket(dev, pipe);
1518 int timeout;
1519 urb_priv_t *urb;
1520 ohci_dev_t *ohci_dev;
1521
1522 urb = ohci_alloc_urb(dev, pipe, buffer, transfer_len, interval);
1523 if (!urb)
1524 return -ENOMEM;
1525
1526 #ifdef DEBUG
1527 urb->actual_length = 0;
1528 pkt_print(ohci, urb, dev, pipe, buffer, transfer_len,
1529 setup, "SUB", usb_pipein(pipe));
1530 #else
1531 ohci_mdelay(1);
1532 #endif
1533 if (!maxsize) {
1534 err("submit_common_message: pipesize for pipe %lx is zero",
1535 pipe);
1536 return -1;
1537 }
1538
1539 ohci_dev = ohci_get_ohci_dev(ohci, dev->devnum, usb_pipeint(pipe));
1540 if (!ohci_dev)
1541 return -ENOMEM;
1542
1543 if (sohci_submit_job(ohci, ohci_dev, urb, setup) < 0) {
1544 err("sohci_submit_job failed");
1545 return -1;
1546 }
1547
1548 #if 0
1549 mdelay(10);
1550 /* ohci_dump_status(ohci); */
1551 #endif
1552
1553 timeout = USB_TIMEOUT_MS(pipe);
1554
1555 /* wait for it to complete */
1556 for (;;) {
1557 /* check whether the controller is done */
1558 stat = hc_interrupt(ohci);
1559 if (stat < 0) {
1560 stat = USB_ST_CRC_ERR;
1561 break;
1562 }
1563
1564 /* NOTE: since we are not interrupt driven in U-Boot and always
1565 * handle only one URB at a time, we cannot assume the
1566 * transaction finished on the first successful return from
1567 * hc_interrupt().. unless the flag for current URB is set,
1568 * meaning that all TD's to/from device got actually
1569 * transferred and processed. If the current URB is not
1570 * finished we need to re-iterate this loop so as
1571 * hc_interrupt() gets called again as there needs to be some
1572 * more TD's to process still */
1573 if ((stat >= 0) && (stat != 0xff) && (urb->finished)) {
1574 /* 0xff is returned for an SF-interrupt */
1575 break;
1576 }
1577
1578 if (--timeout) {
1579 mdelay(1);
1580 if (!urb->finished)
1581 dbg("*");
1582
1583 } else {
1584 if (!usb_pipeint(pipe))
1585 err("CTL:TIMEOUT ");
1586 dbg("submit_common_msg: TO status %x\n", stat);
1587 urb->finished = 1;
1588 stat = USB_ST_CRC_ERR;
1589 break;
1590 }
1591 }
1592
1593 dev->status = stat;
1594 dev->act_len = urb->actual_length;
1595
1596 if (usb_pipein(pipe) && dev->status == 0 && dev->act_len)
1597 invalidate_dcache_buffer(buffer, dev->act_len);
1598
1599 #ifdef DEBUG
1600 pkt_print(ohci, urb, dev, pipe, buffer, transfer_len,
1601 setup, "RET(ctlr)", usb_pipein(pipe));
1602 #else
1603 ohci_mdelay(1);
1604 #endif
1605 urb_free_priv(urb);
1606 return 0;
1607 }
1608
1609 #define MAX_INT_QUEUESIZE 8
1610
1611 struct int_queue {
1612 int queuesize;
1613 int curr_urb;
1614 urb_priv_t *urb[MAX_INT_QUEUESIZE];
1615 };
1616
_ohci_create_int_queue(ohci_t * ohci,struct usb_device * udev,unsigned long pipe,int queuesize,int elementsize,void * buffer,int interval)1617 static struct int_queue *_ohci_create_int_queue(ohci_t *ohci,
1618 struct usb_device *udev, unsigned long pipe, int queuesize,
1619 int elementsize, void *buffer, int interval)
1620 {
1621 struct int_queue *queue;
1622 ohci_dev_t *ohci_dev;
1623 int i;
1624
1625 if (queuesize > MAX_INT_QUEUESIZE)
1626 return NULL;
1627
1628 ohci_dev = ohci_get_ohci_dev(ohci, udev->devnum, 1);
1629 if (!ohci_dev)
1630 return NULL;
1631
1632 queue = malloc(sizeof(*queue));
1633 if (!queue) {
1634 printf("ohci: Error out of memory allocating int queue\n");
1635 return NULL;
1636 }
1637
1638 for (i = 0; i < queuesize; i++) {
1639 queue->urb[i] = ohci_alloc_urb(udev, pipe,
1640 buffer + i * elementsize,
1641 elementsize, interval);
1642 if (!queue->urb[i])
1643 break;
1644
1645 if (sohci_submit_job(ohci, ohci_dev, queue->urb[i], NULL)) {
1646 printf("ohci: Error submitting int queue job\n");
1647 urb_free_priv(queue->urb[i]);
1648 break;
1649 }
1650 }
1651 if (i == 0) {
1652 /* We did not succeed in submitting even 1 urb */
1653 free(queue);
1654 return NULL;
1655 }
1656
1657 queue->queuesize = i;
1658 queue->curr_urb = 0;
1659
1660 return queue;
1661 }
1662
_ohci_poll_int_queue(ohci_t * ohci,struct usb_device * udev,struct int_queue * queue)1663 static void *_ohci_poll_int_queue(ohci_t *ohci, struct usb_device *udev,
1664 struct int_queue *queue)
1665 {
1666 if (queue->curr_urb == queue->queuesize)
1667 return NULL; /* Queue depleted */
1668
1669 if (hc_interrupt(ohci) < 0)
1670 return NULL;
1671
1672 if (queue->urb[queue->curr_urb]->finished) {
1673 void *ret = queue->urb[queue->curr_urb]->transfer_buffer;
1674 queue->curr_urb++;
1675 return ret;
1676 }
1677
1678 return NULL;
1679 }
1680
_ohci_destroy_int_queue(ohci_t * ohci,struct usb_device * dev,struct int_queue * queue)1681 static int _ohci_destroy_int_queue(ohci_t *ohci, struct usb_device *dev,
1682 struct int_queue *queue)
1683 {
1684 int i;
1685
1686 for (i = 0; i < queue->queuesize; i++)
1687 urb_free_priv(queue->urb[i]);
1688
1689 free(queue);
1690
1691 return 0;
1692 }
1693
1694 #ifndef CONFIG_DM_USB
1695 /* submit routines called from usb.c */
submit_bulk_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len)1696 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1697 int transfer_len)
1698 {
1699 info("submit_bulk_msg");
1700 return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len,
1701 NULL, 0);
1702 }
1703
submit_int_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,int interval)1704 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1705 int transfer_len, int interval)
1706 {
1707 info("submit_int_msg");
1708 return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, NULL,
1709 interval);
1710 }
1711
create_int_queue(struct usb_device * dev,unsigned long pipe,int queuesize,int elementsize,void * buffer,int interval)1712 struct int_queue *create_int_queue(struct usb_device *dev,
1713 unsigned long pipe, int queuesize, int elementsize,
1714 void *buffer, int interval)
1715 {
1716 return _ohci_create_int_queue(&gohci, dev, pipe, queuesize,
1717 elementsize, buffer, interval);
1718 }
1719
poll_int_queue(struct usb_device * dev,struct int_queue * queue)1720 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1721 {
1722 return _ohci_poll_int_queue(&gohci, dev, queue);
1723 }
1724
destroy_int_queue(struct usb_device * dev,struct int_queue * queue)1725 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1726 {
1727 return _ohci_destroy_int_queue(&gohci, dev, queue);
1728 }
1729 #endif
1730
_ohci_submit_control_msg(ohci_t * ohci,struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * setup)1731 static int _ohci_submit_control_msg(ohci_t *ohci, struct usb_device *dev,
1732 unsigned long pipe, void *buffer, int transfer_len,
1733 struct devrequest *setup)
1734 {
1735 int maxsize = usb_maxpacket(dev, pipe);
1736
1737 info("submit_control_msg");
1738 #ifdef DEBUG
1739 pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len,
1740 setup, "SUB", usb_pipein(pipe));
1741 #else
1742 ohci_mdelay(1);
1743 #endif
1744 if (!maxsize) {
1745 err("submit_control_message: pipesize for pipe %lx is zero",
1746 pipe);
1747 return -1;
1748 }
1749 if (((pipe >> 8) & 0x7f) == ohci->rh.devnum) {
1750 ohci->rh.dev = dev;
1751 /* root hub - redirect */
1752 return ohci_submit_rh_msg(ohci, dev, pipe, buffer,
1753 transfer_len, setup);
1754 }
1755
1756 return submit_common_msg(ohci, dev, pipe, buffer, transfer_len,
1757 setup, 0);
1758 }
1759
1760 /*-------------------------------------------------------------------------*
1761 * HC functions
1762 *-------------------------------------------------------------------------*/
1763
1764 /* reset the HC and BUS */
1765
hc_reset(ohci_t * ohci)1766 static int hc_reset(ohci_t *ohci)
1767 {
1768 #ifdef CONFIG_PCI_EHCI_DEVNO
1769 pci_dev_t pdev;
1770 #endif
1771 int timeout = 30;
1772 int smm_timeout = 50; /* 0,5 sec */
1773
1774 dbg("%s\n", __FUNCTION__);
1775
1776 #ifdef CONFIG_PCI_EHCI_DEVNO
1777 /*
1778 * Some multi-function controllers (e.g. ISP1562) allow root hub
1779 * resetting via EHCI registers only.
1780 */
1781 pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO);
1782 if (pdev != -1) {
1783 u32 base;
1784 int timeout = 1000;
1785
1786 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
1787 base += EHCI_USBCMD_OFF;
1788 ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base);
1789
1790 while (ohci_readl(base) & EHCI_USBCMD_HCRESET) {
1791 if (timeout-- <= 0) {
1792 printf("USB RootHub reset timed out!");
1793 break;
1794 }
1795 udelay(1);
1796 }
1797 } else
1798 printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO);
1799 #endif
1800 if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
1801 /* SMM owns the HC, request ownership */
1802 ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus);
1803 info("USB HC TakeOver from SMM");
1804 while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
1805 mdelay(10);
1806 if (--smm_timeout == 0) {
1807 err("USB HC TakeOver failed!");
1808 return -1;
1809 }
1810 }
1811 }
1812
1813 /* Disable HC interrupts */
1814 ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
1815
1816 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
1817 ohci->slot_name,
1818 ohci_readl(&ohci->regs->control));
1819
1820 /* Reset USB (needed by some controllers) */
1821 ohci->hc_control = 0;
1822 ohci_writel(ohci->hc_control, &ohci->regs->control);
1823
1824 /* HC Reset requires max 10 us delay */
1825 ohci_writel(OHCI_HCR, &ohci->regs->cmdstatus);
1826 while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1827 if (--timeout == 0) {
1828 err("USB HC reset timed out!");
1829 return -1;
1830 }
1831 udelay(1);
1832 }
1833 return 0;
1834 }
1835
1836 /*-------------------------------------------------------------------------*/
1837
1838 /* Start an OHCI controller, set the BUS operational
1839 * enable interrupts
1840 * connect the virtual root hub */
1841
hc_start(ohci_t * ohci)1842 static int hc_start(ohci_t *ohci)
1843 {
1844 __u32 mask;
1845 unsigned int fminterval;
1846 int i;
1847
1848 ohci->disabled = 1;
1849 for (i = 0; i < NUM_INT_DEVS; i++)
1850 ohci->int_dev[i].devnum = -1;
1851
1852 /* Tell the controller where the control and bulk lists are
1853 * The lists are empty now. */
1854
1855 ohci_writel(0, &ohci->regs->ed_controlhead);
1856 ohci_writel(0, &ohci->regs->ed_bulkhead);
1857
1858 ohci_writel((uintptr_t)ohci->hcca,
1859 &ohci->regs->hcca); /* reset clears this */
1860
1861 fminterval = 0x2edf;
1862 ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
1863 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1864 ohci_writel(fminterval, &ohci->regs->fminterval);
1865 ohci_writel(0x628, &ohci->regs->lsthresh);
1866
1867 /* start controller operations */
1868 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1869 ohci->disabled = 0;
1870 ohci_writel(ohci->hc_control, &ohci->regs->control);
1871
1872 /* disable all interrupts */
1873 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1874 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1875 OHCI_INTR_OC | OHCI_INTR_MIE);
1876 ohci_writel(mask, &ohci->regs->intrdisable);
1877 /* clear all interrupts */
1878 mask &= ~OHCI_INTR_MIE;
1879 ohci_writel(mask, &ohci->regs->intrstatus);
1880 /* Choose the interrupts we care about now - but w/o MIE */
1881 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1882 ohci_writel(mask, &ohci->regs->intrenable);
1883
1884 #ifdef OHCI_USE_NPS
1885 /* required for AMD-756 and some Mac platforms */
1886 ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
1887 &ohci->regs->roothub.a);
1888 ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status);
1889 #endif /* OHCI_USE_NPS */
1890
1891 /* connect the virtual root hub */
1892 ohci->rh.devnum = 0;
1893
1894 return 0;
1895 }
1896
1897 /*-------------------------------------------------------------------------*/
1898
1899 /* an interrupt happens */
1900
hc_interrupt(ohci_t * ohci)1901 static int hc_interrupt(ohci_t *ohci)
1902 {
1903 struct ohci_regs *regs = ohci->regs;
1904 int ints;
1905 int stat = -1;
1906
1907 invalidate_dcache_hcca(ohci->hcca);
1908
1909 if ((ohci->hcca->done_head != 0) &&
1910 !(m32_swap(ohci->hcca->done_head) & 0x01)) {
1911 ints = OHCI_INTR_WDH;
1912 } else {
1913 ints = ohci_readl(®s->intrstatus);
1914 if (ints == ~(u32)0) {
1915 ohci->disabled++;
1916 err("%s device removed!", ohci->slot_name);
1917 return -1;
1918 } else {
1919 ints &= ohci_readl(®s->intrenable);
1920 if (ints == 0) {
1921 dbg("hc_interrupt: returning..\n");
1922 return 0xff;
1923 }
1924 }
1925 }
1926
1927 /* dbg("Interrupt: %x frame: %x", ints,
1928 le16_to_cpu(ohci->hcca->frame_no)); */
1929
1930 if (ints & OHCI_INTR_RHSC)
1931 stat = 0xff;
1932
1933 if (ints & OHCI_INTR_UE) {
1934 ohci->disabled++;
1935 err("OHCI Unrecoverable Error, controller usb-%s disabled",
1936 ohci->slot_name);
1937 /* e.g. due to PCI Master/Target Abort */
1938
1939 #ifdef DEBUG
1940 ohci_dump(ohci, 1);
1941 #else
1942 ohci_mdelay(1);
1943 #endif
1944 /* FIXME: be optimistic, hope that bug won't repeat often. */
1945 /* Make some non-interrupt context restart the controller. */
1946 /* Count and limit the retries though; either hardware or */
1947 /* software errors can go forever... */
1948 hc_reset(ohci);
1949 return -1;
1950 }
1951
1952 if (ints & OHCI_INTR_WDH) {
1953 ohci_mdelay(1);
1954 ohci_writel(OHCI_INTR_WDH, ®s->intrdisable);
1955 (void)ohci_readl(®s->intrdisable); /* flush */
1956 stat = dl_done_list(ohci);
1957 ohci_writel(OHCI_INTR_WDH, ®s->intrenable);
1958 (void)ohci_readl(®s->intrdisable); /* flush */
1959 }
1960
1961 if (ints & OHCI_INTR_SO) {
1962 dbg("USB Schedule overrun\n");
1963 ohci_writel(OHCI_INTR_SO, ®s->intrenable);
1964 stat = -1;
1965 }
1966
1967 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1968 if (ints & OHCI_INTR_SF) {
1969 unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
1970 mdelay(1);
1971 ohci_writel(OHCI_INTR_SF, ®s->intrdisable);
1972 if (ohci->ed_rm_list[frame] != NULL)
1973 ohci_writel(OHCI_INTR_SF, ®s->intrenable);
1974 stat = 0xff;
1975 }
1976
1977 ohci_writel(ints, ®s->intrstatus);
1978 return stat;
1979 }
1980
1981 /*-------------------------------------------------------------------------*/
1982
1983 #ifndef CONFIG_DM_USB
1984
1985 /*-------------------------------------------------------------------------*/
1986
1987 /* De-allocate all resources.. */
1988
hc_release_ohci(ohci_t * ohci)1989 static void hc_release_ohci(ohci_t *ohci)
1990 {
1991 dbg("USB HC release ohci usb-%s", ohci->slot_name);
1992
1993 if (!ohci->disabled)
1994 hc_reset(ohci);
1995 }
1996
1997 /*-------------------------------------------------------------------------*/
1998
1999 /*
2000 * low level initalisation routine, called from usb.c
2001 */
2002 static char ohci_inited = 0;
2003
usb_lowlevel_init(int index,enum usb_init_type init,void ** controller)2004 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
2005 {
2006 #ifdef CONFIG_PCI_OHCI
2007 pci_dev_t pdev;
2008 #endif
2009
2010 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
2011 /* cpu dependant init */
2012 if (usb_cpu_init())
2013 return -1;
2014 #endif
2015
2016 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
2017 /* board dependant init */
2018 if (board_usb_init(index, USB_INIT_HOST))
2019 return -1;
2020 #endif
2021 memset(&gohci, 0, sizeof(ohci_t));
2022
2023 /* align the storage */
2024 if ((__u32)&ghcca[0] & 0xff) {
2025 err("HCCA not aligned!!");
2026 return -1;
2027 }
2028 gohci.hcca = &ghcca[0];
2029 info("aligned ghcca %p", gohci.hcca);
2030 memset(gohci.hcca, 0, sizeof(struct ohci_hcca));
2031
2032 gohci.disabled = 1;
2033 gohci.sleeping = 0;
2034 gohci.irq = -1;
2035 #ifdef CONFIG_PCI_OHCI
2036 pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO);
2037
2038 if (pdev != -1) {
2039 u16 vid, did;
2040 u32 base;
2041 pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);
2042 pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
2043 printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",
2044 vid, did, (pdev >> 16) & 0xff,
2045 (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
2046 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
2047 printf("OHCI regs address 0x%08x\n", base);
2048 gohci.regs = (struct ohci_regs *)base;
2049 } else
2050 return -1;
2051 #else
2052 gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE;
2053 #endif
2054
2055 gohci.flags = 0;
2056 gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME;
2057
2058 if (hc_reset (&gohci) < 0) {
2059 hc_release_ohci (&gohci);
2060 err ("can't reset usb-%s", gohci.slot_name);
2061 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
2062 /* board dependant cleanup */
2063 board_usb_cleanup(index, USB_INIT_HOST);
2064 #endif
2065
2066 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
2067 /* cpu dependant cleanup */
2068 usb_cpu_init_fail();
2069 #endif
2070 return -1;
2071 }
2072
2073 if (hc_start(&gohci) < 0) {
2074 err("can't start usb-%s", gohci.slot_name);
2075 hc_release_ohci(&gohci);
2076 /* Initialization failed */
2077 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
2078 /* board dependant cleanup */
2079 usb_board_stop();
2080 #endif
2081
2082 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
2083 /* cpu dependant cleanup */
2084 usb_cpu_stop();
2085 #endif
2086 return -1;
2087 }
2088
2089 #ifdef DEBUG
2090 ohci_dump(&gohci, 1);
2091 #else
2092 ohci_mdelay(1);
2093 #endif
2094 ohci_inited = 1;
2095 return 0;
2096 }
2097
usb_lowlevel_stop(int index)2098 int usb_lowlevel_stop(int index)
2099 {
2100 /* this gets called really early - before the controller has */
2101 /* even been initialized! */
2102 if (!ohci_inited)
2103 return 0;
2104 /* TODO release any interrupts, etc. */
2105 /* call hc_release_ohci() here ? */
2106 hc_reset(&gohci);
2107
2108 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
2109 /* board dependant cleanup */
2110 if (usb_board_stop())
2111 return -1;
2112 #endif
2113
2114 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
2115 /* cpu dependant cleanup */
2116 if (usb_cpu_stop())
2117 return -1;
2118 #endif
2119 /* This driver is no longer initialised. It needs a new low-level
2120 * init (board/cpu) before it can be used again. */
2121 ohci_inited = 0;
2122 return 0;
2123 }
2124
submit_control_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int transfer_len,struct devrequest * setup)2125 int submit_control_msg(struct usb_device *dev, unsigned long pipe,
2126 void *buffer, int transfer_len, struct devrequest *setup)
2127 {
2128 return _ohci_submit_control_msg(&gohci, dev, pipe, buffer,
2129 transfer_len, setup);
2130 }
2131 #endif
2132
2133 #ifdef CONFIG_DM_USB
ohci_submit_control_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,struct devrequest * setup)2134 static int ohci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
2135 unsigned long pipe, void *buffer, int length,
2136 struct devrequest *setup)
2137 {
2138 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2139
2140 return _ohci_submit_control_msg(ohci, udev, pipe, buffer,
2141 length, setup);
2142 }
2143
ohci_submit_bulk_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length)2144 static int ohci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
2145 unsigned long pipe, void *buffer, int length)
2146 {
2147 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2148
2149 return submit_common_msg(ohci, udev, pipe, buffer, length, NULL, 0);
2150 }
2151
ohci_submit_int_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,int interval)2152 static int ohci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
2153 unsigned long pipe, void *buffer, int length,
2154 int interval)
2155 {
2156 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2157
2158 return submit_common_msg(ohci, udev, pipe, buffer, length,
2159 NULL, interval);
2160 }
2161
ohci_create_int_queue(struct udevice * dev,struct usb_device * udev,unsigned long pipe,int queuesize,int elementsize,void * buffer,int interval)2162 static struct int_queue *ohci_create_int_queue(struct udevice *dev,
2163 struct usb_device *udev, unsigned long pipe, int queuesize,
2164 int elementsize, void *buffer, int interval)
2165 {
2166 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2167
2168 return _ohci_create_int_queue(ohci, udev, pipe, queuesize, elementsize,
2169 buffer, interval);
2170 }
2171
ohci_poll_int_queue(struct udevice * dev,struct usb_device * udev,struct int_queue * queue)2172 static void *ohci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
2173 struct int_queue *queue)
2174 {
2175 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2176
2177 return _ohci_poll_int_queue(ohci, udev, queue);
2178 }
2179
ohci_destroy_int_queue(struct udevice * dev,struct usb_device * udev,struct int_queue * queue)2180 static int ohci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
2181 struct int_queue *queue)
2182 {
2183 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2184
2185 return _ohci_destroy_int_queue(ohci, udev, queue);
2186 }
2187
ohci_register(struct udevice * dev,struct ohci_regs * regs)2188 int ohci_register(struct udevice *dev, struct ohci_regs *regs)
2189 {
2190 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
2191 ohci_t *ohci = dev_get_priv(dev);
2192 u32 reg;
2193
2194 priv->desc_before_addr = true;
2195
2196 ohci->regs = regs;
2197 ohci->hcca = memalign(256, sizeof(struct ohci_hcca));
2198 if (!ohci->hcca)
2199 return -ENOMEM;
2200 memset(ohci->hcca, 0, sizeof(struct ohci_hcca));
2201 flush_dcache_hcca(ohci->hcca);
2202
2203 if (hc_reset(ohci) < 0)
2204 return -EIO;
2205
2206 if (hc_start(ohci) < 0)
2207 return -EIO;
2208
2209 reg = ohci_readl(®s->revision);
2210 printf("USB OHCI %x.%x\n", (reg >> 4) & 0xf, reg & 0xf);
2211
2212 return 0;
2213 }
2214
ohci_deregister(struct udevice * dev)2215 int ohci_deregister(struct udevice *dev)
2216 {
2217 ohci_t *ohci = dev_get_priv(dev);
2218
2219 if (hc_reset(ohci) < 0)
2220 return -EIO;
2221
2222 free(ohci->hcca);
2223
2224 return 0;
2225 }
2226
2227 struct dm_usb_ops ohci_usb_ops = {
2228 .control = ohci_submit_control_msg,
2229 .bulk = ohci_submit_bulk_msg,
2230 .interrupt = ohci_submit_int_msg,
2231 .create_int_queue = ohci_create_int_queue,
2232 .poll_int_queue = ohci_poll_int_queue,
2233 .destroy_int_queue = ohci_destroy_int_queue,
2234 };
2235
2236 #endif
2237