| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/ |
| D | orr.s | 12 orr z5.b, z5.b, #0xf9 label
18 orr z23.h, z23.h, #0xfff9 label
24 orr z0.s, z0.s, #0xfffffff9 label
30 orr z0.d, z0.d, #0xfffffffffffffff9 label
36 orr z5.b, z5.b, #0x6 label
42 orr z23.h, z23.h, #0x6 label
48 orr z0.s, z0.s, #0x6 label
54 orr z0.d, z0.d, #0x6 label
60 orr z0.d, z0.d, z0.d // should use mov-alias label
66 orr z23.d, z13.d, z8.d // should not use mov-alias label
[all …]
|
| D | orr-diagnostics.s | 6 orr z5.b, z5.b, #0xfa label
11 orr z5.b, z5.b, #0xfff9 label
16 orr z5.h, z5.h, #0xfffa label
21 orr z5.h, z5.h, #0xfffffff9 label
26 orr z5.s, z5.s, #0xfffffffa label
31 orr z5.s, z5.s, #0xffffffffffffff9 label
36 orr z15.d, z15.d, #0xfffffffffffffffa label
44 orr z7.d, z8.d, #254 label
49 orr z0.d, p0/m, z1.d, z2.d label
55 orr z21.d, z5.d, z26.b label
[all …]
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | arm-arithmetic-aliases.s | 36 orr r2, r2, #6 label
37 orr r2, #6 label
38 orr r2, r2, r3 label
39 orr r2, r3 label
|
| /external/llvm/test/MC/ARM/ |
| D | arm-arithmetic-aliases.s | 36 orr r2, r2, #6 label
37 orr r2, #6 label
38 orr r2, r2, r3 label
39 orr r2, r3 label
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | arm-arithmetic-aliases.s | 36 orr r2, r2, #6 label
37 orr r2, #6 label
38 orr r2, r2, r3 label
39 orr r2, r3 label
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | arm64-diags.s | 319 orr w0, w0, w0, lsl #32 label
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-diags.s | 258 orr w0, w0, w0, lsl #32 label
|
| /external/v8/src/arm/ |
| D | deoptimizer-arm.cc | 278 __ orr(scratch, scratch, Operand(high << 8)); in GeneratePrologue() local
|
| D | assembler-arm.cc | 1576 void Assembler::orr(Register dst, Register src1, const Operand& src2, in orr() function in v8::internal::Assembler
1581 void Assembler::orr(Register dst, Register src1, Register src2, SBit s, in orr() function in v8::internal::Assembler
|
| /external/v8/src/regexp/arm/ |
| D | regexp-macro-assembler-arm.cc | 258 __ orr(r3, r3, Operand(0x20)); // Convert capture character to lower-case. in CheckNotBackReferenceIgnoreCase() local
259 __ orr(r4, r4, Operand(0x20)); // Also convert input character. in CheckNotBackReferenceIgnoreCase() local
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 265 __ orr(w6, w7, w8); in GenerateTestSequenceBase() local
266 __ orr(x9, x10, x11); in GenerateTestSequenceBase() local
1307 __ orr(v17.V16B(), v17.V16B(), v23.V16B()); in GenerateTestSequenceNEON() local
1308 __ orr(v8.V2S(), 0xe3); in GenerateTestSequenceNEON() local
1309 __ orr(v11.V4H(), 0x97, 8); in GenerateTestSequenceNEON() local
1310 __ orr(v7.V4S(), 0xab); in GenerateTestSequenceNEON() local
1311 __ orr(v8.V8B(), v4.V8B(), v3.V8B()); in GenerateTestSequenceNEON() local
1312 __ orr(v31.V8H(), 0xb0, 8); in GenerateTestSequenceNEON() local
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-aarch32.cc | 688 __ orr(r0, r5, r6); in TEST() local
692 __ orr(r2, r2, 1); in TEST() local
703 __ orr(r2, r2, 1); in TEST() local
715 __ orr(r5, r5, 1); in TEST() local
5579 __ orr(r11, r11, 1); in TEST() local
|
| /external/boringssl/src/crypto/curve25519/asm/ |
| D | x25519-asm-arm.S | 89 orr r6,r6,#64 label
|
| /external/skia/fuzz/ |
| D | FuzzCanvas.cpp | 1255 SkRRect orr, irr; in fuzz_canvas() local
|
| /external/skqp/fuzz/ |
| D | FuzzCanvas.cpp | 1255 SkRRect orr, irr; in fuzz_canvas() local
|
| /external/v8/src/builtins/arm/ |
| D | builtins-arm.cc | 2488 __ orr(result_reg, result_reg, in Generate_DoubleToI() local
2490 __ orr(result_reg, double_low, Operand(result_reg, LSL, scratch)); in Generate_DoubleToI() local
|
| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 1238 void Assembler::orr(const Register& rd, in orr() function in v8::internal::Assembler
3576 void Assembler::orr(const VRegister& vd, const int imm8, const int left_shift) { in orr() function in v8::internal::Assembler
|
| D | simulator-logic-arm64.cc | 1002 LogicVRegister Simulator::orr(VectorFormat vform, LogicVRegister dst, in orr() function in v8::internal::Simulator
2052 LogicVRegister Simulator::orr(VectorFormat vform, LogicVRegister dst, in orr() function in v8::internal::Simulator
|
| /external/vixl/benchmarks/aarch32/ |
| D | asm-disasm-speed-test.cc | 487 __ orr(r8, r8, r2); in Generate_3() local
500 __ orr(r8, r8, r3); in Generate_3() local
891 __ orr(r3, r3, 0x8000); in Generate_6() local
892 __ orr(r3, r3, 0x60); in Generate_6() local
2476 __ orr(r3, r3, 0x8000); in Generate_19() local
2478 __ orr(r3, r3, 0x60); in Generate_19() local
2854 __ orr(r8, r8, r1); in Generate_22() local
2864 __ orr(r8, r8, r3); in Generate_22() local
4269 __ orr(lt, r1, r1, 0x1); in Generate_32() local
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 595 void Assembler::orr(const Register& rd, in orr() function in vixl::aarch64::Assembler
3735 void Assembler::orr(const VRegister& vd, const int imm8, const int left_shift) { in orr() function in vixl::aarch64::Assembler
|
| D | logic-aarch64.cc | 1041 LogicVRegister Simulator::orr(VectorFormat vform, in orr() function in vixl::aarch64::Simulator
2500 LogicVRegister Simulator::orr(VectorFormat vform, in orr() function in vixl::aarch64::Simulator
|
| /external/v8/src/compiler/arm/ |
| D | code-generator-arm.cc | 1117 __ orr(i.OutputRegister(), i.InputRegister(0), i.InputOperand2(1), in AssembleArchInstruction() local
|
| /external/skqp/tests/ |
| D | PathTest.cpp | 4860 SkRRect orr; in DEF_TEST() local
|
| /external/skia/tests/ |
| D | PathTest.cpp | 4887 SkRRect orr; in DEF_TEST() local
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2734 void orr(Register rd, Register rn, const Operand& operand) { in orr() function
2737 void orr(Condition cond, Register rd, Register rn, const Operand& operand) { in orr() function
2740 void orr(EncodingSize size, in orr() function
|