1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_SDRAM_RK3399_H 7 #define _ASM_ARCH_SDRAM_RK3399_H 8 9 enum { 10 DDR3 = 0x3, 11 LPDDR2 = 0x5, 12 LPDDR3 = 0x6, 13 LPDDR4 = 0x7, 14 UNUSED = 0xFF 15 }; 16 17 struct rk3399_ddr_pctl_regs { 18 u32 denali_ctl[332]; 19 }; 20 21 struct rk3399_ddr_publ_regs { 22 u32 denali_phy[959]; 23 }; 24 25 struct rk3399_ddr_pi_regs { 26 u32 denali_pi[200]; 27 }; 28 29 struct rk3399_msch_regs { 30 u32 coreid; 31 u32 revisionid; 32 u32 ddrconf; 33 u32 ddrsize; 34 u32 ddrtiminga0; 35 u32 ddrtimingb0; 36 u32 ddrtimingc0; 37 u32 devtodev0; 38 u32 reserved0[(0x110 - 0x20) / 4]; 39 u32 ddrmode; 40 u32 reserved1[(0x1000 - 0x114) / 4]; 41 u32 agingx0; 42 }; 43 44 struct rk3399_msch_timings { 45 u32 ddrtiminga0; 46 u32 ddrtimingb0; 47 u32 ddrtimingc0; 48 u32 devtodev0; 49 u32 ddrmode; 50 u32 agingx0; 51 }; 52 53 struct rk3399_ddr_cic_regs { 54 u32 cic_ctrl0; 55 u32 cic_ctrl1; 56 u32 cic_idle_th; 57 u32 cic_cg_wait_th; 58 u32 cic_status0; 59 u32 cic_status1; 60 u32 cic_ctrl2; 61 u32 cic_ctrl3; 62 u32 cic_ctrl4; 63 }; 64 65 /* DENALI_CTL_00 */ 66 #define START 1 67 68 /* DENALI_CTL_68 */ 69 #define PWRUP_SREFRESH_EXIT (1 << 16) 70 71 /* DENALI_CTL_274 */ 72 #define MEM_RST_VALID 1 73 74 struct rk3399_sdram_channel { 75 unsigned int rank; 76 /* dram column number, 0 means this channel is invalid */ 77 unsigned int col; 78 /* dram bank number, 3:8bank, 2:4bank */ 79 unsigned int bk; 80 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ 81 unsigned int bw; 82 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 83 unsigned int dbw; 84 /* 85 * row_3_4 = 1: 6Gb or 12Gb die 86 * row_3_4 = 0: normal die, power of 2 87 */ 88 unsigned int row_3_4; 89 unsigned int cs0_row; 90 unsigned int cs1_row; 91 unsigned int ddrconfig; 92 struct rk3399_msch_timings noc_timings; 93 }; 94 95 struct rk3399_base_params { 96 unsigned int ddr_freq; 97 unsigned int dramtype; 98 unsigned int num_channels; 99 unsigned int stride; 100 unsigned int odt; 101 }; 102 103 struct rk3399_sdram_params { 104 struct rk3399_sdram_channel ch[2]; 105 struct rk3399_base_params base; 106 struct rk3399_ddr_pctl_regs pctl_regs; 107 struct rk3399_ddr_pi_regs pi_regs; 108 struct rk3399_ddr_publ_regs phy_regs; 109 }; 110 111 #define PI_CA_TRAINING (1 << 0) 112 #define PI_WRITE_LEVELING (1 << 1) 113 #define PI_READ_GATE_TRAINING (1 << 2) 114 #define PI_READ_LEVELING (1 << 3) 115 #define PI_WDQ_LEVELING (1 << 4) 116 #define PI_FULL_TRAINING 0xff 117 118 #endif 119