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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Renesas RCar Gen3 CPG MSSR driver
4  *
5  * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
6  *
7  * Based on the following driver from Linux kernel:
8  * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
9  *
10  * Copyright (C) 2016 Glider bvba
11  */
12 
13 #ifndef __DRIVERS_CLK_RENESAS_CPG_MSSR__
14 #define __DRIVERS_CLK_RENESAS_CPG_MSSR__
15 
16 struct cpg_mssr_info {
17 	const struct cpg_core_clk	*core_clk;
18 	unsigned int			core_clk_size;
19 	const struct mssr_mod_clk	*mod_clk;
20 	unsigned int			mod_clk_size;
21 	const struct mstp_stop_table	*mstp_table;
22 	unsigned int			mstp_table_size;
23 	const char			*reset_node;
24 	const char			*extalr_node;
25 	const char			*extal_usb_node;
26 	unsigned int			mod_clk_base;
27 	unsigned int			clk_extal_id;
28 	unsigned int			clk_extalr_id;
29 	unsigned int			clk_extal_usb_id;
30 	unsigned int			pll0_div;
31 	const void			*(*get_pll_config)(const u32 cpg_mode);
32 };
33 
34 /*
35  * Definitions of CPG Core Clocks
36  *
37  * These include:
38  *   - Clock outputs exported to DT
39  *   - External input clocks
40  *   - Internal CPG clocks
41  */
42 struct cpg_core_clk {
43 	/* Common */
44 	const char *name;
45 	unsigned int id;
46 	unsigned int type;
47 	/* Depending on type */
48 	unsigned int parent;	/* Core Clocks only */
49 	unsigned int div;
50 	unsigned int mult;
51 	unsigned int offset;
52 };
53 
54 enum clk_types {
55 	/* Generic */
56 	CLK_TYPE_IN,		/* External Clock Input */
57 	CLK_TYPE_FF,		/* Fixed Factor Clock */
58 	CLK_TYPE_DIV6P1,	/* DIV6 Clock with 1 parent clock */
59 	CLK_TYPE_DIV6_RO,	/* DIV6 Clock read only with extra divisor */
60 
61 	/* Custom definitions start here */
62 	CLK_TYPE_CUSTOM,
63 };
64 
65 #define DEF_TYPE(_name, _id, _type...)	\
66 	{ .name = _name, .id = _id, .type = _type }
67 #define DEF_BASE(_name, _id, _type, _parent...)	\
68 	DEF_TYPE(_name, _id, _type, .parent = _parent)
69 
70 #define DEF_INPUT(_name, _id) \
71 	DEF_TYPE(_name, _id, CLK_TYPE_IN)
72 #define DEF_FIXED(_name, _id, _parent, _div, _mult)	\
73 	DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
74 #define DEF_DIV6P1(_name, _id, _parent, _offset)	\
75 	DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
76 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div)	\
77 	DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
78 
79 /*
80  * Definitions of Module Clocks
81  */
82 struct mssr_mod_clk {
83 	const char *name;
84 	unsigned int id;
85 	unsigned int parent;	/* Add MOD_CLK_BASE for Module Clocks */
86 };
87 
88 /* Convert from sparse base-100 to packed index space */
89 #define MOD_CLK_PACK(x)	((x) - ((x) / 100) * (100 - 32))
90 
91 #define MOD_CLK_ID(x)	(MOD_CLK_BASE + MOD_CLK_PACK(x))
92 
93 #define DEF_MOD(_name, _mod, _parent...)	\
94 	{ .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
95 
96 struct mstp_stop_table {
97 	u32	sdis;
98 	u32	sen;
99 	u32	rdis;
100 	u32	ren;
101 };
102 
103 #define TSTR0		0x04
104 #define TSTR0_STR0	BIT(0)
105 
106 bool renesas_clk_is_mod(struct clk *clk);
107 int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
108 			const struct mssr_mod_clk **mssr);
109 int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
110 			 const struct cpg_core_clk **core);
111 int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
112 			   struct clk *parent);
113 int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable);
114 int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
115 
116 #endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */
117