1 //===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file includes common code for rendering MCInst instances as Intel-style
11 // and Intel-style assembly.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "X86InstPrinterCommon.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Support/Casting.h"
23 #include <cstdint>
24 #include <cassert>
25
26 using namespace llvm;
27
printSSEAVXCC(const MCInst * MI,unsigned Op,raw_ostream & O)28 void X86InstPrinterCommon::printSSEAVXCC(const MCInst *MI, unsigned Op,
29 raw_ostream &O) {
30 int64_t Imm = MI->getOperand(Op).getImm();
31 switch (Imm) {
32 default: llvm_unreachable("Invalid ssecc/avxcc argument!");
33 case 0: O << "eq"; break;
34 case 1: O << "lt"; break;
35 case 2: O << "le"; break;
36 case 3: O << "unord"; break;
37 case 4: O << "neq"; break;
38 case 5: O << "nlt"; break;
39 case 6: O << "nle"; break;
40 case 7: O << "ord"; break;
41 case 8: O << "eq_uq"; break;
42 case 9: O << "nge"; break;
43 case 0xa: O << "ngt"; break;
44 case 0xb: O << "false"; break;
45 case 0xc: O << "neq_oq"; break;
46 case 0xd: O << "ge"; break;
47 case 0xe: O << "gt"; break;
48 case 0xf: O << "true"; break;
49 case 0x10: O << "eq_os"; break;
50 case 0x11: O << "lt_oq"; break;
51 case 0x12: O << "le_oq"; break;
52 case 0x13: O << "unord_s"; break;
53 case 0x14: O << "neq_us"; break;
54 case 0x15: O << "nlt_uq"; break;
55 case 0x16: O << "nle_uq"; break;
56 case 0x17: O << "ord_s"; break;
57 case 0x18: O << "eq_us"; break;
58 case 0x19: O << "nge_uq"; break;
59 case 0x1a: O << "ngt_uq"; break;
60 case 0x1b: O << "false_os"; break;
61 case 0x1c: O << "neq_os"; break;
62 case 0x1d: O << "ge_oq"; break;
63 case 0x1e: O << "gt_oq"; break;
64 case 0x1f: O << "true_us"; break;
65 }
66 }
67
printXOPCC(const MCInst * MI,unsigned Op,raw_ostream & O)68 void X86InstPrinterCommon::printXOPCC(const MCInst *MI, unsigned Op,
69 raw_ostream &O) {
70 int64_t Imm = MI->getOperand(Op).getImm();
71 switch (Imm) {
72 default: llvm_unreachable("Invalid xopcc argument!");
73 case 0: O << "lt"; break;
74 case 1: O << "le"; break;
75 case 2: O << "gt"; break;
76 case 3: O << "ge"; break;
77 case 4: O << "eq"; break;
78 case 5: O << "neq"; break;
79 case 6: O << "false"; break;
80 case 7: O << "true"; break;
81 }
82 }
83
printRoundingControl(const MCInst * MI,unsigned Op,raw_ostream & O)84 void X86InstPrinterCommon::printRoundingControl(const MCInst *MI, unsigned Op,
85 raw_ostream &O) {
86 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
87 switch (Imm) {
88 case 0: O << "{rn-sae}"; break;
89 case 1: O << "{rd-sae}"; break;
90 case 2: O << "{ru-sae}"; break;
91 case 3: O << "{rz-sae}"; break;
92 }
93 }
94
95 /// printPCRelImm - This is used to print an immediate value that ends up
96 /// being encoded as a pc-relative value (e.g. for jumps and calls). In
97 /// Intel-style these print slightly differently than normal immediates.
98 /// for example, a $ is not emitted.
printPCRelImm(const MCInst * MI,unsigned OpNo,raw_ostream & O)99 void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, unsigned OpNo,
100 raw_ostream &O) {
101 const MCOperand &Op = MI->getOperand(OpNo);
102 if (Op.isImm())
103 O << formatImm(Op.getImm());
104 else {
105 assert(Op.isExpr() && "unknown pcrel immediate operand");
106 // If a symbolic branch target was added as a constant expression then print
107 // that address in hex.
108 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
109 int64_t Address;
110 if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
111 O << formatHex((uint64_t)Address);
112 } else {
113 // Otherwise, just print the expression.
114 Op.getExpr()->print(O, &MAI);
115 }
116 }
117 }
118
printOptionalSegReg(const MCInst * MI,unsigned OpNo,raw_ostream & O)119 void X86InstPrinterCommon::printOptionalSegReg(const MCInst *MI, unsigned OpNo,
120 raw_ostream &O) {
121 if (MI->getOperand(OpNo).getReg()) {
122 printOperand(MI, OpNo, O);
123 O << ':';
124 }
125 }
126
printInstFlags(const MCInst * MI,raw_ostream & O)127 void X86InstPrinterCommon::printInstFlags(const MCInst *MI, raw_ostream &O) {
128 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
129 uint64_t TSFlags = Desc.TSFlags;
130 unsigned Flags = MI->getFlags();
131
132 if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK))
133 O << "\tlock\t";
134
135 if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK))
136 O << "\tnotrack\t";
137
138 if (Flags & X86::IP_HAS_REPEAT_NE)
139 O << "\trepne\t";
140 else if (Flags & X86::IP_HAS_REPEAT)
141 O << "\trep\t";
142 }
143