1 /******************************************************************************
2 *
3 * Copyright (C) 2018 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20
21 /*!
22 ******************************************************************************
23 * \file ihevce_memory_init.c
24 *
25 * \brief
26 * This file contains functions which perform memory requirement gathering
27 * and freeing of memories of encoder at the end
28 *
29 * \date
30 * 18/09/2012
31 *
32 * \author
33 * Ittiam
34 *
35 * List of Functions
36 * <TODO: TO BE ADDED>
37 *
38 ******************************************************************************
39 */
40
41 /*****************************************************************************/
42 /* File Includes */
43 /*****************************************************************************/
44 /* System include files */
45 #include <stdio.h>
46 #include <string.h>
47 #include <stdlib.h>
48 #include <assert.h>
49 #include <stdarg.h>
50 #include <math.h>
51
52 /* User include files */
53 #include "ihevc_typedefs.h"
54 #include "itt_video_api.h"
55 #include "ihevce_api.h"
56
57 #include "rc_cntrl_param.h"
58 #include "rc_frame_info_collector.h"
59 #include "rc_look_ahead_params.h"
60
61 #include "ihevc_defs.h"
62 #include "ihevc_macros.h"
63 #include "ihevc_debug.h"
64 #include "ihevc_structs.h"
65 #include "ihevc_platform_macros.h"
66 #include "ihevc_deblk.h"
67 #include "ihevc_itrans_recon.h"
68 #include "ihevc_chroma_itrans_recon.h"
69 #include "ihevc_chroma_intra_pred.h"
70 #include "ihevc_intra_pred.h"
71 #include "ihevc_inter_pred.h"
72 #include "ihevc_mem_fns.h"
73 #include "ihevc_padding.h"
74 #include "ihevc_weighted_pred.h"
75 #include "ihevc_sao.h"
76 #include "ihevc_resi_trans.h"
77 #include "ihevc_quant_iquant_ssd.h"
78 #include "ihevc_cabac_tables.h"
79 #include "ihevc_common_tables.h"
80
81 #include "ihevce_defs.h"
82 #include "ihevce_hle_interface.h"
83 #include "ihevce_lap_enc_structs.h"
84 #include "ihevce_lap_interface.h"
85 #include "ihevce_multi_thrd_structs.h"
86 #include "ihevce_multi_thrd_funcs.h"
87 #include "ihevce_me_common_defs.h"
88 #include "ihevce_had_satd.h"
89 #include "ihevce_error_codes.h"
90 #include "ihevce_bitstream.h"
91 #include "ihevce_cabac.h"
92 #include "ihevce_rdoq_macros.h"
93 #include "ihevce_function_selector.h"
94 #include "ihevce_enc_structs.h"
95 #include "ihevce_entropy_structs.h"
96 #include "ihevce_cmn_utils_instr_set_router.h"
97 #include "ihevce_ipe_instr_set_router.h"
98 #include "ihevce_decomp_pre_intra_structs.h"
99 #include "ihevce_decomp_pre_intra_pass.h"
100 #include "ihevce_enc_loop_structs.h"
101 #include "ihevce_nbr_avail.h"
102 #include "ihevce_enc_loop_utils.h"
103 #include "ihevce_sub_pic_rc.h"
104 #include "ihevce_global_tables.h"
105 #include "ihevce_bs_compute_ctb.h"
106 #include "ihevce_cabac_rdo.h"
107 #include "ihevce_deblk.h"
108 #include "ihevce_entropy_interface.h"
109 #include "ihevce_frame_process.h"
110 #include "ihevce_ipe_pass.h"
111 #include "ihevce_rc_enc_structs.h"
112 #include "ihevce_rc_interface.h"
113 #include "hme_datatype.h"
114 #include "hme_interface.h"
115 #include "hme_common_defs.h"
116 #include "hme_defs.h"
117 #include "ihevce_me_instr_set_router.h"
118 #include "ihevce_enc_subpel_gen.h"
119 #include "ihevce_inter_pred.h"
120 #include "ihevce_mv_pred.h"
121 #include "ihevce_mv_pred_merge.h"
122 #include "ihevce_enc_loop_inter_mode_sifter.h"
123 #include "ihevce_me_pass.h"
124 #include "ihevce_coarse_me_pass.h"
125 #include "ihevce_enc_cu_recursion.h"
126 #include "ihevce_enc_loop_pass.h"
127 #include "ihevce_common_utils.h"
128 #include "ihevce_buffer_que_interface.h"
129 #include "ihevce_dep_mngr_interface.h"
130 #include "ihevce_sao.h"
131 #include "ihevce_tile_interface.h"
132
133 #include "cast_types.h"
134 #include "osal.h"
135 #include "osal_defaults.h"
136
137 /*****************************************************************************/
138 /* Function Definitions */
139 /*****************************************************************************/
140
141 /*!
142 ******************************************************************************
143 * \if Function name : ihevce_mem_manager_init \endif
144 *
145 * \brief
146 * Encoder Memory init function
147 *
148 * \param[in] Processing interface context pointer
149 *
150 * \return
151 * None
152 *
153 * \author
154 * Ittiam
155 *
156 *****************************************************************************
157 */
158 #define MAX_QUEUE 40
ihevce_mem_manager_init(enc_ctxt_t * ps_enc_ctxt,ihevce_hle_ctxt_t * ps_intrf_ctxt)159 void ihevce_mem_manager_init(enc_ctxt_t *ps_enc_ctxt, ihevce_hle_ctxt_t *ps_intrf_ctxt)
160 {
161 /* local variables */
162 WORD32 total_memtabs_req = 0;
163 WORD32 total_memtabs_used = 0;
164 WORD32 total_system_memtabs = 0;
165 WORD32 ctr;
166 WORD32 buf_size;
167 WORD32 num_ctb_horz;
168 WORD32 num_ctb_vert;
169 WORD32 num_cu_in_ctb;
170 WORD32 num_pu_in_ctb;
171 WORD32 num_tu_in_ctb;
172 WORD32 ctb_size;
173 WORD32 min_cu_size;
174 WORD32 max_num_ref_pics;
175 WORD32 mem_alloc_ctrl_flag;
176 WORD32 space_for_mem_in_enc_grp = 0;
177 WORD32 space_for_mem_in_pre_enc_grp = 0;
178 WORD32 mv_bank_size;
179 WORD32 ref_idx_bank_size;
180 WORD32 a_wd[MAX_NUM_HME_LAYERS], a_ht[MAX_NUM_HME_LAYERS];
181 WORD32 a_disp_wd[MAX_NUM_HME_LAYERS], a_disp_ht[MAX_NUM_HME_LAYERS];
182 WORD32 a_ctb_align_wd[MAX_NUM_HME_LAYERS], a_ctb_align_ht[MAX_NUM_HME_LAYERS];
183 WORD32 n_enc_layers = 1, n_tot_layers;
184 WORD32 num_bufs_preenc_me_que, num_bufs_L0_ipe_enc;
185 WORD32 i, i4_resolution_id = ps_enc_ctxt->i4_resolution_id; //counter
186 WORD32 i4_num_bitrate_inst;
187 iv_mem_rec_t *ps_memtab;
188 WORD32 i4_field_pic, i4_total_queues = 0;
189
190 recon_pic_buf_t **pps_pre_enc_pic_bufs;
191 frm_proc_ent_cod_ctxt_t **pps_frm_proc_ent_cod_bufs[IHEVCE_MAX_NUM_BITRATES];
192 pre_enc_me_ctxt_t **pps_pre_enc_bufs;
193 me_enc_rdopt_ctxt_t **pps_me_enc_bufs;
194 pre_enc_L0_ipe_encloop_ctxt_t **pps_L0_ipe_enc_bufs;
195 /*get number of input buffer required based on requirement from each stage*/
196 ihevce_lap_enc_buf_t **pps_lap_enc_input_bufs;
197 WORD32 i4_num_enc_loop_frm_pllel;
198 WORD32 i4_num_me_frm_pllel;
199 /*msr: These are parameters required to allocate input buffer,
200 encoder needs to be initilized before getting requirements hence filled once static params are initilized*/
201 WORD32 num_input_buf_per_queue, i4_yuv_min_size, i4_luma_min_size;
202
203 i4_num_bitrate_inst = ps_enc_ctxt->i4_num_bitrates;
204 i4_field_pic = ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_field_pic;
205 ps_intrf_ctxt->i4_gpu_mem_size = 0;
206
207 /*Initialize the thrd id flag and all deafult values for sub pic rc */
208 {
209 WORD32 i, j, k;
210
211 for(i = 0; i < MAX_NUM_ENC_LOOP_PARALLEL; i++)
212 {
213 for(j = 0; j < IHEVCE_MAX_NUM_BITRATES; j++)
214 {
215 ps_enc_ctxt->s_multi_thrd.ai4_acc_ctb_ctr[i][j] = 0;
216 ps_enc_ctxt->s_multi_thrd.ai4_ctb_ctr[i][j] = 0;
217
218 ps_enc_ctxt->s_multi_thrd.ai4_threshold_reached[i][j] = 0;
219
220 ps_enc_ctxt->s_multi_thrd.ai4_curr_qp_acc[i][j] = 0;
221
222 ps_enc_ctxt->s_multi_thrd.af_acc_hdr_bits_scale_err[i][j] = 0;
223
224 for(k = 0; k < MAX_NUM_FRM_PROC_THRDS_ENC; k++)
225 {
226 ps_enc_ctxt->s_multi_thrd.ai4_thrd_id_valid_flag[i][j][k] = -1;
227 }
228 }
229 }
230 }
231
232 #define ENABLE_FRM_PARALLEL
233 #ifdef ENABLE_FRM_PARALLEL
234 i4_num_enc_loop_frm_pllel = MAX_NUM_ENC_LOOP_PARALLEL;
235 i4_num_me_frm_pllel = MAX_NUM_ME_PARALLEL;
236 #else
237 i4_num_enc_loop_frm_pllel = 1;
238 i4_num_me_frm_pllel = 1;
239 #endif
240
241 ps_enc_ctxt->s_multi_thrd.i4_num_enc_loop_frm_pllel = i4_num_enc_loop_frm_pllel;
242 ps_enc_ctxt->i4_max_fr_enc_loop_parallel_rc = i4_num_enc_loop_frm_pllel;
243 ps_enc_ctxt->s_multi_thrd.i4_num_me_frm_pllel = i4_num_me_frm_pllel;
244 ps_enc_ctxt->s_multi_thrd.i4_force_end_flag = 0;
245
246 ps_enc_ctxt->i4_ref_mbr_id = 0;
247 /* get the ctb size from max cu size */
248 ctb_size = ps_enc_ctxt->ps_stat_prms->s_config_prms.i4_max_log2_cu_size;
249
250 /* get the min cu size from config params */
251 min_cu_size = ps_enc_ctxt->ps_stat_prms->s_config_prms.i4_min_log2_cu_size;
252
253 /* convert to actual width */
254 ctb_size = 1 << ctb_size;
255 min_cu_size = 1 << min_cu_size;
256
257 /* Get the width and heights of different decomp layers */
258 *a_wd =
259 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ps_enc_ctxt->i4_resolution_id]
260 .i4_width +
261 SET_CTB_ALIGN(
262 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ps_enc_ctxt->i4_resolution_id]
263 .i4_width,
264 min_cu_size);
265 *a_ht =
266 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ps_enc_ctxt->i4_resolution_id]
267 .i4_height +
268 SET_CTB_ALIGN(
269 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ps_enc_ctxt->i4_resolution_id]
270 .i4_height,
271 min_cu_size);
272
273 n_tot_layers = hme_derive_num_layers(n_enc_layers, a_wd, a_ht, a_disp_wd, a_disp_ht);
274 hme_coarse_get_layer1_mv_bank_ref_idx_size(
275 n_tot_layers,
276 a_wd,
277 a_ht,
278 ((ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_reference_frames == -1)
279 ? ((DEFAULT_MAX_REFERENCE_PICS) << i4_field_pic)
280 : ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_reference_frames),
281 (S32 *)(&mv_bank_size),
282 (S32 *)(&ref_idx_bank_size));
283 if(n_tot_layers < 3)
284 {
285 WORD32 error_code;
286 error_code = IHEVCE_NUM_DECOMP_LYRS_NOT_SUPPORTED;
287 ps_intrf_ctxt->i4_error_code = IHEVCE_SETUNSUPPORTEDINPUT(error_code);
288 return;
289 }
290
291 /* calculate num cu,pu,tu in ctb */
292 num_cu_in_ctb = ctb_size / MIN_CU_SIZE;
293 num_cu_in_ctb *= num_cu_in_ctb;
294
295 num_pu_in_ctb = ctb_size / MIN_PU_SIZE;
296 num_pu_in_ctb *= num_pu_in_ctb;
297
298 num_tu_in_ctb = ctb_size / MIN_PU_SIZE;
299 num_tu_in_ctb *= num_tu_in_ctb;
300
301 /* calcuate the number of ctb horizontally*/
302 num_ctb_horz =
303 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ps_enc_ctxt->i4_resolution_id]
304 .i4_width +
305 SET_CTB_ALIGN(
306 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ps_enc_ctxt->i4_resolution_id]
307 .i4_width,
308 ctb_size);
309 num_ctb_horz = num_ctb_horz / ctb_size;
310
311 /* calcuate the number of ctb vertically*/
312 num_ctb_vert =
313 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ps_enc_ctxt->i4_resolution_id]
314 .i4_height +
315 SET_CTB_ALIGN(
316 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ps_enc_ctxt->i4_resolution_id]
317 .i4_height,
318 ctb_size);
319 num_ctb_vert = num_ctb_vert / ctb_size;
320
321 /* align all the decomp layer dimensions to CTB alignment */
322 for(ctr = 0; ctr < n_tot_layers; ctr++)
323 {
324 a_ctb_align_wd[ctr] = a_wd[ctr] + SET_CTB_ALIGN(a_wd[ctr], ctb_size);
325
326 a_ctb_align_ht[ctr] = a_ht[ctr] + SET_CTB_ALIGN(a_ht[ctr], ctb_size);
327 }
328
329 /* SEI related parametert initialization */
330
331 ps_enc_ctxt->u4_cur_pic_encode_cnt = 0;
332
333 /* store the frame level ctb parameters which will be constant for the session */
334 ps_enc_ctxt->s_frm_ctb_prms.i4_ctb_size = ctb_size;
335 ps_enc_ctxt->s_frm_ctb_prms.i4_min_cu_size = min_cu_size;
336 ps_enc_ctxt->s_frm_ctb_prms.i4_num_cus_in_ctb = num_cu_in_ctb;
337 ps_enc_ctxt->s_frm_ctb_prms.i4_num_pus_in_ctb = num_pu_in_ctb;
338 ps_enc_ctxt->s_frm_ctb_prms.i4_num_tus_in_ctb = num_tu_in_ctb;
339
340 /* intialize cra poc to default value */
341 ps_enc_ctxt->i4_cra_poc = 0;
342
343 /* initialise the memory alloc control flag */
344 mem_alloc_ctrl_flag = ps_enc_ctxt->ps_stat_prms->s_multi_thrd_prms.i4_memory_alloc_ctrl_flag;
345
346 /* decide the memory space for enc_grp and pre_enc_grp based on control flag */
347 if(0 == mem_alloc_ctrl_flag)
348 {
349 /* normal memory */
350 space_for_mem_in_enc_grp = IV_EXT_CACHEABLE_NORMAL_MEM;
351 space_for_mem_in_pre_enc_grp = IV_EXT_CACHEABLE_NORMAL_MEM;
352 }
353 else if(1 == mem_alloc_ctrl_flag)
354 {
355 /* only NUMA Node 0 memory allocation */
356 space_for_mem_in_enc_grp = IV_EXT_CACHEABLE_NUMA_NODE0_MEM;
357 space_for_mem_in_pre_enc_grp = IV_EXT_CACHEABLE_NUMA_NODE0_MEM;
358 }
359 else if(2 == mem_alloc_ctrl_flag)
360 {
361 /* Both NUMA Node 0 & Node 1 memory allocation */
362 space_for_mem_in_enc_grp = IV_EXT_CACHEABLE_NUMA_NODE0_MEM;
363 space_for_mem_in_pre_enc_grp = IV_EXT_CACHEABLE_NUMA_NODE1_MEM;
364 }
365 else
366 {
367 /* should not enter here */
368 ASSERT(0);
369 }
370
371 {
372 if(ps_enc_ctxt->s_multi_thrd.i4_num_enc_loop_frm_pllel > 1)
373 {
374 num_bufs_preenc_me_que = MIN_L1_L0_STAGGER_NON_SEQ +
375 ps_enc_ctxt->ps_stat_prms->s_lap_prms.i4_rc_look_ahead_pics +
376 (MAX_L0_IPE_ENC_STAGGER - 1) + NUM_BUFS_DECOMP_HME;
377 }
378 else
379 {
380 num_bufs_preenc_me_que = MIN_L1_L0_STAGGER_NON_SEQ +
381 ps_enc_ctxt->ps_stat_prms->s_lap_prms.i4_rc_look_ahead_pics +
382 (MIN_L0_IPE_ENC_STAGGER - 1) + NUM_BUFS_DECOMP_HME;
383 }
384
385 /*The number of buffers to support stagger between L0 IPE, ME and enc loop. This is a separate queue to store L0 IPE
386 output to save memory since this is not used in L1 stage*/
387 if(ps_enc_ctxt->s_multi_thrd.i4_num_enc_loop_frm_pllel > 1)
388 {
389 num_bufs_L0_ipe_enc = MAX_L0_IPE_ENC_STAGGER;
390 }
391 else
392 {
393 num_bufs_L0_ipe_enc = MIN_L0_IPE_ENC_STAGGER;
394 }
395 }
396
397 /* ------------ popluate the lap static parameters ------------- */
398 ps_enc_ctxt->s_lap_stat_prms.i4_max_closed_gop_period =
399 ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_closed_gop_period;
400
401 ps_enc_ctxt->s_lap_stat_prms.i4_min_closed_gop_period =
402 ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_min_closed_gop_period;
403
404 ps_enc_ctxt->s_lap_stat_prms.i4_max_cra_open_gop_period =
405 ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_cra_open_gop_period;
406
407 ps_enc_ctxt->s_lap_stat_prms.i4_max_i_open_gop_period =
408 ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_i_open_gop_period;
409
410 ps_enc_ctxt->s_lap_stat_prms.i4_max_reference_frames =
411 ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_reference_frames;
412
413 ps_enc_ctxt->s_lap_stat_prms.i4_max_temporal_layers =
414 ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_temporal_layers;
415
416 ps_enc_ctxt->s_lap_stat_prms.i4_width = ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_width;
417
418 ps_enc_ctxt->s_lap_stat_prms.i4_height = ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_height;
419
420 ps_enc_ctxt->s_lap_stat_prms.i4_enable_logo = ps_enc_ctxt->ps_stat_prms->i4_enable_logo;
421
422 ps_enc_ctxt->s_lap_stat_prms.i4_src_interlace_field =
423 ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_field_pic;
424 ps_enc_ctxt->s_lap_stat_prms.i4_frame_rate =
425 ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_frm_rate_num /
426 ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_frm_rate_denom;
427
428 ps_enc_ctxt->s_lap_stat_prms.i4_blu_ray_spec = ps_enc_ctxt->i4_blu_ray_spec;
429
430 ps_enc_ctxt->s_lap_stat_prms.i4_internal_bit_depth =
431 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.i4_internal_bit_depth;
432
433 ps_enc_ctxt->s_lap_stat_prms.i4_input_bit_depth =
434 ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_input_bit_depth;
435
436 ps_enc_ctxt->s_lap_stat_prms.u1_chroma_array_type =
437 (ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_chr_format == IV_YUV_422SP_UV) ? 2 : 1;
438
439 ps_enc_ctxt->s_lap_stat_prms.i4_rc_pass_num = ps_enc_ctxt->ps_stat_prms->s_pass_prms.i4_pass;
440
441 if(0 == i4_resolution_id)
442 {
443 for(ctr = 0; ctr < ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.i4_num_res_layers; ctr++)
444 {
445 ps_enc_ctxt->s_lap_stat_prms.ai4_quality_preset[ctr] =
446 ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[ctr].i4_quality_preset;
447
448 if(ps_enc_ctxt->s_lap_stat_prms.ai4_quality_preset[ctr] == IHEVCE_QUALITY_P7)
449 {
450 ps_enc_ctxt->s_lap_stat_prms.ai4_quality_preset[ctr] = IHEVCE_QUALITY_P6;
451 }
452 }
453 }
454 memcpy(
455 &ps_enc_ctxt->s_lap_stat_prms.s_lap_params,
456 &ps_enc_ctxt->ps_stat_prms->s_lap_prms,
457 sizeof(ihevce_lap_params_t));
458
459 /* copy the create prms as runtime prms */
460 memcpy(
461 &ps_enc_ctxt->s_runtime_src_prms,
462 &ps_enc_ctxt->ps_stat_prms->s_src_prms,
463 sizeof(ihevce_src_params_t));
464 /*Copy the target params*/
465 memcpy(
466 &ps_enc_ctxt->s_runtime_tgt_params,
467 &ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id],
468 sizeof(ihevce_tgt_params_t));
469 ps_enc_ctxt->s_lap_stat_prms.e_arch_type = ps_enc_ctxt->ps_stat_prms->e_arch_type;
470 ps_enc_ctxt->s_lap_stat_prms.u1_is_popcnt_available = ps_enc_ctxt->u1_is_popcnt_available;
471
472 /* copy the create prms as runtime prms */
473 memcpy(
474 &ps_enc_ctxt->s_runtime_src_prms,
475 &ps_enc_ctxt->ps_stat_prms->s_src_prms,
476 sizeof(ihevce_src_params_t));
477 /*Copy the target params*/
478 memcpy(
479 &ps_enc_ctxt->s_runtime_tgt_params,
480 &ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id],
481 sizeof(ihevce_tgt_params_t));
482
483 /* copy the run time coding parameters */
484 memcpy(
485 &ps_enc_ctxt->s_runtime_coding_prms,
486 &ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms,
487 sizeof(ihevce_coding_params_t));
488 /*change in run time parameter*/
489 if(ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_reference_frames == -1)
490 {
491 ps_enc_ctxt->s_runtime_coding_prms.i4_max_reference_frames = (DEFAULT_MAX_REFERENCE_PICS)
492 << i4_field_pic;
493 ps_enc_ctxt->s_lap_stat_prms.i4_max_reference_frames =
494 ps_enc_ctxt->s_runtime_coding_prms.i4_max_reference_frames;
495 }
496 ASSERT(i4_num_enc_loop_frm_pllel == i4_num_me_frm_pllel);
497
498 if((1 == i4_num_enc_loop_frm_pllel) && (1 == i4_num_me_frm_pllel))
499 {
500 max_num_ref_pics = ps_enc_ctxt->s_runtime_coding_prms.i4_max_reference_frames;
501 }
502 else
503 {
504 max_num_ref_pics =
505 ps_enc_ctxt->s_runtime_coding_prms.i4_max_reference_frames * i4_num_enc_loop_frm_pllel;
506 }
507 /* --------------------------------------------------------------------- */
508 /* -------------- Collating the number of memtabs required ------------ */
509 /* --------------------------------------------------------------------- */
510
511 /* Memtabs for syntactical tiles */
512 total_memtabs_req += ihevce_tiles_get_num_mem_recs();
513
514 /* ---------- Enc loop Memtabs --------- */
515 total_memtabs_req +=
516 ihevce_enc_loop_get_num_mem_recs(i4_num_bitrate_inst, i4_num_enc_loop_frm_pllel);
517 /* ---------- ME Memtabs --------------- */
518 total_memtabs_req += ihevce_me_get_num_mem_recs(i4_num_me_frm_pllel);
519
520 /* ---------- Coarse ME Memtabs --------------- */
521 total_memtabs_req += ihevce_coarse_me_get_num_mem_recs();
522 /* ---------- IPE Memtabs -------------- */
523 total_memtabs_req += ihevce_ipe_get_num_mem_recs();
524
525 /* ---------- ECD Memtabs -------------- */
526 for(i = 0; i < i4_num_bitrate_inst; i++)
527 {
528 total_memtabs_req += ihevce_entropy_get_num_mem_recs();
529 }
530 if(0 == ps_enc_ctxt->i4_resolution_id)
531 {
532 /* ---------- LAP Memtabs--------------- */
533 total_memtabs_req += ihevce_lap_get_num_mem_recs();
534 }
535 /* ---------- Decomp Pre Intra Memtabs--------------- */
536 total_memtabs_req += ihevce_decomp_pre_intra_get_num_mem_recs();
537
538 /* ---------- RC memtabs --------------- */
539 for(i = 0; i < i4_num_bitrate_inst; i++)
540 {
541 total_memtabs_req += ihevce_rc_get_num_mem_recs(); /*HEVC_RC*/
542 }
543
544 /* ---------- System Memtabs ----------- */
545 total_memtabs_req += TOTAL_SYSTEM_MEM_RECS; //increment this based on final requirement
546
547 /* -----Frameproc Entcod Que Memtabs --- */
548 /* one queue for each bit-rate is used */
549 for(i = 0; i < i4_num_bitrate_inst; i++)
550 {
551 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
552 }
553 /* mrs:memtab for one queue for encoder owned input queue, This is only request for memtab, currently more than
554 required memtabs are allocated. Hence my change of using memtab for yuv buffers is surviving. Only memtab
555 usage and initialization needs to be exact sync*/
556 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
557
558 /* ---Pre-encode Encode Que Mem requests -- */
559 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
560
561 /* -----ME / Enc-RD opt Que Mem requests --- */
562 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
563
564 /* ----Pre-encode L0 IPE to enc Que Mem requests -- */
565 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
566
567 /* --- ME-EncLoop Dep Mngr Row-Row Mem requests -- */
568 total_memtabs_req += NUM_ME_ENC_BUFS * ihevce_dmgr_get_num_mem_recs();
569
570 /* --- Prev. frame EncLoop Done Dep Mngr Frm-Frm Mem requests -- */
571 total_memtabs_req += i4_num_enc_loop_frm_pllel * ihevce_dmgr_get_num_mem_recs();
572
573 /* --- Prev. frame EncLoop Done for re-encode Dep Mngr Frm-Frm Mem requests -- */
574 total_memtabs_req += ihevce_dmgr_get_num_mem_recs();
575
576 /* --- Prev. frame ME Done Dep Mngr Frm-Frm Mem requests -- */
577 total_memtabs_req += i4_num_me_frm_pllel * ihevce_dmgr_get_num_mem_recs();
578
579 /* --- Prev. frame PreEnc L1 Done Dep Mngr Frm-Frm Mem requests -- */
580 total_memtabs_req += ihevce_dmgr_get_num_mem_recs();
581
582 /* --- Prev. frame PreEnc HME Done Dep Mngr Frm-Frm Mem requests -- */
583 total_memtabs_req += ihevce_dmgr_get_num_mem_recs();
584
585 /* --- Prev. frame PreEnc L0 Done Dep Mngr Frm-Frm Mem requests -- */
586 total_memtabs_req += ihevce_dmgr_get_num_mem_recs();
587
588 /* --- ME-Prev Recon Dep Mngr Row-Frm Mem requests -- */
589 total_memtabs_req +=
590 (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS) * ihevce_dmgr_get_num_mem_recs();
591
592 /* ----- allocate memomry for memtabs --- */
593 {
594 iv_mem_rec_t s_memtab;
595
596 s_memtab.i4_size = sizeof(iv_mem_rec_t);
597 s_memtab.i4_mem_size = total_memtabs_req * sizeof(iv_mem_rec_t);
598 s_memtab.e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
599 s_memtab.i4_mem_alignment = 4;
600
601 ps_intrf_ctxt->ihevce_mem_alloc(
602 ps_intrf_ctxt->pv_mem_mgr_hdl, &ps_enc_ctxt->ps_stat_prms->s_sys_api, &s_memtab);
603 if(s_memtab.pv_base == NULL)
604 {
605 ps_intrf_ctxt->i4_error_code = IHEVCE_CANNOT_ALLOCATE_MEMORY;
606 return;
607 }
608
609 ps_memtab = (iv_mem_rec_t *)s_memtab.pv_base;
610 }
611
612 /* --------------------------------------------------------------------- */
613 /* ------------------ Collating memory requirements ------------------- */
614 /* --------------------------------------------------------------------- */
615
616 /* ----------- Tiles mem requests -------------*/
617 total_memtabs_used += ihevce_tiles_get_mem_recs(
618 &ps_memtab[total_memtabs_used],
619 ps_enc_ctxt->ps_stat_prms,
620 &ps_enc_ctxt->s_frm_ctb_prms,
621 i4_resolution_id,
622 space_for_mem_in_enc_grp);
623
624 /* ---------- Enc loop Mem requests --------- */
625 total_memtabs_used += ihevce_enc_loop_get_mem_recs(
626 &ps_memtab[total_memtabs_used],
627 ps_enc_ctxt->ps_stat_prms,
628 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
629 i4_num_bitrate_inst,
630 i4_num_enc_loop_frm_pllel,
631 space_for_mem_in_enc_grp,
632 i4_resolution_id);
633 /* ---------- ME Mem requests --------------- */
634 total_memtabs_used += ihevce_me_get_mem_recs(
635 &ps_memtab[total_memtabs_used],
636 ps_enc_ctxt->ps_stat_prms,
637 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
638 space_for_mem_in_enc_grp,
639 i4_resolution_id,
640 i4_num_me_frm_pllel);
641
642 /* ---------- Coarse ME Mem requests --------------- */
643 total_memtabs_used += ihevce_coarse_me_get_mem_recs(
644 &ps_memtab[total_memtabs_used],
645 ps_enc_ctxt->ps_stat_prms,
646 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
647 space_for_mem_in_pre_enc_grp,
648 i4_resolution_id);
649 /* ---------- IPE Mem requests -------------- */
650 total_memtabs_used += ihevce_ipe_get_mem_recs(
651 &ps_memtab[total_memtabs_used],
652 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
653 space_for_mem_in_pre_enc_grp);
654 /* ---------- ECD Mem requests -------------- */
655 i4_num_bitrate_inst = ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id]
656 .i4_num_bitrate_instances;
657 for(i = 0; i < i4_num_bitrate_inst; i++)
658 {
659 total_memtabs_used += ihevce_entropy_get_mem_recs(
660 &ps_memtab[total_memtabs_used],
661 ps_enc_ctxt->ps_stat_prms,
662 space_for_mem_in_pre_enc_grp,
663 i4_resolution_id);
664 }
665
666 if(0 == i4_resolution_id)
667 {
668 /* ---------- LAP Mem requests--------------- */
669 total_memtabs_used +=
670 ihevce_lap_get_mem_recs(&ps_memtab[total_memtabs_used], space_for_mem_in_pre_enc_grp);
671 }
672
673 /* -------- DECOMPOSITION PRE INTRA Mem requests-------- */
674 total_memtabs_used += ihevce_decomp_pre_intra_get_mem_recs(
675 &ps_memtab[total_memtabs_used],
676 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
677 space_for_mem_in_pre_enc_grp);
678
679 /* ---------- RC Mem requests --------------- */
680 for(i = 0; i < i4_num_bitrate_inst; i++)
681 {
682 total_memtabs_used += ihevce_rc_get_mem_recs(
683 &ps_memtab[total_memtabs_used],
684 ps_enc_ctxt->ps_stat_prms,
685 space_for_mem_in_pre_enc_grp,
686 &ps_enc_ctxt->ps_stat_prms->s_sys_api);
687 }
688
689 /* ---------- System Mem requests ----------- */
690
691 /* allocate memory for pps tile */
692 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
693
694 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
695
696 if(1 == ps_enc_ctxt->ps_stat_prms->s_app_tile_params.i4_tiles_enabled_flag)
697 {
698 ps_memtab[total_memtabs_used].i4_mem_size =
699 (ps_enc_ctxt->ps_stat_prms->s_app_tile_params.i4_num_tile_cols *
700 ps_enc_ctxt->ps_stat_prms->s_app_tile_params.i4_num_tile_rows) *
701 (sizeof(tile_t));
702 }
703 else
704 {
705 ps_memtab[total_memtabs_used].i4_mem_size = sizeof(tile_t);
706 }
707
708 /* increment the memtab counter */
709 total_memtabs_used++;
710 total_system_memtabs++;
711
712 /* recon picture buffer pointer array */
713 for(i = 0; i < i4_num_bitrate_inst; i++)
714 {
715 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
716
717 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
718
719 ps_memtab[total_memtabs_used].i4_mem_size =
720 (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS) * (sizeof(recon_pic_buf_t *));
721
722 /* increment the memtab counter */
723 total_memtabs_used++;
724 total_system_memtabs++;
725 }
726
727 /* recon picture buffers structures */
728 for(i = 0; i < i4_num_bitrate_inst; i++)
729 {
730 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
731
732 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
733
734 ps_memtab[total_memtabs_used].i4_mem_size =
735 (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS) * (sizeof(recon_pic_buf_t));
736
737 /* increment the memtab counter */
738 total_memtabs_used++;
739 total_system_memtabs++;
740 }
741
742 /* reference/recon picture buffers */
743 for(i = 0; i < i4_num_bitrate_inst; i++)
744 {
745 WORD32 i4_chroma_buf_size_shift =
746 -(ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.i4_internal_bit_depth <= 8) +
747 (ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_chr_format == IV_YUV_422SP_UV);
748
749 buf_size = ((num_ctb_horz * ctb_size) + (PAD_HORZ << 1));
750 buf_size = buf_size * ((num_ctb_vert * ctb_size) + (PAD_VERT << 1));
751 buf_size = buf_size * (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS);
752
753 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
754
755 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
756
757 /* If HBD, both 8bit and 16 bit luma buffers are required, whereas only 16bit chroma buffers are required */
758 ps_memtab[total_memtabs_used].i4_mem_size =
759 /* Luma */
760 (buf_size * ((ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.i4_internal_bit_depth > 8)
761 ? BUFFER_SIZE_MULTIPLIER_IF_HBD
762 : 1)) +
763 /* Chroma */
764 (SHL_NEG(buf_size, i4_chroma_buf_size_shift));
765
766 /* increment the memtab counter */
767 total_memtabs_used++;
768 total_system_memtabs++;
769 }
770 /* reference/recon picture subpel planes */
771 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
772
773 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
774
775 ps_memtab[total_memtabs_used].i4_mem_size =
776 buf_size * (3 + L0ME_IN_OPENLOOP_MODE); /* 3 planes */
777
778 /* increment the memtab counter */
779 total_memtabs_used++;
780 total_system_memtabs++;
781 /* reference colocated MV bank */
782 /* Keep memory for an extra CTB at the right and bottom of frame.
783 This extra space is needed by dist-encoding and unused in non-dist-encoding */
784 buf_size = (num_ctb_horz + 1) * (num_ctb_vert + 1) * num_pu_in_ctb;
785 buf_size = buf_size * sizeof(pu_col_mv_t) * (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS) *
786 i4_num_bitrate_inst;
787
788 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
789
790 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
791
792 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
793
794 /* increment the memtab counter */
795 total_memtabs_used++;
796 total_system_memtabs++;
797
798 /* reference colocated MV bank map */
799 /* Keep memory for an extra CTB at the right and bottom of frame.
800 This extra space is needed by dist-encoding and unused in non-dist-encoding */
801 buf_size = (num_ctb_horz + 1) * (num_ctb_vert + 1) * num_pu_in_ctb;
802 buf_size = buf_size * sizeof(UWORD8) * (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS) *
803 i4_num_bitrate_inst;
804
805 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
806
807 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
808
809 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
810
811 /* increment the memtab counter */
812 total_memtabs_used++;
813 total_system_memtabs++;
814
815 /* reference collocated MV bank map offsets map */
816 buf_size = num_ctb_horz * num_ctb_vert;
817 buf_size = buf_size * sizeof(UWORD16) * (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS) *
818 i4_num_bitrate_inst;
819
820 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
821
822 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
823
824 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
825
826 /* increment the memtab counter */
827 total_memtabs_used++;
828 total_system_memtabs++;
829
830 /* reference colocated MV bank ctb offset */
831 buf_size = num_ctb_horz;
832 buf_size = buf_size * num_ctb_vert;
833 buf_size = buf_size * sizeof(UWORD32) * (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS) *
834 i4_num_bitrate_inst;
835
836 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
837
838 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
839
840 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
841
842 /* increment the memtab counter */
843 total_memtabs_used++;
844 total_system_memtabs++;
845
846 /* recon picture buffer pointer array for pre enc group */
847 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
848
849 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
850
851 ps_memtab[total_memtabs_used].i4_mem_size =
852 (max_num_ref_pics + 1) * (sizeof(recon_pic_buf_t *));
853
854 /* increment the memtab counter */
855 total_memtabs_used++;
856 total_system_memtabs++;
857
858 /* recon picture buffers structures for pre enc group */
859 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
860
861 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
862
863 ps_memtab[total_memtabs_used].i4_mem_size = (max_num_ref_pics + 1) * (sizeof(recon_pic_buf_t));
864
865 /* increment the memtab counter */
866 total_memtabs_used++;
867 total_system_memtabs++;
868 {
869 num_input_buf_per_queue = ihevce_lap_get_num_ip_bufs(&ps_enc_ctxt->s_lap_stat_prms);
870 {
871 WORD32 i4_count_temp = 0, i4_last_queue_length;
872
873 /*First allocate the memory for the buffer based on resolution*/
874 WORD32 ctb_align_pic_wd = ps_enc_ctxt->s_runtime_tgt_params.i4_width +
875 SET_CTB_ALIGN(
876 ps_enc_ctxt->s_runtime_tgt_params.i4_width,
877 ps_enc_ctxt->s_frm_ctb_prms.i4_ctb_size);
878
879 WORD32 ctb_align_pic_ht = ps_enc_ctxt->s_runtime_tgt_params.i4_height +
880 SET_CTB_ALIGN(
881 ps_enc_ctxt->s_runtime_tgt_params.i4_height,
882 ps_enc_ctxt->s_frm_ctb_prms.i4_ctb_size);
883
884 i4_last_queue_length = (num_input_buf_per_queue % MAX_QUEUE);
885
886 if((num_input_buf_per_queue % MAX_QUEUE) == 0)
887 i4_last_queue_length = MAX_QUEUE;
888
889 ps_enc_ctxt->i4_num_input_buf_per_queue = num_input_buf_per_queue;
890 i4_yuv_min_size =
891 (ctb_align_pic_wd * ctb_align_pic_ht) +
892 ((ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_chr_format == IV_YUV_422SP_UV)
893 ? (ctb_align_pic_wd * ctb_align_pic_ht)
894 : ((ctb_align_pic_wd * ctb_align_pic_ht) >> 1));
895 i4_luma_min_size = (ctb_align_pic_wd * ctb_align_pic_ht);
896
897 /*Inorder to allocate memory for the large buffer sizes overflowing WORD32 we are splitting the memtabs using i4_total_hbd_queues and MAX_HBD_QUEUE*/
898 i4_total_queues = num_input_buf_per_queue / MAX_QUEUE;
899
900 if((num_input_buf_per_queue % MAX_QUEUE) != 0)
901 {
902 i4_total_queues++;
903 }
904
905 ASSERT(i4_total_queues < 5);
906
907 for(i4_count_temp = 0; i4_count_temp < i4_total_queues; i4_count_temp++)
908 {
909 ps_memtab[total_memtabs_used].i4_mem_alignment = 32;
910
911 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
912 /*Memory size for yuv buffer of one frame * num of input required to stored in the queue*/
913 if((i4_count_temp < (i4_total_queues - 1)))
914 ps_memtab[total_memtabs_used].i4_mem_size = i4_yuv_min_size * MAX_QUEUE;
915 else
916 ps_memtab[total_memtabs_used].i4_mem_size =
917 (i4_yuv_min_size)*i4_last_queue_length;
918
919 /* increment the memtab counter */
920 total_memtabs_used++;
921 total_system_memtabs++;
922 }
923 }
924 /*memory for input buffer structure*/
925 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
926
927 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
928
929 ps_memtab[total_memtabs_used].i4_mem_size =
930 (num_input_buf_per_queue) * (sizeof(ihevce_lap_enc_buf_t *));
931
932 /* increment the memtab counter */
933 total_memtabs_used++;
934 total_system_memtabs++;
935
936 /* frame process/entropy coding buffer structures */
937 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
938
939 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
940
941 ps_memtab[total_memtabs_used].i4_mem_size =
942 (num_input_buf_per_queue) * (sizeof(ihevce_lap_enc_buf_t));
943 /* increment the memtab counter */
944 total_memtabs_used++;
945 total_system_memtabs++;
946
947 /*input synch ctrl command*/
948 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
949
950 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
951
952 ps_memtab[total_memtabs_used].i4_mem_size =
953 (num_input_buf_per_queue) * (ENC_COMMAND_BUFF_SIZE);
954
955 total_memtabs_used++;
956 total_system_memtabs++;
957 }
958
959 /* Pre-encode/encode coding buffer pointer array */
960 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
961
962 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
963
964 ps_memtab[total_memtabs_used].i4_mem_size =
965 (num_bufs_preenc_me_que) * (sizeof(pre_enc_me_ctxt_t *));
966
967 /* increment the memtab counter */
968 total_memtabs_used++;
969 total_system_memtabs++;
970
971 /* frame process/entropy coding buffer structures */
972 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
973
974 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
975
976 ps_memtab[total_memtabs_used].i4_mem_size =
977 (num_bufs_preenc_me_que) * (sizeof(pre_enc_me_ctxt_t));
978
979 /* increment the memtab counter */
980 total_memtabs_used++;
981 total_system_memtabs++;
982
983 /* Pre-encode L0 IPE output to ME buffer pointer*/
984 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
985
986 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
987
988 ps_memtab[total_memtabs_used].i4_mem_size =
989 (num_bufs_L0_ipe_enc) * (sizeof(pre_enc_L0_ipe_encloop_ctxt_t *));
990
991 /* increment the memtab counter */
992 total_memtabs_used++;
993 total_system_memtabs++;
994
995 /* Pre-encode L0 IPE output to ME buffer */
996 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
997
998 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
999
1000 ps_memtab[total_memtabs_used].i4_mem_size =
1001 (num_bufs_L0_ipe_enc) * (sizeof(pre_enc_L0_ipe_encloop_ctxt_t));
1002
1003 /* increment the memtab counter */
1004 total_memtabs_used++;
1005 total_system_memtabs++;
1006
1007 /* CTB analyse Frame level */
1008 buf_size = num_ctb_horz;
1009 buf_size = buf_size * num_ctb_vert;
1010 buf_size = buf_size * sizeof(ctb_analyse_t) * num_bufs_preenc_me_que;
1011
1012 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1013
1014 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1015
1016 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1017
1018 /* increment the memtab counter */
1019 total_memtabs_used++;
1020 total_system_memtabs++;
1021
1022 /* ME layer ctxt pointer */
1023 buf_size = sizeof(layer_ctxt_t) * num_bufs_preenc_me_que;
1024
1025 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1026
1027 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1028
1029 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1030
1031 /* increment the memtab counter */
1032 total_memtabs_used++;
1033 total_system_memtabs++;
1034
1035 /* ME layer MV bank ctxt pointer */
1036 buf_size = sizeof(layer_mv_t) * num_bufs_preenc_me_que;
1037
1038 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1039
1040 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1041
1042 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1043
1044 /* increment the memtab counter */
1045 total_memtabs_used++;
1046 total_system_memtabs++;
1047
1048 /* ME layer MV bank pointer */
1049 buf_size = mv_bank_size * num_bufs_preenc_me_que;
1050
1051 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1052
1053 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1054
1055 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1056
1057 /* increment the memtab counter */
1058 total_memtabs_used++;
1059 total_system_memtabs++;
1060
1061 /* ME layer ref idx bank pointer */
1062 buf_size = ref_idx_bank_size * num_bufs_preenc_me_que;
1063
1064 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1065
1066 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1067
1068 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1069
1070 /* increment the memtab counter */
1071 total_memtabs_used++;
1072 total_system_memtabs++;
1073 /* Frame level array to store 8x8 intra cost */
1074 buf_size = (num_ctb_horz * ctb_size) >> 3;
1075 buf_size *= ((num_ctb_vert * ctb_size) >> 3);
1076 buf_size *= sizeof(double) * num_bufs_preenc_me_que;
1077
1078 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1079
1080 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1081
1082 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1083
1084 /* increment the memtab counter */
1085 total_memtabs_used++;
1086 total_system_memtabs++;
1087
1088 /* Frame level array to store ctb intra cost and modes */
1089 buf_size = (num_ctb_horz * num_ctb_vert);
1090 buf_size *= sizeof(ipe_l0_ctb_analyse_for_me_t) * num_bufs_L0_ipe_enc;
1091
1092 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1093
1094 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1095
1096 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1097
1098 /* increment the memtab counter */
1099 total_memtabs_used++;
1100 total_system_memtabs++;
1101 /*
1102 * L0 8x8 cur satd for qp mod
1103 */
1104 buf_size = (a_ctb_align_wd[0] >> 3) * (a_ctb_align_ht[0] >> 3) * sizeof(ihevce_8x8_L0_satd_t) *
1105 num_bufs_preenc_me_que;
1106
1107 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1108
1109 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_pre_enc_grp;
1110
1111 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1112
1113 /* increment the memtab counter */
1114 total_memtabs_used++;
1115 total_system_memtabs++;
1116
1117 /*
1118 * L0 8x8 cur mean for qp mod
1119 */
1120 buf_size = (a_ctb_align_wd[0] >> 3) * (a_ctb_align_ht[0] >> 3) * sizeof(ihevce_8x8_L0_mean_t) *
1121 num_bufs_preenc_me_que;
1122
1123 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1124
1125 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_pre_enc_grp;
1126
1127 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1128
1129 /* increment the memtab counter */
1130 total_memtabs_used++;
1131 total_system_memtabs++;
1132
1133 /*
1134 * Layer early decision buffer L1 buf.Since the pre intra analysis always
1135 * expects memory for ihevce_ed_blk_t for complete ctbs, align the width and
1136 * height in layer to mutiple of 32.
1137 */
1138 buf_size = (a_ctb_align_wd[1] >> 5) * (a_ctb_align_ht[1] >> 5) * sizeof(ihevce_ed_ctb_l1_t) *
1139 num_bufs_preenc_me_que;
1140
1141 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1142
1143 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_pre_enc_grp;
1144
1145 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1146
1147 /* increment the memtab counter */
1148 total_memtabs_used++;
1149 total_system_memtabs++;
1150
1151 /*
1152 * Layer early decision buffer L1 buf.Since the pre intra analysis always
1153 * expects memory for ihevce_ed_blk_t for complete ctbs, align the width and
1154 * height in layer to mutiple of 32.
1155 */
1156 buf_size = (a_ctb_align_wd[1] >> 2) * (a_ctb_align_ht[1] >> 2) * sizeof(ihevce_ed_blk_t) *
1157 num_bufs_preenc_me_que;
1158
1159 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1160
1161 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_pre_enc_grp;
1162
1163 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1164
1165 /* increment the memtab counter */
1166 total_memtabs_used++;
1167 total_system_memtabs++;
1168
1169 /*
1170 * Layer early decision buffer L2 buf.Since the pre intra analysis always
1171 * expects memory for ihevce_ed_blk_t for complete ctbs, align the width and
1172 * height in layer to mutiple of 16.
1173 */
1174 buf_size = (a_ctb_align_wd[2] >> 2) * (a_ctb_align_ht[2] >> 2) * sizeof(ihevce_ed_blk_t) *
1175 num_bufs_preenc_me_que;
1176
1177 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1178
1179 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_pre_enc_grp;
1180
1181 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1182
1183 /* increment the memtab counter */
1184 total_memtabs_used++;
1185 total_system_memtabs++;
1186
1187 /* following is the buffer requirement of
1188 que between me and enc*/
1189
1190 /* me/enc que buffer pointer array */
1191 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1192
1193 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1194
1195 ps_memtab[total_memtabs_used].i4_mem_size = (NUM_ME_ENC_BUFS) * (sizeof(me_enc_rdopt_ctxt_t *));
1196
1197 /* increment the memtab counter */
1198 total_memtabs_used++;
1199 total_system_memtabs++;
1200
1201 /* fme/enc que buffer structures */
1202 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1203
1204 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1205
1206 ps_memtab[total_memtabs_used].i4_mem_size = (NUM_ME_ENC_BUFS) * (sizeof(me_enc_rdopt_ctxt_t));
1207
1208 /* increment the memtab counter */
1209 total_memtabs_used++;
1210 total_system_memtabs++;
1211
1212 /* Job Queue related memory */
1213 /* max num ctb rows is doubled to take care worst case */
1214 /* requirements because of HME layers */
1215 buf_size = (MAX_NUM_VERT_UNITS_FRM) * (NUM_ENC_JOBS_QUES)*NUM_ME_ENC_BUFS; //PING_PONG_BUF;
1216 /* In tile case, based on the number of column tiles,
1217 we will have separate jobQ per column tile */
1218 if(1 == ps_enc_ctxt->ps_stat_prms->s_app_tile_params.i4_tiles_enabled_flag)
1219 {
1220 buf_size *= ps_enc_ctxt->ps_stat_prms->s_app_tile_params.i4_num_tile_cols;
1221 }
1222 buf_size *= sizeof(job_queue_t);
1223 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1224
1225 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1226
1227 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1228
1229 /* increment the memtab counter */
1230 total_memtabs_used++;
1231 total_system_memtabs++;
1232
1233 /* cur_ctb_cu_tree_t Frame level */
1234 buf_size = num_ctb_horz * MAX_NUM_NODES_CU_TREE;
1235 buf_size = buf_size * num_ctb_vert;
1236
1237 /* ps_cu_analyse_inter buffer is used to popualte outputs form ME after using cu analyse form IPE */
1238 buf_size = buf_size * sizeof(cur_ctb_cu_tree_t) * NUM_ME_ENC_BUFS;
1239
1240 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1241
1242 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1243
1244 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1245
1246 /* increment the memtab counter */
1247 total_memtabs_used++;
1248 total_system_memtabs++;
1249
1250 /* me_ctb_data_t Frame level */
1251 buf_size = num_ctb_horz * num_ctb_vert;
1252
1253 /* This buffer is used to */
1254 buf_size = buf_size * sizeof(me_ctb_data_t) * NUM_ME_ENC_BUFS;
1255
1256 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1257
1258 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1259
1260 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1261
1262 /* increment the memtab counter */
1263 total_memtabs_used++;
1264 total_system_memtabs++;
1265
1266 /* following is for each bit-rate */
1267 for(i = 0; i < i4_num_bitrate_inst; i++)
1268 {
1269 /* frame process/entropy coding buffer pointer array */
1270 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1271
1272 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1273
1274 ps_memtab[total_memtabs_used].i4_mem_size =
1275 (NUM_FRMPROC_ENTCOD_BUFS) * (sizeof(frm_proc_ent_cod_ctxt_t *));
1276
1277 /* increment the memtab counter */
1278 total_memtabs_used++;
1279 total_system_memtabs++;
1280
1281 /* frame process/entropy coding buffer structures */
1282 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1283
1284 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1285
1286 ps_memtab[total_memtabs_used].i4_mem_size =
1287 (NUM_FRMPROC_ENTCOD_BUFS) * (sizeof(frm_proc_ent_cod_ctxt_t));
1288
1289 /* increment the memtab counter */
1290 total_memtabs_used++;
1291 total_system_memtabs++;
1292
1293 /* CTB enc loop Frame level */
1294 buf_size = num_ctb_horz;
1295 buf_size = buf_size * num_ctb_vert;
1296 buf_size = buf_size * sizeof(ctb_enc_loop_out_t) * NUM_FRMPROC_ENTCOD_BUFS;
1297
1298 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1299
1300 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1301
1302 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1303
1304 /* increment the memtab counter */
1305 total_memtabs_used++;
1306 total_system_memtabs++;
1307
1308 /* CU enc loop Frame level */
1309 buf_size = num_ctb_horz * num_cu_in_ctb;
1310 buf_size = buf_size * num_ctb_vert;
1311 buf_size = buf_size * sizeof(cu_enc_loop_out_t) * NUM_FRMPROC_ENTCOD_BUFS;
1312
1313 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1314
1315 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1316
1317 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1318
1319 /* increment the memtab counter */
1320 total_memtabs_used++;
1321 total_system_memtabs++;
1322
1323 /* TU enc loop Frame level */
1324 buf_size = num_ctb_horz * num_tu_in_ctb;
1325 buf_size = buf_size * num_ctb_vert;
1326 buf_size = buf_size * sizeof(tu_enc_loop_out_t) * NUM_FRMPROC_ENTCOD_BUFS;
1327
1328 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1329
1330 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1331
1332 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1333
1334 /* increment the memtab counter */
1335 total_memtabs_used++;
1336 total_system_memtabs++;
1337
1338 /* PU enc loop Frame level */
1339 buf_size = num_ctb_horz * num_pu_in_ctb;
1340 buf_size = buf_size * num_ctb_vert;
1341 buf_size = buf_size * sizeof(pu_t) * NUM_FRMPROC_ENTCOD_BUFS;
1342
1343 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1344
1345 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1346
1347 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1348
1349 /* increment the memtab counter */
1350 total_memtabs_used++;
1351 total_system_memtabs++;
1352
1353 /* Coeffs Frame level */
1354 buf_size =
1355 num_ctb_horz * ((ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_chr_format == IV_YUV_422SP_UV)
1356 ? (num_tu_in_ctb << 1)
1357 : ((num_tu_in_ctb * 3) >> 1));
1358 buf_size = buf_size * num_ctb_vert;
1359 buf_size = buf_size * sizeof(UWORD8) * MAX_SCAN_COEFFS_BYTES_4x4 * NUM_FRMPROC_ENTCOD_BUFS;
1360
1361 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1362
1363 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1364
1365 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1366
1367 /* increment the memtab counter */
1368 total_memtabs_used++;
1369 total_system_memtabs++;
1370
1371 /* SEI Payload Data */
1372 buf_size = sizeof(UWORD8) * MAX_NUMBER_OF_SEI_PAYLOAD * MAX_SEI_PAYLOAD_PER_TLV *
1373 NUM_FRMPROC_ENTCOD_BUFS;
1374
1375 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1376 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1377
1378 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1379
1380 /* increment the memtab counter */
1381 total_memtabs_used++;
1382 total_system_memtabs++;
1383 }
1384
1385 /* ------ Working mem frame level -------*/
1386 buf_size = ((num_ctb_horz * ctb_size) + 16);
1387 buf_size *= ((num_ctb_vert * ctb_size) + 23);
1388 buf_size *= sizeof(WORD16);
1389 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1390
1391 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1392
1393 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1394
1395 /* increment the memtab counter */
1396 total_memtabs_used++;
1397 total_system_memtabs++;
1398 /* Job Queue related memory */
1399 /* max num ctb rows is doubled to take care worst case */
1400 /* requirements because of HME layers */
1401 buf_size = (MAX_NUM_VERT_UNITS_FRM) * (NUM_PRE_ENC_JOBS_QUES) *
1402 (MAX_PRE_ENC_STAGGER + NUM_BUFS_DECOMP_HME); //PING_PONG_BUF;
1403
1404 buf_size *= sizeof(job_queue_t);
1405 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
1406
1407 ps_memtab[total_memtabs_used].e_mem_type = (IV_MEM_TYPE_T)space_for_mem_in_enc_grp;
1408
1409 ps_memtab[total_memtabs_used].i4_mem_size = buf_size;
1410
1411 /* increment the memtab counter */
1412 total_memtabs_used++;
1413 total_system_memtabs++;
1414
1415 /* check on the system memtabs */
1416 ASSERT(total_system_memtabs <= TOTAL_SYSTEM_MEM_RECS);
1417
1418 /* -----Frameproc Entcod Que Mem requests --- */
1419 /* derive for each bit-rate */
1420 for(i = 0; i < i4_num_bitrate_inst; i++)
1421 {
1422 total_memtabs_used += ihevce_buff_que_get_mem_recs(
1423 &ps_memtab[total_memtabs_used], NUM_FRMPROC_ENTCOD_BUFS, space_for_mem_in_enc_grp);
1424 }
1425 /*mrs: Request memory for the input yuv queue*/
1426 total_memtabs_used += ihevce_buff_que_get_mem_recs(
1427 &ps_memtab[total_memtabs_used], num_input_buf_per_queue, space_for_mem_in_enc_grp);
1428 /*------ The encoder owned input buffer queue*/
1429 /* -----Pre-encode Encode Que Mem requests --- */
1430 total_memtabs_used += ihevce_buff_que_get_mem_recs(
1431 &ps_memtab[total_memtabs_used], num_bufs_preenc_me_que, space_for_mem_in_enc_grp);
1432
1433 /* -----ME / Enc-RD opt Que Mem requests --- */
1434 total_memtabs_used += ihevce_buff_que_get_mem_recs(
1435 &ps_memtab[total_memtabs_used], NUM_ME_ENC_BUFS, space_for_mem_in_enc_grp);
1436
1437 /* -----Pre-encode L0 IPE to enc Que Mem requests --- */
1438 total_memtabs_used += ihevce_buff_que_get_mem_recs(
1439 &ps_memtab[total_memtabs_used], num_bufs_L0_ipe_enc, space_for_mem_in_enc_grp);
1440
1441 /* ---------- Dependency Manager allocations -------- */
1442 {
1443 /* --- ME-EncLoop Dep Mngr Row-Row Mem requests -- */
1444 for(ctr = 0; ctr < NUM_ME_ENC_BUFS; ctr++)
1445 {
1446 total_memtabs_used += ihevce_dmgr_get_mem_recs(
1447 &ps_memtab[total_memtabs_used],
1448 DEP_MNGR_ROW_ROW_SYNC,
1449 (a_ctb_align_ht[0] / ctb_size),
1450 ps_enc_ctxt->ps_stat_prms->s_app_tile_params
1451 .i4_num_tile_cols, /* Number of Col Tiles */
1452 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
1453 space_for_mem_in_enc_grp);
1454 }
1455
1456 for(ctr = 0; ctr < i4_num_enc_loop_frm_pllel; ctr++)
1457 {
1458 /* --- Prev. frame EncLoop Done Dep Mngr Frm-Frm Mem requests -- */
1459 total_memtabs_used += ihevce_dmgr_get_mem_recs(
1460 &ps_memtab[total_memtabs_used],
1461 DEP_MNGR_FRM_FRM_SYNC,
1462 (a_ctb_align_ht[0] / ctb_size),
1463 1, /* Number of Col Tiles : Don't care for FRM_FRM */
1464 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
1465 space_for_mem_in_enc_grp);
1466 }
1467 /* --- Prev. frame EncLoop Done for re-encode Dep Mngr Frm-Frm Mem requests -- */
1468 total_memtabs_used += ihevce_dmgr_get_mem_recs(
1469 &ps_memtab[total_memtabs_used],
1470 DEP_MNGR_FRM_FRM_SYNC,
1471 (a_ctb_align_ht[0] / ctb_size),
1472 1, /* Number of Col Tiles : Don't care for FRM_FRM */
1473 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
1474 space_for_mem_in_enc_grp);
1475 for(ctr = 0; ctr < i4_num_me_frm_pllel; ctr++)
1476 {
1477 /* --- Prev. frame ME Done Dep Mngr Frm-Frm Mem requests -- */
1478 total_memtabs_used += ihevce_dmgr_get_mem_recs(
1479 &ps_memtab[total_memtabs_used],
1480 DEP_MNGR_FRM_FRM_SYNC,
1481 (a_ctb_align_ht[0] / ctb_size),
1482 1, /* Number of Col Tiles : Don't care for FRM_FRM */
1483 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
1484 space_for_mem_in_enc_grp);
1485 }
1486
1487 /* --- Prev. frame PreEnc L1 Done Dep Mngr Frm-Frm Mem requests -- */
1488 total_memtabs_used += ihevce_dmgr_get_mem_recs(
1489 &ps_memtab[total_memtabs_used],
1490 DEP_MNGR_FRM_FRM_SYNC,
1491 (a_ctb_align_ht[0] / ctb_size),
1492 1, /* Number of Col Tiles : Don't care for FRM_FRM */
1493 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
1494 space_for_mem_in_enc_grp);
1495
1496 /* --- Prev. frame PreEnc HME Done Dep Mngr Frm-Frm Mem requests -- */
1497 total_memtabs_used += ihevce_dmgr_get_mem_recs(
1498 &ps_memtab[total_memtabs_used],
1499 DEP_MNGR_FRM_FRM_SYNC,
1500 (a_ctb_align_ht[0] / ctb_size),
1501 1, /* Number of Col Tiles : Don't care for FRM_FRM */
1502 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
1503 space_for_mem_in_enc_grp);
1504
1505 /* --- Prev. frame PreEnc L0 Done Dep Mngr Frm-Frm Mem requests -- */
1506 total_memtabs_used += ihevce_dmgr_get_mem_recs(
1507 &ps_memtab[total_memtabs_used],
1508 DEP_MNGR_FRM_FRM_SYNC,
1509 (a_ctb_align_ht[0] / ctb_size),
1510 1, /* Number of Col Tiles : Don't care for FRM_FRM */
1511 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
1512 space_for_mem_in_enc_grp);
1513
1514 /* --- ME-Prev Recon Dep Mngr Row-Frm Mem requests -- */
1515 for(ctr = 0; ctr < (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS); ctr++)
1516 {
1517 WORD32 i4_num_units = num_ctb_horz * num_ctb_vert;
1518
1519 total_memtabs_used += ihevce_dmgr_map_get_mem_recs(
1520 &ps_memtab[total_memtabs_used],
1521 i4_num_units,
1522 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
1523 space_for_mem_in_enc_grp);
1524 }
1525 }
1526
1527 /* ----- allocate memory as per requests ---- */
1528
1529 /* check on memtabs requested v/s memtabs used */
1530 //ittiam : should put an assert
1531
1532 //ASSERT(total_memtabs_used == total_memtabs_req);
1533
1534 for(ctr = 0; ctr < total_memtabs_used; ctr++)
1535 {
1536 UWORD8 *pu1_mem = NULL;
1537 ps_intrf_ctxt->ihevce_mem_alloc(
1538 ps_intrf_ctxt->pv_mem_mgr_hdl, &ps_enc_ctxt->ps_stat_prms->s_sys_api, &ps_memtab[ctr]);
1539
1540 pu1_mem = (UWORD8 *)ps_memtab[ctr].pv_base;
1541
1542 if(NULL == pu1_mem)
1543 {
1544 ps_intrf_ctxt->i4_error_code = IHEVCE_CANNOT_ALLOCATE_MEMORY;
1545 return;
1546 }
1547
1548 memset(pu1_mem, 0, ps_memtab[ctr].i4_mem_size);
1549 }
1550
1551 /* --------------------------------------------------------------------- */
1552 /* --------- Initialisation of Modules & System memory ----------------- */
1553 /* --------------------------------------------------------------------- */
1554
1555 /* store the final allocated memtabs */
1556 ps_enc_ctxt->s_mem_mngr.i4_num_create_memtabs = total_memtabs_used;
1557 ps_enc_ctxt->s_mem_mngr.ps_create_memtab = ps_memtab;
1558
1559 /* ---------- Tiles Mem init --------- */
1560 ps_enc_ctxt->ps_tile_params_base = (ihevce_tile_params_t *)ihevce_tiles_mem_init(
1561 ps_memtab, ps_enc_ctxt->ps_stat_prms, ps_enc_ctxt, i4_resolution_id);
1562
1563 ps_memtab += ihevce_tiles_get_num_mem_recs();
1564
1565 /* ---------- Enc loop Mem init --------- */
1566 ps_enc_ctxt->s_module_ctxt.pv_enc_loop_ctxt = ihevce_enc_loop_init(
1567 ps_memtab,
1568 ps_enc_ctxt->ps_stat_prms,
1569 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
1570 ps_intrf_ctxt->pv_osal_handle,
1571 &ps_enc_ctxt->s_func_selector,
1572 &ps_enc_ctxt->s_rc_quant,
1573 ps_enc_ctxt->ps_tile_params_base,
1574 i4_resolution_id,
1575 i4_num_enc_loop_frm_pllel,
1576 ps_enc_ctxt->u1_is_popcnt_available);
1577
1578 ps_memtab += ihevce_enc_loop_get_num_mem_recs(i4_num_bitrate_inst, i4_num_enc_loop_frm_pllel);
1579 /* ---------- ME Mem init --------------- */
1580 ps_enc_ctxt->s_module_ctxt.pv_me_ctxt = ihevce_me_init(
1581 ps_memtab,
1582 ps_enc_ctxt->ps_stat_prms,
1583 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
1584 ps_intrf_ctxt->pv_osal_handle,
1585 &ps_enc_ctxt->s_rc_quant,
1586 (void *)ps_enc_ctxt->ps_tile_params_base,
1587 i4_resolution_id,
1588 i4_num_me_frm_pllel,
1589 ps_enc_ctxt->u1_is_popcnt_available);
1590
1591 ps_memtab += ihevce_me_get_num_mem_recs(i4_num_me_frm_pllel);
1592
1593 /* ---------- Coarse ME Mem init --------------- */
1594 ps_enc_ctxt->s_module_ctxt.pv_coarse_me_ctxt = ihevce_coarse_me_init(
1595 ps_memtab,
1596 ps_enc_ctxt->ps_stat_prms,
1597 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
1598 ps_intrf_ctxt->pv_osal_handle,
1599 i4_resolution_id,
1600 ps_enc_ctxt->u1_is_popcnt_available);
1601
1602 ps_memtab += ihevce_coarse_me_get_num_mem_recs();
1603 /* ---------- IPE Mem init -------------- */
1604 ps_enc_ctxt->s_module_ctxt.pv_ipe_ctxt = ihevce_ipe_init(
1605 ps_memtab,
1606 ps_enc_ctxt->ps_stat_prms,
1607 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
1608 ps_enc_ctxt->i4_ref_mbr_id,
1609 &ps_enc_ctxt->s_func_selector,
1610 &ps_enc_ctxt->s_rc_quant,
1611 i4_resolution_id,
1612 ps_enc_ctxt->u1_is_popcnt_available);
1613
1614 ps_memtab += ihevce_ipe_get_num_mem_recs();
1615
1616 ps_enc_ctxt->s_rc_quant.i2_max_qp = 51;
1617 ps_enc_ctxt->s_rc_quant.i2_min_qp = 0;
1618 ps_enc_ctxt->s_rc_quant.i1_qp_offset = 0;
1619 ps_enc_ctxt->s_rc_quant.i2_max_qscale =
1620 228 << 3; // Q3 format is mantained for accuarate calc at lower qp
1621 ps_enc_ctxt->s_rc_quant.i2_min_qscale = 1;
1622
1623 /* ---------- ECD Mem init -------------- */
1624 for(i = 0; i < i4_num_bitrate_inst; i++)
1625 {
1626 ps_enc_ctxt->s_module_ctxt.apv_ent_cod_ctxt[i] = ihevce_entropy_init(
1627 ps_memtab,
1628 ps_enc_ctxt->ps_stat_prms,
1629 (void *)ps_enc_ctxt->ps_tile_params_base,
1630 i4_resolution_id);
1631
1632 ps_memtab += ihevce_entropy_get_num_mem_recs();
1633 }
1634
1635 /* ---------- LAP Mem init--------------- */
1636 if(i4_resolution_id == 0)
1637 {
1638 ps_enc_ctxt->s_module_ctxt.pv_lap_ctxt =
1639 ihevce_lap_init(ps_memtab, &ps_enc_ctxt->s_lap_stat_prms, ps_enc_ctxt->ps_stat_prms);
1640
1641 ps_memtab += ihevce_lap_get_num_mem_recs();
1642 }
1643 /*-----------DECOMPOSITION PRE INTRA init----*/
1644 ps_enc_ctxt->s_module_ctxt.pv_decomp_pre_intra_ctxt = ihevce_decomp_pre_intra_init(
1645 ps_memtab,
1646 ps_enc_ctxt->ps_stat_prms,
1647 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
1648 &ps_enc_ctxt->s_func_selector,
1649 i4_resolution_id,
1650 ps_enc_ctxt->u1_is_popcnt_available);
1651
1652 ps_memtab += ihevce_decomp_pre_intra_get_num_mem_recs();
1653
1654 /* ---------- RC Mem init --------------- */
1655 for(i = 0; i < i4_num_bitrate_inst; i++)
1656 {
1657 /*swaping of buf_id for 0th and reference bitrate location, as encoder
1658 assumes always 0th loc for reference bitrate and app must receive in
1659 the configured order*/
1660 if(i == 0)
1661 {
1662 ps_enc_ctxt->s_module_ctxt.apv_rc_ctxt[i] = ihevce_rc_mem_init(
1663 ps_memtab,
1664 ps_enc_ctxt->ps_stat_prms,
1665 ps_enc_ctxt->i4_ref_mbr_id,
1666 &ps_enc_ctxt->s_rc_quant,
1667 ps_enc_ctxt->i4_resolution_id,
1668 ps_enc_ctxt->i4_look_ahead_frames_in_first_pass);
1669 }
1670 else if(i == ps_enc_ctxt->i4_ref_mbr_id)
1671 {
1672 ps_enc_ctxt->s_module_ctxt.apv_rc_ctxt[i] = ihevce_rc_mem_init(
1673 ps_memtab,
1674 ps_enc_ctxt->ps_stat_prms,
1675 0,
1676 &ps_enc_ctxt->s_rc_quant,
1677 ps_enc_ctxt->i4_resolution_id,
1678 ps_enc_ctxt->i4_look_ahead_frames_in_first_pass);
1679 }
1680 else
1681 {
1682 ps_enc_ctxt->s_module_ctxt.apv_rc_ctxt[i] = ihevce_rc_mem_init(
1683 ps_memtab,
1684 ps_enc_ctxt->ps_stat_prms,
1685 i,
1686 &ps_enc_ctxt->s_rc_quant,
1687 ps_enc_ctxt->i4_resolution_id,
1688 ps_enc_ctxt->i4_look_ahead_frames_in_first_pass);
1689 }
1690 ps_memtab += ihevce_rc_get_num_mem_recs();
1691 }
1692
1693 /* ---------- System Mem init ----------- */
1694 {
1695 recon_pic_buf_t **pps_pic_bufs[IHEVCE_MAX_NUM_BITRATES];
1696 recon_pic_buf_t *ps_pic_bufs[IHEVCE_MAX_NUM_BITRATES];
1697 void *pv_recon_buf[IHEVCE_MAX_NUM_BITRATES];
1698 #if(SRC_PADDING_FOR_TRAQO || ENABLE_SSD_CALC_RC)
1699 void *pv_recon_buf_source[IHEVCE_MAX_NUM_BITRATES] = { NULL };
1700 #endif
1701 void *pv_uv_recon_buf[IHEVCE_MAX_NUM_BITRATES];
1702 UWORD8 *pu1_subpel_buf;
1703 pu_col_mv_t *ps_col_mv;
1704 UWORD8 *pu1_col_mv_map;
1705 UWORD16 *pu2_col_num_pu_map;
1706 UWORD32 *pu4_col_mv_off;
1707 WORD32 luma_frm_size;
1708 WORD32 recon_stride; /* stride for Y and UV(interleave) */
1709 WORD32 luma_frm_height; /* including padding */
1710 WORD32 num_pu_in_frm;
1711
1712 /* pps tile memory */
1713 for(i = 0; i < i4_num_bitrate_inst; i++)
1714 {
1715 ps_enc_ctxt->as_pps[i].ps_tile = (tile_t *)ps_memtab->pv_base;
1716 }
1717
1718 ps_memtab++; /* increment the memtabs */
1719
1720 /* recon picture buffer pointer array */
1721 for(i = 0; i < i4_num_bitrate_inst; i++)
1722 {
1723 pps_pic_bufs[i] = (recon_pic_buf_t **)ps_memtab->pv_base;
1724 ps_memtab++; /* increment the memtabs */
1725 }
1726
1727 /* recon picture buffers structures */
1728 for(i = 0; i < i4_num_bitrate_inst; i++)
1729 {
1730 ps_pic_bufs[i] = (recon_pic_buf_t *)ps_memtab->pv_base;
1731 ps_memtab++; /* increment the memtabs */
1732 }
1733
1734 /* reference/recon picture buffers */
1735 for(i = 0; i < i4_num_bitrate_inst; i++)
1736 {
1737 pv_recon_buf[i] = ps_memtab->pv_base;
1738 ps_memtab++; /* increment the memtabs */
1739 }
1740 /* reference/recon picture subpel planes */
1741 pu1_subpel_buf = (UWORD8 *)ps_memtab->pv_base;
1742 /* increment the memtabs */
1743 ps_memtab++;
1744 /* reference colocated MV bank */
1745 ps_col_mv = (pu_col_mv_t *)ps_memtab->pv_base;
1746 /* increment the memtabs */
1747 ps_memtab++;
1748
1749 /* reference colocated MV bank map */
1750 pu1_col_mv_map = (UWORD8 *)ps_memtab->pv_base;
1751 /* increment the memtabs */
1752 ps_memtab++;
1753
1754 /* reference collocated MV bank map offsets map */
1755 pu2_col_num_pu_map = (UWORD16 *)ps_memtab->pv_base;
1756 /* increment the memtabs */
1757 ps_memtab++;
1758
1759 /* reference colocated MV bank ctb offset */
1760 pu4_col_mv_off = (UWORD32 *)ps_memtab->pv_base;
1761 /* increment the memtabs */
1762 ps_memtab++;
1763
1764 /* compute the stride and frame height after accounting for padding */
1765 recon_stride = ((num_ctb_horz * ctb_size) + (PAD_HORZ << 1));
1766 luma_frm_height = ((num_ctb_vert * ctb_size) + (PAD_VERT << 1));
1767 luma_frm_size = recon_stride * luma_frm_height;
1768 /* The subpel buffer is also incremented to take care of padding */
1769 /* Both luma and subpel buffer use same stride */
1770 pu1_subpel_buf += (recon_stride * PAD_VERT);
1771 pu1_subpel_buf += PAD_HORZ;
1772
1773 /* Keep memory for an extra CTB at the right and bottom of frame.
1774 This extra space is needed by dist-encoding and unused in non-dist-encoding */
1775 num_pu_in_frm = (num_ctb_horz + 1) * num_pu_in_ctb * (num_ctb_vert + 1);
1776
1777 for(i = 0; i < i4_num_bitrate_inst; i++)
1778 {
1779 pv_uv_recon_buf[i] = pv_recon_buf[i];
1780
1781 /* increment the recon buffer to take care of padding */
1782 pv_recon_buf[i] = (UWORD8 *)pv_recon_buf[i] + (recon_stride * PAD_VERT) + PAD_HORZ;
1783
1784 /* chroma buffer starts at the end of luma buffer */
1785 pv_uv_recon_buf[i] = (UWORD8 *)pv_uv_recon_buf[i] + luma_frm_size;
1786 if(ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.i4_internal_bit_depth == 8)
1787 {
1788 /* increment the chroma recon buffer to take care of padding */
1789 /* vert padding halved but horiz is same due to uv interleave */
1790 pv_uv_recon_buf[i] =
1791 (UWORD8 *)pv_uv_recon_buf[i] + (recon_stride * (PAD_VERT >> 1)) +
1792 ((ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_chr_format == IV_YUV_422SP_UV)
1793 ? (recon_stride * (PAD_VERT >> 1))
1794 : 0);
1795 pv_uv_recon_buf[i] = (UWORD8 *)pv_uv_recon_buf[i] + PAD_HORZ;
1796 }
1797
1798 /* loop to initialise all the memories */
1799 /* initialize recon buffers */
1800 /* only YUV buffers are allocated for each bit-rate instnaces.
1801 Subpel buffers and col buffers are made NULL for auxiliary bit-rate instances,
1802 since ME and IPE happens only for reference bit-rate instnace */
1803 for(ctr = 0; ctr < (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS); ctr++)
1804 {
1805 pps_pic_bufs[i][ctr] =
1806 ps_pic_bufs[i]; //check the index of pps [i] should be first or last index?!!
1807
1808 ps_pic_bufs[i]->s_yuv_buf_desc.i4_size = sizeof(iv_enc_yuv_buf_t);
1809 ps_pic_bufs[i]->s_yuv_buf_desc.pv_y_buf = pv_recon_buf[i];
1810 ps_pic_bufs[i]->s_yuv_buf_desc.pv_v_buf = NULL;
1811 {
1812 ps_pic_bufs[i]->s_yuv_buf_desc.pv_u_buf = pv_uv_recon_buf[i];
1813 }
1814 ps_pic_bufs[i]->apu1_y_sub_pel_planes[0] = ((i == 0) ? pu1_subpel_buf : NULL);
1815 ps_pic_bufs[i]->apu1_y_sub_pel_planes[1] =
1816 ((i == 0) ? (pu1_subpel_buf + luma_frm_size) : NULL);
1817 ps_pic_bufs[i]->apu1_y_sub_pel_planes[2] =
1818 ((i == 0) ? (pu1_subpel_buf + (luma_frm_size * 2)) : NULL);
1819 ps_pic_bufs[i]->ps_frm_col_mv = ps_col_mv;
1820 ps_pic_bufs[i]->pu1_frm_pu_map = pu1_col_mv_map;
1821 ps_pic_bufs[i]->pu2_num_pu_map = pu2_col_num_pu_map;
1822 ps_pic_bufs[i]->pu4_pu_off = pu4_col_mv_off;
1823 ps_pic_bufs[i]->i4_is_free = 1;
1824 ps_pic_bufs[i]->i4_poc = -1;
1825 ps_pic_bufs[i]->i4_display_num = -1;
1826 ps_pic_bufs[i]->i4_buf_id = ctr;
1827
1828 /* frame level buff increments */
1829 ps_col_mv += num_pu_in_frm;
1830 pu1_col_mv_map += num_pu_in_frm;
1831 pu2_col_num_pu_map += (num_ctb_horz * num_ctb_vert);
1832 pu4_col_mv_off += (num_ctb_horz * num_ctb_vert);
1833
1834 if(ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_chr_format == IV_YUV_422SP_UV)
1835 {
1836 pv_recon_buf[i] = (UWORD8 *)pv_recon_buf[i] + (luma_frm_size << 1);
1837 pv_uv_recon_buf[i] = (UWORD8 *)pv_uv_recon_buf[i] + (luma_frm_size << 1);
1838 }
1839 else
1840 {
1841 pv_recon_buf[i] = (UWORD8 *)pv_recon_buf[i] + ((3 * luma_frm_size) >> 1);
1842 pv_uv_recon_buf[i] = (UWORD8 *)pv_uv_recon_buf[i] + ((3 * luma_frm_size) >> 1);
1843 }
1844 pu1_subpel_buf += ((3 + L0ME_IN_OPENLOOP_MODE) * luma_frm_size); /* 3 planes */
1845 ps_pic_bufs[i]++;
1846 } //ctr ends
1847
1848 /* store the queue pointer and num buffs to context */
1849 ps_enc_ctxt->pps_recon_buf_q[i] = pps_pic_bufs[i];
1850 ps_enc_ctxt->ai4_num_buf_recon_q[i] = (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS);
1851
1852 } //bitrate ctr ends
1853
1854 } //end of system memory init
1855
1856 /* Pre encode group recon buffer containier NO Buffers will be allocated / used */
1857 {
1858 recon_pic_buf_t *ps_pic_bufs;
1859
1860 /* recon picture buffer pointer array */
1861 pps_pre_enc_pic_bufs = (recon_pic_buf_t **)ps_memtab->pv_base;
1862 /* increment the memtabs */
1863 ps_memtab++;
1864
1865 /* recon picture buffers structures */
1866 ps_pic_bufs = (recon_pic_buf_t *)ps_memtab->pv_base;
1867 /* increment the memtabs */
1868 ps_memtab++;
1869
1870 /* loop to initialise all the memories */
1871 for(ctr = 0; ctr < (max_num_ref_pics + 1); ctr++)
1872 {
1873 pps_pre_enc_pic_bufs[ctr] = ps_pic_bufs;
1874
1875 ps_pic_bufs->s_yuv_buf_desc.i4_size = sizeof(iv_enc_yuv_buf_t);
1876 ps_pic_bufs->s_yuv_buf_desc.pv_y_buf = NULL;
1877 ps_pic_bufs->s_yuv_buf_desc.pv_u_buf = NULL;
1878 ps_pic_bufs->s_yuv_buf_desc.pv_v_buf = NULL;
1879 ps_pic_bufs->apu1_y_sub_pel_planes[0] = NULL;
1880 ps_pic_bufs->apu1_y_sub_pel_planes[1] = NULL;
1881 ps_pic_bufs->apu1_y_sub_pel_planes[2] = NULL;
1882 ps_pic_bufs->ps_frm_col_mv = NULL;
1883 ps_pic_bufs->pu1_frm_pu_map = NULL;
1884 ps_pic_bufs->pu2_num_pu_map = NULL;
1885 ps_pic_bufs->pu4_pu_off = NULL;
1886 ps_pic_bufs->i4_is_free = 1;
1887 ps_pic_bufs->i4_poc = -1;
1888 ps_pic_bufs->i4_buf_id = ctr;
1889
1890 /* frame level buff increments */
1891 ps_pic_bufs++;
1892 }
1893
1894 /* store the queue pointer and num buffs to context */
1895 ps_enc_ctxt->pps_pre_enc_recon_buf_q = pps_pre_enc_pic_bufs;
1896 ps_enc_ctxt->i4_pre_enc_num_buf_recon_q = (max_num_ref_pics + 1);
1897 }
1898
1899 /* Frame level buffers and Que between pre-encode & encode */
1900 {
1901 pre_enc_me_ctxt_t *ps_pre_enc_bufs;
1902 pre_enc_L0_ipe_encloop_ctxt_t *ps_L0_ipe_enc_bufs;
1903 ihevce_lap_enc_buf_t *ps_lap_enc_input_buf;
1904 ctb_analyse_t *ps_ctb_analyse;
1905 UWORD8 *pu1_me_lyr_ctxt;
1906 UWORD8 *pu1_me_lyr_bank_ctxt;
1907 UWORD8 *pu1_mv_bank;
1908 UWORD8 *pu1_ref_idx_bank;
1909 double *plf_intra_8x8_cost;
1910 ipe_l0_ctb_analyse_for_me_t *ps_ipe_analyse_ctb;
1911 ihevce_ed_ctb_l1_t *ps_ed_ctb_l1;
1912 ihevce_ed_blk_t *ps_layer1_buf;
1913 ihevce_ed_blk_t *ps_layer2_buf;
1914 ihevce_8x8_L0_satd_t *ps_layer0_cur_satd;
1915 ihevce_8x8_L0_mean_t *ps_layer0_cur_mean;
1916 UWORD8 *pu1_lap_input_yuv_buf[4];
1917 UWORD8 *pu1_input_synch_ctrl_cmd;
1918 WORD32 i4_count = 0;
1919 /*initialize the memory for input buffer*/
1920 {
1921 for(i4_count = 0; i4_count < i4_total_queues; i4_count++)
1922 {
1923 pu1_lap_input_yuv_buf[i4_count] = (UWORD8 *)ps_memtab->pv_base;
1924 /* increment the memtabs */
1925 ps_memtab++;
1926 }
1927 pps_lap_enc_input_bufs = (ihevce_lap_enc_buf_t **)ps_memtab->pv_base;
1928 /* increment the memtabs */
1929 ps_memtab++;
1930
1931 /*memory for the input buffer structure*/
1932 ps_lap_enc_input_buf = (ihevce_lap_enc_buf_t *)ps_memtab->pv_base;
1933 ps_memtab++;
1934
1935 pu1_input_synch_ctrl_cmd = (UWORD8 *)ps_memtab->pv_base;
1936 ps_memtab++;
1937 }
1938 /* pre encode /encode coding buffer pointer array */
1939 pps_pre_enc_bufs = (pre_enc_me_ctxt_t **)ps_memtab->pv_base;
1940 /* increment the memtabs */
1941 ps_memtab++;
1942
1943 /* pre encode /encode buffer structure */
1944 ps_pre_enc_bufs = (pre_enc_me_ctxt_t *)ps_memtab->pv_base;
1945 /* increment the memtabs */
1946 ps_memtab++;
1947
1948 /* Pre-encode L0 IPE output to ME buffer pointer */
1949 pps_L0_ipe_enc_bufs = (pre_enc_L0_ipe_encloop_ctxt_t **)ps_memtab->pv_base;
1950 /* increment the memtabs */
1951 ps_memtab++;
1952
1953 /* Pre-encode L0 IPE output to ME buffer */
1954 ps_L0_ipe_enc_bufs = (pre_enc_L0_ipe_encloop_ctxt_t *)ps_memtab->pv_base;
1955 /* increment the memtabs */
1956 ps_memtab++;
1957
1958 /* CTB analyse Frame level */
1959 ps_ctb_analyse = (ctb_analyse_t *)ps_memtab->pv_base;
1960 /* increment the memtabs */
1961 ps_memtab++;
1962
1963 /* ME layer ctxt Frame level */
1964 pu1_me_lyr_ctxt = (UWORD8 *)ps_memtab->pv_base;
1965 /* increment the memtabs */
1966 ps_memtab++;
1967
1968 /* ME layer bank ctxt Frame level */
1969 pu1_me_lyr_bank_ctxt = (UWORD8 *)ps_memtab->pv_base;
1970 /* increment the memtabs */
1971 ps_memtab++;
1972
1973 /* ME layer MV bank Frame level */
1974 pu1_mv_bank = (UWORD8 *)ps_memtab->pv_base;
1975 /* increment the memtabs */
1976 ps_memtab++;
1977
1978 /* ME layer ref idx bank Frame level */
1979 pu1_ref_idx_bank = (UWORD8 *)ps_memtab->pv_base;
1980 /* increment the memtabs */
1981 ps_memtab++;
1982 /* 8x8 intra costs for entire frame */
1983 plf_intra_8x8_cost = (double *)ps_memtab->pv_base;
1984 ps_memtab++;
1985
1986 /* ctb intra costs and modes for entire frame */
1987 ps_ipe_analyse_ctb = (ipe_l0_ctb_analyse_for_me_t *)ps_memtab->pv_base;
1988 ps_memtab++;
1989
1990 /*L0 8x8 cur satd for qp mod*/
1991 ps_layer0_cur_satd = (ihevce_8x8_L0_satd_t *)ps_memtab->pv_base;
1992 ps_memtab++;
1993
1994 /*L0 8x8 cur mean for qp mod*/
1995 ps_layer0_cur_mean = (ihevce_8x8_L0_mean_t *)ps_memtab->pv_base;
1996 ps_memtab++;
1997
1998 /*Contains ctb level information at pre-intra stage */
1999 ps_ed_ctb_l1 = (ihevce_ed_ctb_l1_t *)ps_memtab->pv_base;
2000 ps_memtab++;
2001
2002 /* Layer L1 buf */
2003 ps_layer1_buf = (ihevce_ed_blk_t *)ps_memtab->pv_base;
2004 /* increment the memtabs */
2005 ps_memtab++;
2006
2007 /* Layer2 buf */
2008 ps_layer2_buf = (ihevce_ed_blk_t *)ps_memtab->pv_base;
2009 /* increment the memtabs */
2010 ps_memtab++;
2011
2012 /* loop to initialise all the memories*/
2013 /*mrs: assign individual input yuv frame pointers here*/
2014
2015 i4_count = 0;
2016 /* loop to initialise the buffer pointer */
2017 for(ctr = 0; ctr < num_input_buf_per_queue; ctr++)
2018 {
2019 pps_lap_enc_input_bufs[ctr] = &ps_lap_enc_input_buf[ctr];
2020
2021 pps_lap_enc_input_bufs[ctr]->s_input_buf.i4_size = sizeof(iv_input_data_ctrl_buffs_t);
2022
2023 pps_lap_enc_input_bufs[ctr]->s_input_buf.pv_synch_ctrl_bufs = pu1_input_synch_ctrl_cmd;
2024
2025 pps_lap_enc_input_bufs[ctr]->s_input_buf.s_input_buf.i4_size = sizeof(iv_yuv_buf_t);
2026
2027 pu1_input_synch_ctrl_cmd += ENC_COMMAND_BUFF_SIZE;
2028 /*pointer to i/p buf initialised to null in case of run time allocation*/
2029
2030 {
2031 pps_lap_enc_input_bufs[ctr]->s_lap_out.s_input_buf.pv_y_buf =
2032 pu1_lap_input_yuv_buf[i4_count];
2033
2034 pps_lap_enc_input_bufs[ctr]->s_lap_out.s_input_buf.pv_u_buf =
2035 pu1_lap_input_yuv_buf[i4_count] + i4_luma_min_size;
2036
2037 pps_lap_enc_input_bufs[ctr]->s_lap_out.s_input_buf.pv_v_buf =
2038 NULL; /*since yuv 420 format*/
2039
2040 pu1_lap_input_yuv_buf[i4_count] += i4_yuv_min_size;
2041
2042 if(((ctr + 1) % MAX_QUEUE) == 0)
2043 i4_count++;
2044 }
2045 }
2046 for(ctr = 0; ctr < num_bufs_preenc_me_que; ctr++)
2047 {
2048 pps_pre_enc_bufs[ctr] = ps_pre_enc_bufs;
2049
2050 ps_pre_enc_bufs->ps_ctb_analyse = ps_ctb_analyse;
2051 ps_pre_enc_bufs->pv_me_lyr_ctxt = (void *)pu1_me_lyr_ctxt;
2052 ps_pre_enc_bufs->pv_me_lyr_bnk_ctxt = (void *)pu1_me_lyr_bank_ctxt;
2053 ps_pre_enc_bufs->pv_me_mv_bank = (void *)pu1_mv_bank;
2054 ps_pre_enc_bufs->pv_me_ref_idx = (void *)pu1_ref_idx_bank;
2055 ps_pre_enc_bufs->ps_layer1_buf = ps_layer1_buf;
2056 ps_pre_enc_bufs->ps_layer2_buf = ps_layer2_buf;
2057 ps_pre_enc_bufs->ps_layer0_cur_satd = ps_layer0_cur_satd;
2058 ps_pre_enc_bufs->ps_layer0_cur_mean = ps_layer0_cur_mean;
2059 ps_pre_enc_bufs->ps_ed_ctb_l1 = ps_ed_ctb_l1;
2060 ps_pre_enc_bufs->plf_intra_8x8_cost = plf_intra_8x8_cost;
2061
2062 ps_ctb_analyse += num_ctb_horz * num_ctb_vert;
2063 pu1_me_lyr_ctxt += sizeof(layer_ctxt_t);
2064 pu1_me_lyr_bank_ctxt += sizeof(layer_mv_t);
2065 pu1_mv_bank += mv_bank_size;
2066 pu1_ref_idx_bank += ref_idx_bank_size;
2067 plf_intra_8x8_cost +=
2068 (((num_ctb_horz * ctb_size) >> 3) * ((num_ctb_vert * ctb_size) >> 3));
2069 ps_ed_ctb_l1 += (a_ctb_align_wd[1] >> 5) * (a_ctb_align_ht[1] >> 5);
2070 ps_layer1_buf += (a_ctb_align_wd[1] >> 2) * (a_ctb_align_ht[1] >> 2);
2071 ps_layer2_buf += (a_ctb_align_wd[2] >> 2) * (a_ctb_align_ht[2] >> 2);
2072 ps_layer0_cur_satd += (a_ctb_align_wd[0] >> 3) * (a_ctb_align_ht[0] >> 3);
2073 ps_pre_enc_bufs++;
2074 }
2075
2076 for(ctr = 0; ctr < num_bufs_L0_ipe_enc; ctr++)
2077 {
2078 pps_L0_ipe_enc_bufs[ctr] = ps_L0_ipe_enc_bufs;
2079 ps_L0_ipe_enc_bufs->ps_ipe_analyse_ctb = ps_ipe_analyse_ctb;
2080 ps_ipe_analyse_ctb += num_ctb_horz * num_ctb_vert;
2081 ps_L0_ipe_enc_bufs++;
2082 }
2083 }
2084
2085 /* Frame level que between ME and Enc rd-opt */
2086 {
2087 me_enc_rdopt_ctxt_t *ps_me_enc_bufs;
2088 job_queue_t *ps_job_q_enc;
2089 me_ctb_data_t *ps_cur_ctb_me_data;
2090 cur_ctb_cu_tree_t *ps_cur_ctb_cu_tree;
2091
2092 /* pre encode /encode coding buffer pointer array */
2093 pps_me_enc_bufs = (me_enc_rdopt_ctxt_t **)ps_memtab->pv_base;
2094 /* increment the memtabs */
2095 ps_memtab++;
2096
2097 /* pre encode /encode buffer structure */
2098 ps_me_enc_bufs = (me_enc_rdopt_ctxt_t *)ps_memtab->pv_base;
2099 /* increment the memtabs */
2100 ps_memtab++;
2101
2102 /*me and enc job queue memory */
2103 ps_job_q_enc = (job_queue_t *)ps_memtab->pv_base;
2104 /* increment the memtabs */
2105 ps_memtab++;
2106
2107 /*ctb me data memory*/
2108 ps_cur_ctb_cu_tree = (cur_ctb_cu_tree_t *)ps_memtab->pv_base;
2109 /* increment the memtabs */
2110 ps_memtab++;
2111
2112 /*ctb me data memory*/
2113 ps_cur_ctb_me_data = (me_ctb_data_t *)ps_memtab->pv_base;
2114 /* increment the memtabs */
2115 ps_memtab++;
2116
2117 /* loop to initialise all the memories */
2118 for(ctr = 0; ctr < NUM_ME_ENC_BUFS; ctr++)
2119 {
2120 pps_me_enc_bufs[ctr] = ps_me_enc_bufs;
2121
2122 ps_me_enc_bufs->ps_job_q_enc = ps_job_q_enc;
2123 ps_me_enc_bufs->ps_cur_ctb_cu_tree = ps_cur_ctb_cu_tree;
2124 ps_me_enc_bufs->ps_cur_ctb_me_data = ps_cur_ctb_me_data;
2125
2126 ps_job_q_enc += (MAX_NUM_VERT_UNITS_FRM * NUM_ENC_JOBS_QUES);
2127 /* In tile case, based on the number of column tiles,
2128 increment jobQ per column tile */
2129 if(1 == ps_enc_ctxt->ps_stat_prms->s_app_tile_params.i4_tiles_enabled_flag)
2130 {
2131 WORD32 col_tile_ctr;
2132 for(col_tile_ctr = 1;
2133 col_tile_ctr < ps_enc_ctxt->ps_stat_prms->s_app_tile_params.i4_num_tile_cols;
2134 col_tile_ctr++)
2135 {
2136 ps_job_q_enc += (MAX_NUM_VERT_UNITS_FRM * NUM_ENC_JOBS_QUES);
2137 }
2138 }
2139
2140 ps_cur_ctb_cu_tree += (num_ctb_horz * MAX_NUM_NODES_CU_TREE * num_ctb_vert);
2141 ps_cur_ctb_me_data += (num_ctb_horz * num_ctb_vert);
2142
2143 ps_me_enc_bufs++;
2144 }
2145 }
2146 /* Frame level Que between frame process & entropy */
2147 for(i = 0; i < i4_num_bitrate_inst; i++)
2148 {
2149 frm_proc_ent_cod_ctxt_t *ps_frmp_ent_bufs;
2150 ctb_enc_loop_out_t *ps_ctb;
2151 cu_enc_loop_out_t *ps_cu;
2152 tu_enc_loop_out_t *ps_tu;
2153 pu_t *ps_pu;
2154 UWORD8 *pu1_coeffs;
2155 WORD32 num_ctb_in_frm;
2156 WORD32 coeff_size;
2157 UWORD8 *pu1_sei_payload;
2158
2159 /* frame process/entropy coding buffer pointer array */
2160 pps_frm_proc_ent_cod_bufs[i] = (frm_proc_ent_cod_ctxt_t **)ps_memtab->pv_base;
2161 /* increment the memtabs */
2162 ps_memtab++;
2163
2164 /* frame process/entropy coding buffer structure */
2165 ps_frmp_ent_bufs = (frm_proc_ent_cod_ctxt_t *)ps_memtab->pv_base;
2166 /* increment the memtabs */
2167 ps_memtab++;
2168
2169 /* CTB enc loop Frame level */
2170 ps_ctb = (ctb_enc_loop_out_t *)ps_memtab->pv_base;
2171 /* increment the memtabs */
2172 ps_memtab++;
2173
2174 /* CU enc loop Frame level */
2175 ps_cu = (cu_enc_loop_out_t *)ps_memtab->pv_base;
2176 /* increment the memtabs */
2177 ps_memtab++;
2178
2179 /* TU enc loop Frame level */
2180 ps_tu = (tu_enc_loop_out_t *)ps_memtab->pv_base;
2181 /* increment the memtabs */
2182 ps_memtab++;
2183
2184 /* PU enc loop Frame level */
2185 ps_pu = (pu_t *)ps_memtab->pv_base;
2186 /* increment the memtabs */
2187 ps_memtab++;
2188
2189 /* Coeffs Frame level */
2190 pu1_coeffs = (UWORD8 *)ps_memtab->pv_base;
2191 /* increment the memtabs */
2192 ps_memtab++;
2193
2194 /* CC User Data */
2195 pu1_sei_payload = (UWORD8 *)ps_memtab->pv_base;
2196 ps_memtab++;
2197
2198 num_ctb_in_frm = num_ctb_horz * num_ctb_vert;
2199
2200 /* calculate the coeff size */
2201 coeff_size =
2202 num_ctb_horz * ((ps_enc_ctxt->ps_stat_prms->s_src_prms.i4_chr_format == IV_YUV_422SP_UV)
2203 ? (num_tu_in_ctb << 1)
2204 : ((num_tu_in_ctb * 3) >> 1));
2205 coeff_size = coeff_size * num_ctb_vert * MAX_SCAN_COEFFS_BYTES_4x4;
2206 /* loop to initialise all the memories */
2207 for(ctr = 0; ctr < NUM_FRMPROC_ENTCOD_BUFS; ctr++)
2208 {
2209 WORD32 num_sei;
2210 pps_frm_proc_ent_cod_bufs[i][ctr] = ps_frmp_ent_bufs;
2211
2212 ps_frmp_ent_bufs->ps_frm_ctb_data = ps_ctb;
2213 ps_frmp_ent_bufs->ps_frm_cu_data = ps_cu;
2214 ps_frmp_ent_bufs->ps_frm_pu_data = ps_pu;
2215 ps_frmp_ent_bufs->ps_frm_tu_data = ps_tu;
2216 ps_frmp_ent_bufs->pv_coeff_data = pu1_coeffs;
2217
2218 /* memset the slice headers and buffer to keep track */
2219 memset(&ps_frmp_ent_bufs->s_slice_hdr, 0, sizeof(slice_header_t));
2220
2221 /*PIC_INFO*/
2222 memset(&ps_frmp_ent_bufs->s_pic_level_info, 0, sizeof(s_pic_level_acc_info_t));
2223
2224 ps_ctb += num_ctb_in_frm;
2225 ps_cu += num_ctb_in_frm * num_cu_in_ctb;
2226 ps_pu += num_ctb_in_frm * num_pu_in_ctb;
2227 ps_tu += num_ctb_in_frm * num_tu_in_ctb;
2228
2229 pu1_coeffs += coeff_size;
2230
2231 for(num_sei = 0; num_sei < MAX_NUMBER_OF_SEI_PAYLOAD; num_sei++)
2232 {
2233 ps_frmp_ent_bufs->as_sei_payload[num_sei].pu1_sei_payload = pu1_sei_payload;
2234 ps_frmp_ent_bufs->as_sei_payload[num_sei].u4_payload_type = 0;
2235 ps_frmp_ent_bufs->as_sei_payload[num_sei].u4_payload_length = 0;
2236 pu1_sei_payload += MAX_SEI_PAYLOAD_PER_TLV;
2237 }
2238
2239 ps_frmp_ent_bufs++;
2240 }
2241 }
2242
2243 /* Working memory for encoder */
2244 ps_enc_ctxt->pu1_frm_lvl_wkg_mem = (UWORD8 *)ps_memtab->pv_base;
2245 ps_memtab++;
2246
2247 /* Job Que memory */
2248 /* Job que memory distribution is as follows _______
2249 enc_group_ping -> MAX_NUM_VERT_UNITS_FRM for all the passes (NUM_ENC_JOBS_QUES)------------>|_______|
2250 enc_group_pong -> MAX_NUM_VERT_UNITS_FRM for all the passes (NUM_ENC_JOBS_QUES)------------>|_______|
2251 pre_enc_group_ping -> MAX_NUM_VERT_UNITS_FRM for all the passes (NUM_PRE_ENC_JOBS_QUES)---->|_______|
2252 pre_enc_group_ping -> MAX_NUM_VERT_UNITS_FRM for all the passes (NUM_PRE_ENC_JOBS_QUES)---->|_______|
2253 */
2254
2255 ps_enc_ctxt->s_multi_thrd.aps_job_q_pre_enc[0] = (job_queue_t *)ps_memtab->pv_base;
2256 for(ctr = 1; ctr < MAX_PRE_ENC_STAGGER + NUM_BUFS_DECOMP_HME; ctr++)
2257 {
2258 ps_enc_ctxt->s_multi_thrd.aps_job_q_pre_enc[ctr] =
2259 ps_enc_ctxt->s_multi_thrd.aps_job_q_pre_enc[0] +
2260 (MAX_NUM_VERT_UNITS_FRM * NUM_PRE_ENC_JOBS_QUES * ctr);
2261 }
2262 ps_memtab++;
2263
2264 /* -----Frameproc Entcod Que mem_init --- */
2265 /* init ptrs for each bit-rate */
2266 for(i = 0; i < i4_num_bitrate_inst; i++)
2267 {
2268 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_FRM_PRS_ENT_COD_Q + i] = ihevce_buff_que_init(
2269 ps_memtab, NUM_FRMPROC_ENTCOD_BUFS, (void **)pps_frm_proc_ent_cod_bufs[i]);
2270 ps_memtab += ihevce_buff_que_get_num_mem_recs();
2271 }
2272 /*mrs*/
2273 /* ----Encoder owned input buffer queue init----*/
2274 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_ENC_INPUT_Q] =
2275 ihevce_buff_que_init(ps_memtab, num_input_buf_per_queue, (void **)pps_lap_enc_input_bufs);
2276 ps_memtab += ihevce_buff_que_get_num_mem_recs();
2277
2278 /* -----Pre-Encode / Encode Que mem_init --- */
2279 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_PRE_ENC_ME_Q] =
2280 ihevce_buff_que_init(ps_memtab, num_bufs_preenc_me_que, (void **)pps_pre_enc_bufs);
2281
2282 ps_memtab += ihevce_buff_que_get_num_mem_recs();
2283
2284 /* -----ME / Enc-RD opt Que mem_init --- */
2285 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_ME_ENC_RDOPT_Q] =
2286 ihevce_buff_que_init(ps_memtab, NUM_ME_ENC_BUFS, (void **)pps_me_enc_bufs);
2287
2288 ps_memtab += ihevce_buff_que_get_num_mem_recs();
2289
2290 /* -----Pre-Encode L0 IPE to enc queue --- */
2291 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_L0_IPE_ENC_Q] =
2292 ihevce_buff_que_init(ps_memtab, num_bufs_L0_ipe_enc, (void **)pps_L0_ipe_enc_bufs);
2293
2294 ps_memtab += ihevce_buff_que_get_num_mem_recs();
2295
2296 /* ---------- Dependency Manager allocations -------- */
2297 {
2298 osal_sem_attr_t attr = OSAL_DEFAULT_SEM_ATTR;
2299 WORD32 i1_is_sem_enabled;
2300
2301 if(ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id]
2302 .i4_quality_preset >= IHEVCE_QUALITY_P4)
2303 {
2304 i1_is_sem_enabled = 0;
2305 }
2306 else
2307 {
2308 i1_is_sem_enabled = 1;
2309 }
2310
2311 /* allocate semaphores for all the threads in pre-enc and enc */
2312 for(ctr = 0; ctr < ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds; ctr++)
2313 {
2314 ps_enc_ctxt->s_multi_thrd.apv_enc_thrd_sem_handle[ctr] =
2315 osal_sem_create(ps_intrf_ctxt->pv_osal_handle, &attr);
2316 if(NULL == ps_enc_ctxt->s_multi_thrd.apv_enc_thrd_sem_handle[ctr])
2317 {
2318 ps_intrf_ctxt->i4_error_code = IHEVCE_CANNOT_ALLOCATE_MEMORY;
2319 return;
2320 }
2321 }
2322
2323 for(ctr = 0; ctr < ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds; ctr++)
2324 {
2325 ps_enc_ctxt->s_multi_thrd.apv_pre_enc_thrd_sem_handle[ctr] =
2326 osal_sem_create(ps_intrf_ctxt->pv_osal_handle, &attr);
2327 if(NULL == ps_enc_ctxt->s_multi_thrd.apv_pre_enc_thrd_sem_handle[ctr])
2328 {
2329 ps_intrf_ctxt->i4_error_code = IHEVCE_CANNOT_ALLOCATE_MEMORY;
2330 return;
2331 }
2332 }
2333
2334 /* --- ME-EncLoop Dep Mngr Row-Row Init -- */
2335 for(ctr = 0; ctr < NUM_ME_ENC_BUFS; ctr++)
2336 {
2337 me_enc_rdopt_ctxt_t *ps_me_enc_bufs = pps_me_enc_bufs[ctr];
2338
2339 ps_me_enc_bufs->pv_dep_mngr_encloop_dep_me = ihevce_dmgr_init(
2340 ps_memtab,
2341 ps_intrf_ctxt->pv_osal_handle,
2342 DEP_MNGR_ROW_ROW_SYNC,
2343 (a_ctb_align_ht[0] / ctb_size),
2344 (a_ctb_align_wd[0] / ctb_size),
2345 ps_enc_ctxt->ps_tile_params_base->i4_num_tile_cols, /* Number of Col Tiles */
2346 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
2347 i1_is_sem_enabled /*Sem Disabled/Enabled*/
2348 );
2349 ps_memtab += ihevce_dmgr_get_num_mem_recs();
2350
2351 /* Register Enc group semaphore handles */
2352 ihevce_dmgr_reg_sem_hdls(
2353 ps_me_enc_bufs->pv_dep_mngr_encloop_dep_me,
2354 ps_enc_ctxt->s_multi_thrd.apv_enc_thrd_sem_handle,
2355 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds);
2356
2357 /* Register the handle in multithread ctxt also for free purpose */
2358 ps_enc_ctxt->s_multi_thrd.apv_dep_mngr_encloop_dep_me[ctr] =
2359 ps_me_enc_bufs->pv_dep_mngr_encloop_dep_me;
2360 }
2361
2362 for(ctr = 0; ctr < i4_num_enc_loop_frm_pllel; ctr++)
2363 {
2364 /* --- Prev. frame EncLoop Done Dep Mngr Frm-Frm Mem Init -- */
2365 ps_enc_ctxt->s_multi_thrd.apv_dep_mngr_prev_frame_done[ctr] = ihevce_dmgr_init(
2366 ps_memtab,
2367 ps_intrf_ctxt->pv_osal_handle,
2368 DEP_MNGR_FRM_FRM_SYNC,
2369 (a_ctb_align_ht[0] / ctb_size),
2370 (a_ctb_align_wd[0] / ctb_size),
2371 1, /* Number of Col Tiles : Don't care for FRM_FRM */
2372 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
2373 1 /*Sem Enabled*/
2374 );
2375 ps_memtab += ihevce_dmgr_get_num_mem_recs();
2376
2377 /* Register Enc group semaphore handles */
2378 ihevce_dmgr_reg_sem_hdls(
2379 ps_enc_ctxt->s_multi_thrd.apv_dep_mngr_prev_frame_done[ctr],
2380 ps_enc_ctxt->s_multi_thrd.apv_enc_thrd_sem_handle,
2381 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds);
2382 }
2383 /* --- Prev. frame EncLoop Done Dep Mngr for re-encode Frm-Frm Mem Init -- */
2384 ps_enc_ctxt->s_multi_thrd.pv_dep_mngr_prev_frame_enc_done_for_reenc = ihevce_dmgr_init(
2385 ps_memtab,
2386 ps_intrf_ctxt->pv_osal_handle,
2387 DEP_MNGR_FRM_FRM_SYNC,
2388 (a_ctb_align_ht[0] / ctb_size),
2389 (a_ctb_align_wd[0] / ctb_size),
2390 1, /* Number of Col Tiles : Don't care for FRM_FRM */
2391 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
2392 1 /*Sem Enabled*/
2393 );
2394 ps_memtab += ihevce_dmgr_get_num_mem_recs();
2395
2396 /* Register Enc group semaphore handles */
2397 ihevce_dmgr_reg_sem_hdls(
2398 ps_enc_ctxt->s_multi_thrd.pv_dep_mngr_prev_frame_enc_done_for_reenc,
2399 ps_enc_ctxt->s_multi_thrd.apv_enc_thrd_sem_handle,
2400 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds);
2401 for(ctr = 0; ctr < i4_num_me_frm_pllel; ctr++)
2402 {
2403 /* --- Prev. frame ME Done Dep Mngr Frm-Frm Mem Init -- */
2404 ps_enc_ctxt->s_multi_thrd.apv_dep_mngr_prev_frame_me_done[ctr] = ihevce_dmgr_init(
2405 ps_memtab,
2406 ps_intrf_ctxt->pv_osal_handle,
2407 DEP_MNGR_FRM_FRM_SYNC,
2408 (a_ctb_align_ht[0] / ctb_size),
2409 (a_ctb_align_wd[0] / ctb_size),
2410 1, /* Number of Col Tiles : Don't care for FRM_FRM */
2411 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
2412 1 /*Sem Enabled*/
2413 );
2414 ps_memtab += ihevce_dmgr_get_num_mem_recs();
2415
2416 /* Register Enc group semaphore handles */
2417 ihevce_dmgr_reg_sem_hdls(
2418 ps_enc_ctxt->s_multi_thrd.apv_dep_mngr_prev_frame_me_done[ctr],
2419 ps_enc_ctxt->s_multi_thrd.apv_enc_thrd_sem_handle,
2420 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds);
2421 }
2422 /* --- Prev. frame PreEnc L1 Done Dep Mngr Frm-Frm Mem Init -- */
2423 ps_enc_ctxt->s_multi_thrd.pv_dep_mngr_prev_frame_pre_enc_l1 = ihevce_dmgr_init(
2424 ps_memtab,
2425 ps_intrf_ctxt->pv_osal_handle,
2426 DEP_MNGR_FRM_FRM_SYNC,
2427 (a_ctb_align_ht[0] / ctb_size),
2428 (a_ctb_align_wd[0] / ctb_size),
2429 1, /* Number of Col Tiles : Don't care for FRM_FRM */
2430 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
2431 1 /*Sem Enabled*/
2432 );
2433 ps_memtab += ihevce_dmgr_get_num_mem_recs();
2434
2435 /* Register Pre-Enc group semaphore handles */
2436 ihevce_dmgr_reg_sem_hdls(
2437 ps_enc_ctxt->s_multi_thrd.pv_dep_mngr_prev_frame_pre_enc_l1,
2438 ps_enc_ctxt->s_multi_thrd.apv_pre_enc_thrd_sem_handle,
2439 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds);
2440
2441 /* --- Prev. frame PreEnc HME Done Dep Mngr Frm-Frm Mem Init -- */
2442 ps_enc_ctxt->s_multi_thrd.pv_dep_mngr_prev_frame_pre_enc_coarse_me = ihevce_dmgr_init(
2443 ps_memtab,
2444 ps_intrf_ctxt->pv_osal_handle,
2445 DEP_MNGR_FRM_FRM_SYNC,
2446 (a_ctb_align_ht[0] / ctb_size),
2447 (a_ctb_align_wd[0] / ctb_size),
2448 1, /* Number of Col Tiles : Don't care for FRM_FRM */
2449 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
2450 1 /*Sem Enabled*/
2451 );
2452 ps_memtab += ihevce_dmgr_get_num_mem_recs();
2453
2454 /* Register Pre-Enc group semaphore handles */
2455 ihevce_dmgr_reg_sem_hdls(
2456 ps_enc_ctxt->s_multi_thrd.pv_dep_mngr_prev_frame_pre_enc_coarse_me,
2457 ps_enc_ctxt->s_multi_thrd.apv_pre_enc_thrd_sem_handle,
2458 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds);
2459
2460 /* --- Prev. frame PreEnc L0 Done Dep Mngr Frm-Frm Mem Init -- */
2461 ps_enc_ctxt->s_multi_thrd.pv_dep_mngr_prev_frame_pre_enc_l0 = ihevce_dmgr_init(
2462 ps_memtab,
2463 ps_intrf_ctxt->pv_osal_handle,
2464 DEP_MNGR_FRM_FRM_SYNC,
2465 (a_ctb_align_ht[0] / ctb_size),
2466 (a_ctb_align_wd[0] / ctb_size),
2467 1, /* Number of Col Tiles : Don't care for FRM_FRM */
2468 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds,
2469 1 /*Sem Enabled*/
2470 );
2471 ps_memtab += ihevce_dmgr_get_num_mem_recs();
2472
2473 /* Register Pre-Enc group semaphore handles */
2474 ihevce_dmgr_reg_sem_hdls(
2475 ps_enc_ctxt->s_multi_thrd.pv_dep_mngr_prev_frame_pre_enc_l0,
2476 ps_enc_ctxt->s_multi_thrd.apv_pre_enc_thrd_sem_handle,
2477 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds);
2478
2479 /* --- ME-Prev Recon Dep Mngr Row-Frm Mem init -- */
2480 for(ctr = 0; ctr < (max_num_ref_pics + 1 + NUM_EXTRA_RECON_BUFS); ctr++)
2481 {
2482 WORD32 ai4_tile_xtra_ctb[4] = { 0 };
2483
2484 ps_enc_ctxt->pps_recon_buf_q[0][ctr]->pv_dep_mngr_recon = ihevce_dmgr_map_init(
2485 ps_memtab,
2486 num_ctb_vert,
2487 num_ctb_horz,
2488 i1_is_sem_enabled, /*Sem Disabled/Enabled*/
2489 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds,
2490 ai4_tile_xtra_ctb);
2491
2492 ps_memtab += ihevce_dmgr_get_num_mem_recs();
2493
2494 /* Register Enc group semaphore handles */
2495 ihevce_dmgr_reg_sem_hdls(
2496 ps_enc_ctxt->pps_recon_buf_q[0][ctr]->pv_dep_mngr_recon,
2497 ps_enc_ctxt->s_multi_thrd.apv_enc_thrd_sem_handle,
2498 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds);
2499 }
2500
2501 /* ------ Module level register semaphores -------- */
2502 ihevce_coarse_me_reg_thrds_sem(
2503 ps_enc_ctxt->s_module_ctxt.pv_coarse_me_ctxt,
2504 ps_enc_ctxt->s_multi_thrd.apv_pre_enc_thrd_sem_handle,
2505 ps_enc_ctxt->s_multi_thrd.i4_num_pre_enc_proc_thrds);
2506
2507 ihevce_enc_loop_reg_sem_hdls(
2508 ps_enc_ctxt->s_module_ctxt.pv_enc_loop_ctxt,
2509 ps_enc_ctxt->s_multi_thrd.apv_enc_thrd_sem_handle,
2510 ps_enc_ctxt->s_multi_thrd.i4_num_enc_proc_thrds);
2511 }
2512
2513 /* copy the run time source parameters from create time prms */
2514 memcpy(
2515 &ps_enc_ctxt->s_runtime_src_prms,
2516 &ps_enc_ctxt->ps_stat_prms->s_src_prms,
2517 sizeof(ihevce_src_params_t));
2518
2519 memcpy(
2520 &ps_enc_ctxt->s_runtime_tgt_params,
2521 &ps_enc_ctxt->ps_stat_prms->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id],
2522 sizeof(ihevce_tgt_params_t));
2523
2524 /* copy the run time coding parameters from create time prms */
2525 memcpy(
2526 &ps_enc_ctxt->s_runtime_coding_prms,
2527 &ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms,
2528 sizeof(ihevce_coding_params_t));
2529
2530 /*change in run time parameter*/
2531 if(ps_enc_ctxt->ps_stat_prms->s_coding_tools_prms.i4_max_reference_frames == -1)
2532 {
2533 ps_enc_ctxt->s_runtime_coding_prms.i4_max_reference_frames = (DEFAULT_MAX_REFERENCE_PICS)
2534 << i4_field_pic;
2535
2536 ps_enc_ctxt->s_lap_stat_prms.i4_max_reference_frames =
2537 ps_enc_ctxt->s_runtime_coding_prms.i4_max_reference_frames;
2538 }
2539
2540 /* populate the frame level ctb parameters based on run time params */
2541 ihevce_set_pre_enc_prms(ps_enc_ctxt);
2542
2543 return;
2544 }
2545
2546 /*!
2547 ******************************************************************************
2548 * \if Function name : ihevce_mem_manager_que_init \endif
2549 *
2550 * \brief
2551 * Encoder Que memory init function
2552 *
2553 * \param[in] Encoder context pointer
2554 * \param[in] High level Encoder context pointer
2555 * \param[in] Buffer descriptors
2556 *
2557 * \return
2558 * None
2559 *
2560 * \author
2561 * Ittiam
2562 *
2563 *****************************************************************************
2564 */
ihevce_mem_manager_que_init(enc_ctxt_t * ps_enc_ctxt,ihevce_hle_ctxt_t * ps_hle_ctxt,iv_input_data_ctrl_buffs_desc_t * ps_input_data_ctrl_buffs_desc,iv_input_asynch_ctrl_buffs_desc_t * ps_input_asynch_ctrl_buffs_desc,iv_output_data_buffs_desc_t * ps_output_data_buffs_desc,iv_recon_data_buffs_desc_t * ps_recon_data_buffs_desc)2565 void ihevce_mem_manager_que_init(
2566 enc_ctxt_t *ps_enc_ctxt,
2567 ihevce_hle_ctxt_t *ps_hle_ctxt,
2568 iv_input_data_ctrl_buffs_desc_t *ps_input_data_ctrl_buffs_desc,
2569 iv_input_asynch_ctrl_buffs_desc_t *ps_input_asynch_ctrl_buffs_desc,
2570 iv_output_data_buffs_desc_t *ps_output_data_buffs_desc,
2571 iv_recon_data_buffs_desc_t *ps_recon_data_buffs_desc)
2572 {
2573 /* local variables */
2574 WORD32 total_memtabs_req = 0;
2575 WORD32 total_memtabs_used = 0;
2576 WORD32 ctr;
2577 iv_mem_rec_t *ps_memtab;
2578 WORD32 i; //counter variable
2579 iv_output_data_buffs_desc_t *ps_out_desc;
2580 iv_recon_data_buffs_desc_t *ps_rec_desc;
2581 WORD32 i4_num_bitrate_inst; //number of bit-rate instance
2582 /* storing 0th instance's pointer. This will be used for assigning buffer queue handles for input/output queues */
2583 enc_ctxt_t *ps_enc_ctxt_base = (enc_ctxt_t *)ps_hle_ctxt->apv_enc_hdl[0];
2584
2585 i4_num_bitrate_inst = ps_enc_ctxt->i4_num_bitrates;
2586 //ps_hle_ctxt->ps_static_cfg_prms->s_tgt_lyr_prms.as_tgt_params[0].i4_num_bitrate_instances;
2587
2588 /* --------------------------------------------------------------------- */
2589 /* -------------- Collating the number of memtabs required ------------ */
2590 /* --------------------------------------------------------------------- */
2591
2592 /* ------ Input Data Que Memtab -------- */
2593 if(0 == ps_enc_ctxt->i4_resolution_id)
2594 {
2595 /* array of pointers for input */
2596 total_memtabs_req++;
2597
2598 /* pointers for input desc */
2599 total_memtabs_req++;
2600
2601 /* que manager buffer requirements */
2602 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
2603
2604 /* ------ Input Control Que memtab ----- */
2605 /* array of pointers for input control */
2606 total_memtabs_req++;
2607
2608 /* pointers for input control desc */
2609 total_memtabs_req++;
2610
2611 /* que manager buffer requirements */
2612 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
2613 }
2614
2615 /* ------ Output Data Que Memtab -------- */
2616 for(i = 0; i < i4_num_bitrate_inst; i++)
2617 {
2618 /* array of pointers for output */
2619 total_memtabs_req++;
2620
2621 /* pointers for output desc */
2622 total_memtabs_req++;
2623
2624 /* que manager buffer requirements */
2625 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
2626 }
2627
2628 /* ------ Recon Data Que Memtab -------- */
2629 for(i = 0; i < i4_num_bitrate_inst; i++)
2630 {
2631 if(ps_hle_ctxt->ps_static_cfg_prms->i4_save_recon)
2632 {
2633 /* array of pointers for input */
2634 total_memtabs_req++;
2635
2636 /* pointers for input desc */
2637 total_memtabs_req++;
2638
2639 /* que manager buffer requirements */
2640 total_memtabs_req += ihevce_buff_que_get_num_mem_recs();
2641 }
2642 }
2643
2644 /* ----- allocate memomry for memtabs --- */
2645 {
2646 iv_mem_rec_t s_memtab;
2647
2648 s_memtab.i4_size = sizeof(iv_mem_rec_t);
2649 s_memtab.i4_mem_size = total_memtabs_req * sizeof(iv_mem_rec_t);
2650 s_memtab.e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2651 s_memtab.i4_mem_alignment = 4;
2652
2653 ps_hle_ctxt->ihevce_mem_alloc(
2654 ps_hle_ctxt->pv_mem_mgr_hdl, &ps_hle_ctxt->ps_static_cfg_prms->s_sys_api, &s_memtab);
2655 if(s_memtab.pv_base == NULL)
2656 {
2657 ps_hle_ctxt->i4_error_code = IHEVCE_CANNOT_ALLOCATE_MEMORY;
2658 return;
2659 }
2660 ps_memtab = (iv_mem_rec_t *)s_memtab.pv_base;
2661 }
2662
2663 /* --------------------------------------------------------------------- */
2664 /* ------------------ Collating memory requirements ------------------- */
2665 /* --------------------------------------------------------------------- */
2666 if(0 == ps_enc_ctxt->i4_resolution_id)
2667 {
2668 /* ------ Input Data Que memory requests -------- */
2669 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
2670
2671 ps_memtab[total_memtabs_used].e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2672
2673 ps_memtab[total_memtabs_used].i4_mem_size =
2674 ((ps_input_data_ctrl_buffs_desc->i4_num_yuv_bufs) * (sizeof(ihevce_lap_enc_buf_t *)));
2675
2676 /* increment the memtab counter */
2677 total_memtabs_used++;
2678
2679 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
2680
2681 ps_memtab[total_memtabs_used].e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2682
2683 ps_memtab[total_memtabs_used].i4_mem_size =
2684 ((ps_input_data_ctrl_buffs_desc->i4_num_yuv_bufs) * (sizeof(ihevce_lap_enc_buf_t)));
2685
2686 /* increment the memtab counter */
2687 total_memtabs_used++;
2688
2689 /* call the Que manager get mem recs */
2690 total_memtabs_used += ihevce_buff_que_get_mem_recs(
2691 &ps_memtab[total_memtabs_used],
2692 ps_input_data_ctrl_buffs_desc->i4_num_yuv_bufs,
2693 IV_EXT_CACHEABLE_NORMAL_MEM);
2694
2695 /* ------ Input Control Que memory requests -------- */
2696 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
2697
2698 ps_memtab[total_memtabs_used].e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2699
2700 ps_memtab[total_memtabs_used].i4_mem_size =
2701 ((ps_input_asynch_ctrl_buffs_desc->i4_num_asynch_ctrl_bufs) *
2702 (sizeof(iv_input_ctrl_buffs_t *)));
2703
2704 /* increment the memtab counter */
2705 total_memtabs_used++;
2706
2707 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
2708
2709 ps_memtab[total_memtabs_used].e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2710
2711 ps_memtab[total_memtabs_used].i4_mem_size =
2712 ((ps_input_asynch_ctrl_buffs_desc->i4_num_asynch_ctrl_bufs) *
2713 (sizeof(iv_input_ctrl_buffs_t)));
2714
2715 /* increment the memtab counter */
2716 total_memtabs_used++;
2717
2718 /* call the Que manager get mem recs */
2719 total_memtabs_used += ihevce_buff_que_get_mem_recs(
2720 &ps_memtab[total_memtabs_used],
2721 ps_input_asynch_ctrl_buffs_desc->i4_num_asynch_ctrl_bufs,
2722 IV_EXT_CACHEABLE_NORMAL_MEM);
2723 }
2724
2725 /* ------ Output data Que memory requests -------- */
2726 ps_out_desc = ps_output_data_buffs_desc;
2727 for(i = 0; i < i4_num_bitrate_inst; i++)
2728 {
2729 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
2730
2731 ps_memtab[total_memtabs_used].e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2732
2733 ps_memtab[total_memtabs_used].i4_mem_size =
2734 ((ps_out_desc->i4_num_bitstream_bufs) * (sizeof(iv_output_data_buffs_t *)));
2735
2736 /* increment the memtab counter */
2737 total_memtabs_used++;
2738
2739 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
2740
2741 ps_memtab[total_memtabs_used].e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2742
2743 ps_memtab[total_memtabs_used].i4_mem_size =
2744 ((ps_out_desc->i4_num_bitstream_bufs) * (sizeof(iv_output_data_buffs_t)));
2745
2746 /* increment the memtab counter */
2747 total_memtabs_used++;
2748
2749 /* call the Que manager get mem recs */
2750 total_memtabs_used += ihevce_buff_que_get_mem_recs(
2751 &ps_memtab[total_memtabs_used],
2752 ps_out_desc->i4_num_bitstream_bufs,
2753 IV_EXT_CACHEABLE_NORMAL_MEM);
2754 ps_out_desc++;
2755 }
2756
2757 //recon_dump
2758 /* ------ Recon Data Que memory requests -------- */
2759 ps_rec_desc = ps_recon_data_buffs_desc;
2760 if(ps_hle_ctxt->ps_static_cfg_prms->i4_save_recon)
2761 {
2762 for(i = 0; i < i4_num_bitrate_inst; i++)
2763 {
2764 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
2765
2766 ps_memtab[total_memtabs_used].e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2767
2768 ps_memtab[total_memtabs_used].i4_mem_size =
2769 ((ps_rec_desc->i4_num_recon_bufs) * (sizeof(iv_enc_recon_data_buffs_t *)));
2770
2771 /* increment the memtab counter */
2772 total_memtabs_used++;
2773
2774 ps_memtab[total_memtabs_used].i4_mem_alignment = 8;
2775
2776 ps_memtab[total_memtabs_used].e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
2777
2778 ps_memtab[total_memtabs_used].i4_mem_size =
2779 ((ps_rec_desc->i4_num_recon_bufs) * (sizeof(iv_enc_recon_data_buffs_t)));
2780
2781 /* increment the memtab counter */
2782 total_memtabs_used++;
2783
2784 /* call the Que manager get mem recs */
2785 total_memtabs_used += ihevce_buff_que_get_mem_recs(
2786 &ps_memtab[total_memtabs_used],
2787 ps_rec_desc->i4_num_recon_bufs,
2788 IV_EXT_CACHEABLE_NORMAL_MEM);
2789
2790 ps_rec_desc++;
2791 }
2792 }
2793
2794 /* ----- allocate memory as per requests ---- */
2795
2796 /* check on memtabs requested v/s memtabs used */
2797 //ittiam : should put an assert
2798 ASSERT(total_memtabs_req == total_memtabs_used);
2799 for(ctr = 0; ctr < total_memtabs_used; ctr++)
2800 {
2801 UWORD8 *pu1_mem = NULL;
2802 ps_hle_ctxt->ihevce_mem_alloc(
2803 ps_hle_ctxt->pv_mem_mgr_hdl,
2804 &ps_hle_ctxt->ps_static_cfg_prms->s_sys_api,
2805 &ps_memtab[ctr]);
2806
2807 pu1_mem = (UWORD8 *)ps_memtab[ctr].pv_base;
2808
2809 if(NULL == pu1_mem)
2810 {
2811 ps_hle_ctxt->i4_error_code = IHEVCE_CANNOT_ALLOCATE_MEMORY;
2812 return;
2813 }
2814 }
2815
2816 /* store the final allocated memtabs */
2817 ps_enc_ctxt->s_mem_mngr.i4_num_q_memtabs = total_memtabs_used;
2818 ps_enc_ctxt->s_mem_mngr.ps_q_memtab = ps_memtab;
2819
2820 /* --------------------------------------------------------------------- */
2821 /* -------------- Initialisation of Queues memory ---------------------- */
2822 /* --------------------------------------------------------------------- */
2823
2824 /* ---------- Input Data Que Mem init --------------- */
2825 if(0 == ps_enc_ctxt->i4_resolution_id)
2826 {
2827 ihevce_lap_enc_buf_t **pps_inp_bufs;
2828 ihevce_lap_enc_buf_t *ps_inp_bufs;
2829
2830 pps_inp_bufs = (ihevce_lap_enc_buf_t **)ps_memtab->pv_base;
2831 ps_memtab++;
2832
2833 ps_inp_bufs = (ihevce_lap_enc_buf_t *)ps_memtab->pv_base;
2834 ps_memtab++;
2835
2836 /* loop to initialise the buffer pointer */
2837 for(ctr = 0; ctr < ps_input_data_ctrl_buffs_desc->i4_num_yuv_bufs; ctr++)
2838 {
2839 pps_inp_bufs[ctr] = &ps_inp_bufs[ctr];
2840
2841 pps_inp_bufs[ctr]->s_input_buf.i4_size = sizeof(iv_input_data_ctrl_buffs_t);
2842
2843 pps_inp_bufs[ctr]->s_input_buf.s_input_buf.i4_size = sizeof(iv_yuv_buf_t);
2844
2845 /*pointer to i/p buf initialised to null in case of run time allocation*/
2846 if(ps_hle_ctxt->i4_create_time_input_allocation == 1)
2847 {
2848 pps_inp_bufs[ctr]->s_input_buf.pv_synch_ctrl_bufs =
2849 ps_input_data_ctrl_buffs_desc->ppv_synch_ctrl_bufs[ctr];
2850
2851 pps_inp_bufs[ctr]->s_input_buf.s_input_buf.pv_y_buf =
2852 ps_input_data_ctrl_buffs_desc->ppv_y_buf[ctr];
2853
2854 pps_inp_bufs[ctr]->s_input_buf.s_input_buf.pv_u_buf =
2855 ps_input_data_ctrl_buffs_desc->ppv_u_buf[ctr];
2856
2857 pps_inp_bufs[ctr]->s_input_buf.s_input_buf.pv_v_buf =
2858 ps_input_data_ctrl_buffs_desc->ppv_v_buf[ctr];
2859 }
2860 else
2861 {
2862 pps_inp_bufs[ctr]->s_input_buf.pv_synch_ctrl_bufs = NULL;
2863
2864 pps_inp_bufs[ctr]->s_input_buf.s_input_buf.pv_y_buf = NULL;
2865
2866 pps_inp_bufs[ctr]->s_input_buf.s_input_buf.pv_u_buf = NULL;
2867
2868 pps_inp_bufs[ctr]->s_input_buf.s_input_buf.pv_v_buf = NULL;
2869 }
2870 }
2871
2872 /* Get the input data buffer Q handle */
2873 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_INPUT_DATA_CTRL_Q] = ihevce_buff_que_init(
2874 ps_memtab, ps_input_data_ctrl_buffs_desc->i4_num_yuv_bufs, (void **)pps_inp_bufs);
2875
2876 /* increment the memtab pointer */
2877 ps_memtab += ihevce_buff_que_get_num_mem_recs();
2878 }
2879 else
2880 {
2881 /* Get the input data buffer Q handle from 0th instance */
2882 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_INPUT_DATA_CTRL_Q] =
2883 ps_enc_ctxt_base->s_enc_ques.apv_q_hdl[IHEVCE_INPUT_DATA_CTRL_Q];
2884 }
2885
2886 /* ---------- Input control Que Mem init --------------- */
2887 if(0 == ps_enc_ctxt->i4_resolution_id)
2888 {
2889 iv_input_ctrl_buffs_t **pps_inp_bufs;
2890 iv_input_ctrl_buffs_t *ps_inp_bufs;
2891
2892 pps_inp_bufs = (iv_input_ctrl_buffs_t **)ps_memtab->pv_base;
2893 ps_memtab++;
2894
2895 ps_inp_bufs = (iv_input_ctrl_buffs_t *)ps_memtab->pv_base;
2896 ps_memtab++;
2897
2898 /* loop to initialise the buffer pointer */
2899 for(ctr = 0; ctr < ps_input_asynch_ctrl_buffs_desc->i4_num_asynch_ctrl_bufs; ctr++)
2900 {
2901 pps_inp_bufs[ctr] = &ps_inp_bufs[ctr];
2902
2903 pps_inp_bufs[ctr]->i4_size = sizeof(iv_input_ctrl_buffs_t);
2904
2905 pps_inp_bufs[ctr]->pv_asynch_ctrl_bufs =
2906 ps_input_asynch_ctrl_buffs_desc->ppv_asynch_ctrl_bufs[ctr];
2907 }
2908
2909 /* Get the input control buffer Q handle */
2910 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_INPUT_ASYNCH_CTRL_Q] = ihevce_buff_que_init(
2911 ps_memtab,
2912 ps_input_asynch_ctrl_buffs_desc->i4_num_asynch_ctrl_bufs,
2913 (void **)pps_inp_bufs);
2914
2915 /* increment the memtab pointer */
2916 ps_memtab += ihevce_buff_que_get_num_mem_recs();
2917 }
2918 else
2919 {
2920 /* Get the input control buffer Q handle from 0th instance */
2921 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_INPUT_ASYNCH_CTRL_Q] =
2922 ps_enc_ctxt_base->s_enc_ques.apv_q_hdl[IHEVCE_INPUT_ASYNCH_CTRL_Q];
2923 }
2924
2925 /* ---------- Output data Que Mem init --------------- */
2926 ps_out_desc = ps_output_data_buffs_desc;
2927 for(i = 0; i < i4_num_bitrate_inst; i++)
2928 {
2929 iv_output_data_buffs_t **pps_out_bufs;
2930 iv_output_data_buffs_t *ps_out_bufs;
2931
2932 pps_out_bufs = (iv_output_data_buffs_t **)ps_memtab->pv_base;
2933 ps_memtab++;
2934
2935 ps_out_bufs = (iv_output_data_buffs_t *)ps_memtab->pv_base;
2936 ps_memtab++;
2937
2938 /* loop to initialise the buffer pointer */
2939 for(ctr = 0; ctr < ps_out_desc->i4_num_bitstream_bufs; ctr++)
2940 {
2941 pps_out_bufs[ctr] = &ps_out_bufs[ctr];
2942
2943 pps_out_bufs[ctr]->i4_size = sizeof(iv_output_data_buffs_t);
2944
2945 pps_out_bufs[ctr]->i4_bitstream_buf_size = ps_out_desc->i4_size_bitstream_buf;
2946
2947 /*pointer to o/p buf initialised to null in case of run time allocation*/
2948 if(ps_hle_ctxt->i4_create_time_output_allocation == 1)
2949 {
2950 pps_out_bufs[ctr]->pv_bitstream_bufs = ps_out_desc->ppv_bitstream_bufs[ctr];
2951 }
2952 else
2953 {
2954 pps_out_bufs[ctr]->pv_bitstream_bufs = NULL;
2955 }
2956 }
2957
2958 /* Get the output data buffer Q handle */
2959 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_OUTPUT_DATA_Q + i] = ihevce_buff_que_init(
2960 ps_memtab, ps_out_desc->i4_num_bitstream_bufs, (void **)pps_out_bufs);
2961
2962 /* increment the memtab pointer */
2963 ps_memtab += ihevce_buff_que_get_num_mem_recs();
2964
2965 ps_out_desc++;
2966 }
2967
2968 /* ----------Recon data Que Mem init --------------- */
2969 ps_rec_desc = ps_recon_data_buffs_desc;
2970 for(i = 0; i < i4_num_bitrate_inst; i++)
2971 {
2972 if(ps_hle_ctxt->ps_static_cfg_prms->i4_save_recon)
2973 {
2974 iv_enc_recon_data_buffs_t **pps_recon_bufs;
2975 iv_enc_recon_data_buffs_t *ps_recon_bufs;
2976
2977 pps_recon_bufs = (iv_enc_recon_data_buffs_t **)ps_memtab->pv_base;
2978 ps_memtab++;
2979
2980 ps_recon_bufs = (iv_enc_recon_data_buffs_t *)ps_memtab->pv_base;
2981 ps_memtab++;
2982
2983 /* loop to initialise the buffer pointer */
2984 for(ctr = 0; ctr < ps_rec_desc->i4_num_recon_bufs; ctr++)
2985 {
2986 pps_recon_bufs[ctr] = &ps_recon_bufs[ctr];
2987
2988 pps_recon_bufs[ctr]->i4_size = sizeof(iv_enc_recon_data_buffs_t);
2989
2990 pps_recon_bufs[ctr]->pv_y_buf = ps_rec_desc->ppv_y_buf[ctr];
2991
2992 pps_recon_bufs[ctr]->pv_cb_buf = ps_rec_desc->ppv_u_buf[ctr];
2993
2994 pps_recon_bufs[ctr]->pv_cr_buf = ps_rec_desc->ppv_v_buf[ctr];
2995 }
2996
2997 /* Get the output data buffer Q handle */
2998 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_RECON_DATA_Q + i] = ihevce_buff_que_init(
2999 ps_memtab, ps_rec_desc->i4_num_recon_bufs, (void **)pps_recon_bufs);
3000
3001 /* increment the memtab pointer */
3002 ps_memtab += ihevce_buff_que_get_num_mem_recs();
3003
3004 ps_rec_desc++;
3005 }
3006 else
3007 {
3008 ps_enc_ctxt->s_enc_ques.apv_q_hdl[IHEVCE_RECON_DATA_Q + i] = NULL;
3009 }
3010 }
3011
3012 return;
3013 }
3014
3015 /*!
3016 ******************************************************************************
3017 * \if Function name : ihevce_mem_manager_free \endif
3018 *
3019 * \brief
3020 * Encoder memory free function
3021 *
3022 * \param[in] Processing interface context pointer
3023 *
3024 * \return
3025 * None
3026 *
3027 * \author
3028 * Ittiam
3029 *
3030 *****************************************************************************
3031 */
ihevce_mem_manager_free(enc_ctxt_t * ps_enc_ctxt,ihevce_hle_ctxt_t * ps_intrf_ctxt)3032 void ihevce_mem_manager_free(enc_ctxt_t *ps_enc_ctxt, ihevce_hle_ctxt_t *ps_intrf_ctxt)
3033 {
3034 WORD32 ctr;
3035
3036 /* run a loop to free all the memory allocated create time */
3037 for(ctr = 0; ctr < ps_enc_ctxt->s_mem_mngr.i4_num_create_memtabs; ctr++)
3038 {
3039 ps_intrf_ctxt->ihevce_mem_free(
3040 ps_intrf_ctxt->pv_mem_mgr_hdl, &ps_enc_ctxt->s_mem_mngr.ps_create_memtab[ctr]);
3041 }
3042
3043 /* free the memtab memory */
3044 {
3045 iv_mem_rec_t s_memtab;
3046
3047 s_memtab.i4_size = sizeof(iv_mem_rec_t);
3048 s_memtab.i4_mem_size = ps_enc_ctxt->s_mem_mngr.i4_num_create_memtabs * sizeof(iv_mem_rec_t);
3049 s_memtab.e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
3050 s_memtab.i4_mem_alignment = 4;
3051 s_memtab.pv_base = (void *)ps_enc_ctxt->s_mem_mngr.ps_create_memtab;
3052
3053 ps_intrf_ctxt->ihevce_mem_free(ps_intrf_ctxt->pv_mem_mgr_hdl, &s_memtab);
3054 }
3055
3056 if(1 == ps_enc_ctxt->i4_io_queues_created)
3057 {
3058 /* run a loop to free all the memory allocated durign que creation */
3059 for(ctr = 0; ctr < ps_enc_ctxt->s_mem_mngr.i4_num_q_memtabs; ctr++)
3060 {
3061 ps_intrf_ctxt->ihevce_mem_free(
3062 ps_intrf_ctxt->pv_mem_mgr_hdl, &ps_enc_ctxt->s_mem_mngr.ps_q_memtab[ctr]);
3063 }
3064
3065 /* free the memtab memory */
3066 {
3067 iv_mem_rec_t s_memtab;
3068
3069 s_memtab.i4_size = sizeof(iv_mem_rec_t);
3070 s_memtab.i4_mem_size = ps_enc_ctxt->s_mem_mngr.i4_num_q_memtabs * sizeof(iv_mem_rec_t);
3071 s_memtab.e_mem_type = IV_EXT_CACHEABLE_NORMAL_MEM;
3072 s_memtab.i4_mem_alignment = 4;
3073 s_memtab.pv_base = (void *)ps_enc_ctxt->s_mem_mngr.ps_q_memtab;
3074
3075 ps_intrf_ctxt->ihevce_mem_free(ps_intrf_ctxt->pv_mem_mgr_hdl, &s_memtab);
3076 }
3077 }
3078 return;
3079 }
3080