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1 /*
2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * on the rights to use, copy, modify, merge, publish, distribute, sub
8  * license, and/or sell copies of the Software, and to permit persons to whom
9  * the Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Jerome Glisse
25  */
26 #include "r600_pipe.h"
27 #include "r600d.h"
28 #include "util/u_memory.h"
29 #include <errno.h>
30 #include <unistd.h>
31 
32 
r600_need_cs_space(struct r600_context * ctx,unsigned num_dw,boolean count_draw_in)33 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
34 			boolean count_draw_in)
35 {
36 	/* Flush the DMA IB if it's not empty. */
37 	if (radeon_emitted(ctx->b.dma.cs, 0))
38 		ctx->b.dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
39 
40 	if (!radeon_cs_memory_below_limit(ctx->b.screen, ctx->b.gfx.cs,
41 					  ctx->b.vram, ctx->b.gtt)) {
42 		ctx->b.gtt = 0;
43 		ctx->b.vram = 0;
44 		ctx->b.gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
45 		return;
46 	}
47 	/* all will be accounted once relocation are emited */
48 	ctx->b.gtt = 0;
49 	ctx->b.vram = 0;
50 
51 	/* Check available space in CS. */
52 	if (count_draw_in) {
53 		uint64_t mask;
54 
55 		/* The number of dwords all the dirty states would take. */
56 		mask = ctx->dirty_atoms;
57 		while (mask != 0)
58 			num_dw += ctx->atoms[u_bit_scan64(&mask)]->num_dw;
59 
60 		/* The upper-bound of how much space a draw command would take. */
61 		num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
62 	}
63 
64 	/* Count in r600_suspend_queries. */
65 	num_dw += ctx->b.num_cs_dw_queries_suspend;
66 
67 	/* Count in streamout_end at the end of CS. */
68 	if (ctx->b.streamout.begin_emitted) {
69 		num_dw += ctx->b.streamout.num_dw_for_end;
70 	}
71 
72 	/* SX_MISC */
73 	if (ctx->b.chip_class == R600) {
74 		num_dw += 3;
75 	}
76 
77 	/* Count in framebuffer cache flushes at the end of CS. */
78 	num_dw += R600_MAX_FLUSH_CS_DWORDS;
79 
80 	/* The fence at the end of CS. */
81 	num_dw += 10;
82 
83 	/* Flush if there's not enough space. */
84 	if (!ctx->b.ws->cs_check_space(ctx->b.gfx.cs, num_dw)) {
85 		ctx->b.gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
86 	}
87 }
88 
r600_flush_emit(struct r600_context * rctx)89 void r600_flush_emit(struct r600_context *rctx)
90 {
91 	struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
92 	unsigned cp_coher_cntl = 0;
93 	unsigned wait_until = 0;
94 
95 	if (!rctx->b.flags) {
96 		return;
97 	}
98 
99 	/* Ensure coherency between streamout and shaders. */
100 	if (rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH)
101 		rctx->b.flags |= r600_get_flush_flags(R600_COHERENCY_SHADER);
102 
103 	if (rctx->b.flags & R600_CONTEXT_WAIT_3D_IDLE) {
104 		wait_until |= S_008040_WAIT_3D_IDLE(1);
105 	}
106 	if (rctx->b.flags & R600_CONTEXT_WAIT_CP_DMA_IDLE) {
107 		wait_until |= S_008040_WAIT_CP_DMA_IDLE(1);
108 	}
109 
110 	if (wait_until) {
111 		/* Use of WAIT_UNTIL is deprecated on Cayman+ */
112 		if (rctx->b.family >= CHIP_CAYMAN) {
113 			/* emit a PS partial flush on Cayman/TN */
114 			rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
115 		}
116 	}
117 
118 	/* Wait packets must be executed first, because SURFACE_SYNC doesn't
119 	 * wait for shaders if it's not flushing CB or DB.
120 	 */
121 	if (rctx->b.flags & R600_CONTEXT_PS_PARTIAL_FLUSH) {
122 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
123 		radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
124 	}
125 
126 	if (wait_until) {
127 		/* Use of WAIT_UNTIL is deprecated on Cayman+ */
128 		if (rctx->b.family < CHIP_CAYMAN) {
129 			/* wait for things to settle */
130 			radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, wait_until);
131 		}
132 	}
133 
134 	if (rctx->b.chip_class >= R700 &&
135 	    (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
136 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
137 		radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
138 	}
139 
140 	if (rctx->b.chip_class >= R700 &&
141 	    (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_DB_META)) {
142 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
143 		radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
144 
145 		/* Set FULL_CACHE_ENA for DB META flushes on r7xx and later.
146 		 *
147 		 * This hack predates use of FLUSH_AND_INV_DB_META, so it's
148 		 * unclear whether it's still needed or even whether it has
149 		 * any effect.
150 		 */
151 		cp_coher_cntl |= S_0085F0_FULL_CACHE_ENA(1);
152 	}
153 
154 	if (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV ||
155 	    (rctx->b.chip_class == R600 && rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH)) {
156 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
157 		radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
158 	}
159 
160 	if (rctx->b.flags & R600_CONTEXT_INV_CONST_CACHE) {
161 		/* Direct constant addressing uses the shader cache.
162 		 * Indirect contant addressing uses the vertex cache. */
163 		cp_coher_cntl |= S_0085F0_SH_ACTION_ENA(1) |
164 				 (rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1)
165 							 : S_0085F0_TC_ACTION_ENA(1));
166 	}
167 	if (rctx->b.flags & R600_CONTEXT_INV_VERTEX_CACHE) {
168 		cp_coher_cntl |= rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1)
169 							: S_0085F0_TC_ACTION_ENA(1);
170 	}
171 	if (rctx->b.flags & R600_CONTEXT_INV_TEX_CACHE) {
172 		/* Textures use the texture cache.
173 		 * Texture buffer objects use the vertex cache. */
174 		cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
175 				 (rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1) : 0);
176 	}
177 
178 	/* Don't use the DB CP COHER logic on r6xx.
179 	 * There are hw bugs.
180 	 */
181 	if (rctx->b.chip_class >= R700 &&
182 	    (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_DB)) {
183 		cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
184 				S_0085F0_DB_DEST_BASE_ENA(1) |
185 				S_0085F0_SMX_ACTION_ENA(1);
186 	}
187 
188 	/* Don't use the CB CP COHER logic on r6xx.
189 	 * There are hw bugs.
190 	 */
191 	if (rctx->b.chip_class >= R700 &&
192 	    (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV_CB)) {
193 		cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
194 				S_0085F0_CB0_DEST_BASE_ENA(1) |
195 				S_0085F0_CB1_DEST_BASE_ENA(1) |
196 				S_0085F0_CB2_DEST_BASE_ENA(1) |
197 				S_0085F0_CB3_DEST_BASE_ENA(1) |
198 				S_0085F0_CB4_DEST_BASE_ENA(1) |
199 				S_0085F0_CB5_DEST_BASE_ENA(1) |
200 				S_0085F0_CB6_DEST_BASE_ENA(1) |
201 				S_0085F0_CB7_DEST_BASE_ENA(1) |
202 				S_0085F0_SMX_ACTION_ENA(1);
203 		if (rctx->b.chip_class >= EVERGREEN)
204 			cp_coher_cntl |= S_0085F0_CB8_DEST_BASE_ENA(1) |
205 					S_0085F0_CB9_DEST_BASE_ENA(1) |
206 					S_0085F0_CB10_DEST_BASE_ENA(1) |
207 					S_0085F0_CB11_DEST_BASE_ENA(1);
208 	}
209 
210 	if (rctx->b.chip_class >= R700 &&
211 	    rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH) {
212 		cp_coher_cntl |= S_0085F0_SO0_DEST_BASE_ENA(1) |
213 				S_0085F0_SO1_DEST_BASE_ENA(1) |
214 				S_0085F0_SO2_DEST_BASE_ENA(1) |
215 				S_0085F0_SO3_DEST_BASE_ENA(1) |
216 				S_0085F0_SMX_ACTION_ENA(1);
217 	}
218 
219 	/* Workaround for buggy flushing on some R6xx chipsets. */
220 	if ((rctx->b.flags & (R600_CONTEXT_FLUSH_AND_INV |
221 			      R600_CONTEXT_STREAMOUT_FLUSH)) &&
222 	    (rctx->b.family == CHIP_RV670 ||
223 	     rctx->b.family == CHIP_RS780 ||
224 	     rctx->b.family == CHIP_RS880)) {
225 		cp_coher_cntl |=  S_0085F0_CB1_DEST_BASE_ENA(1) |
226 				  S_0085F0_DEST_BASE_0_ENA(1);
227 	}
228 
229 	if (cp_coher_cntl) {
230 		radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
231 		radeon_emit(cs, cp_coher_cntl);   /* CP_COHER_CNTL */
232 		radeon_emit(cs, 0xffffffff);      /* CP_COHER_SIZE */
233 		radeon_emit(cs, 0);               /* CP_COHER_BASE */
234 		radeon_emit(cs, 0x0000000A);      /* POLL_INTERVAL */
235 	}
236 
237 	if (rctx->b.flags & R600_CONTEXT_START_PIPELINE_STATS) {
238 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
239 		radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) |
240 			        EVENT_INDEX(0));
241 	} else if (rctx->b.flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
242 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
243 		radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_STOP) |
244 			        EVENT_INDEX(0));
245 	}
246 
247 	/* everything is properly flushed */
248 	rctx->b.flags = 0;
249 }
250 
r600_context_gfx_flush(void * context,unsigned flags,struct pipe_fence_handle ** fence)251 void r600_context_gfx_flush(void *context, unsigned flags,
252 			    struct pipe_fence_handle **fence)
253 {
254 	struct r600_context *ctx = context;
255 	struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
256 	struct radeon_winsys *ws = ctx->b.ws;
257 
258 	if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size))
259 		return;
260 
261 	if (r600_check_device_reset(&ctx->b))
262 		return;
263 
264 	r600_preflush_suspend_features(&ctx->b);
265 
266 	/* flush the framebuffer cache */
267 	ctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV |
268 		      R600_CONTEXT_FLUSH_AND_INV_CB |
269 		      R600_CONTEXT_FLUSH_AND_INV_DB |
270 		      R600_CONTEXT_FLUSH_AND_INV_CB_META |
271 		      R600_CONTEXT_FLUSH_AND_INV_DB_META |
272 		      R600_CONTEXT_WAIT_3D_IDLE |
273 		      R600_CONTEXT_WAIT_CP_DMA_IDLE;
274 
275 	r600_flush_emit(ctx);
276 
277 	if (ctx->trace_buf)
278 		eg_trace_emit(ctx);
279 	/* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
280 	if (ctx->b.chip_class == R600) {
281 		radeon_set_context_reg(cs, R_028350_SX_MISC, 0);
282 	}
283 
284 	if (ctx->is_debug) {
285 		/* Save the IB for debug contexts. */
286 		radeon_clear_saved_cs(&ctx->last_gfx);
287 		radeon_save_cs(ws, cs, &ctx->last_gfx, true);
288 		r600_resource_reference(&ctx->last_trace_buf, ctx->trace_buf);
289 		r600_resource_reference(&ctx->trace_buf, NULL);
290 	}
291 	/* Flush the CS. */
292 	ws->cs_flush(cs, flags, &ctx->b.last_gfx_fence);
293 	if (fence)
294 		ws->fence_reference(fence, ctx->b.last_gfx_fence);
295 	ctx->b.num_gfx_cs_flushes++;
296 
297 	if (ctx->is_debug) {
298 		if (!ws->fence_wait(ws, ctx->b.last_gfx_fence, 10000000)) {
299 			const char *fname = getenv("R600_TRACE");
300 			if (!fname)
301 				exit(-1);
302 			FILE *fl = fopen(fname, "w+");
303 			if (fl) {
304 				eg_dump_debug_state(&ctx->b.b, fl, 0);
305 				fclose(fl);
306 			} else
307 				perror(fname);
308 			exit(-1);
309 		}
310 	}
311 	r600_begin_new_cs(ctx);
312 }
313 
r600_begin_new_cs(struct r600_context * ctx)314 void r600_begin_new_cs(struct r600_context *ctx)
315 {
316 	unsigned shader;
317 
318 	if (ctx->is_debug) {
319 		uint32_t zero = 0;
320 
321 		/* Create a buffer used for writing trace IDs and initialize it to 0. */
322 		assert(!ctx->trace_buf);
323 		ctx->trace_buf = (struct r600_resource*)
324 			pipe_buffer_create(ctx->b.b.screen, 0,
325 					   PIPE_USAGE_STAGING, 4);
326 		if (ctx->trace_buf)
327 			pipe_buffer_write_nooverlap(&ctx->b.b, &ctx->trace_buf->b.b,
328 						    0, sizeof(zero), &zero);
329 		ctx->trace_id = 0;
330 	}
331 
332 	if (ctx->trace_buf)
333 		eg_trace_emit(ctx);
334 
335 	ctx->b.flags = 0;
336 	ctx->b.gtt = 0;
337 	ctx->b.vram = 0;
338 
339 	/* Begin a new CS. */
340 	r600_emit_command_buffer(ctx->b.gfx.cs, &ctx->start_cs_cmd);
341 
342 	/* Re-emit states. */
343 	r600_mark_atom_dirty(ctx, &ctx->alphatest_state.atom);
344 	r600_mark_atom_dirty(ctx, &ctx->blend_color.atom);
345 	r600_mark_atom_dirty(ctx, &ctx->cb_misc_state.atom);
346 	r600_mark_atom_dirty(ctx, &ctx->clip_misc_state.atom);
347 	r600_mark_atom_dirty(ctx, &ctx->clip_state.atom);
348 	r600_mark_atom_dirty(ctx, &ctx->db_misc_state.atom);
349 	r600_mark_atom_dirty(ctx, &ctx->db_state.atom);
350 	r600_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
351 	if (ctx->b.chip_class >= EVERGREEN) {
352 		r600_mark_atom_dirty(ctx, &ctx->fragment_images.atom);
353 		r600_mark_atom_dirty(ctx, &ctx->fragment_buffers.atom);
354 		r600_mark_atom_dirty(ctx, &ctx->compute_images.atom);
355 		r600_mark_atom_dirty(ctx, &ctx->compute_buffers.atom);
356 	}
357 	r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[R600_HW_STAGE_PS].atom);
358 	r600_mark_atom_dirty(ctx, &ctx->poly_offset_state.atom);
359 	r600_mark_atom_dirty(ctx, &ctx->vgt_state.atom);
360 	r600_mark_atom_dirty(ctx, &ctx->sample_mask.atom);
361 	ctx->b.scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
362 	r600_mark_atom_dirty(ctx, &ctx->b.scissors.atom);
363 	ctx->b.viewports.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
364 	ctx->b.viewports.depth_range_dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
365 	r600_mark_atom_dirty(ctx, &ctx->b.viewports.atom);
366 	if (ctx->b.chip_class <= EVERGREEN) {
367 		r600_mark_atom_dirty(ctx, &ctx->config_state.atom);
368 	}
369 	r600_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
370 	r600_mark_atom_dirty(ctx, &ctx->vertex_fetch_shader.atom);
371 	r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[R600_HW_STAGE_ES].atom);
372 	r600_mark_atom_dirty(ctx, &ctx->shader_stages.atom);
373 	if (ctx->gs_shader) {
374 		r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[R600_HW_STAGE_GS].atom);
375 		r600_mark_atom_dirty(ctx, &ctx->gs_rings.atom);
376 	}
377 	if (ctx->tes_shader) {
378 		r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[EG_HW_STAGE_HS].atom);
379 		r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[EG_HW_STAGE_LS].atom);
380 	}
381 	r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[R600_HW_STAGE_VS].atom);
382 	r600_mark_atom_dirty(ctx, &ctx->b.streamout.enable_atom);
383 	r600_mark_atom_dirty(ctx, &ctx->b.render_cond_atom);
384 
385 	if (ctx->blend_state.cso)
386 		r600_mark_atom_dirty(ctx, &ctx->blend_state.atom);
387 	if (ctx->dsa_state.cso)
388 		r600_mark_atom_dirty(ctx, &ctx->dsa_state.atom);
389 	if (ctx->rasterizer_state.cso)
390 		r600_mark_atom_dirty(ctx, &ctx->rasterizer_state.atom);
391 
392 	if (ctx->b.chip_class <= R700) {
393 		r600_mark_atom_dirty(ctx, &ctx->seamless_cube_map.atom);
394 	}
395 
396 	ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
397 	r600_vertex_buffers_dirty(ctx);
398 
399 	/* Re-emit shader resources. */
400 	for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
401 		struct r600_constbuf_state *constbuf = &ctx->constbuf_state[shader];
402 		struct r600_textures_info *samplers = &ctx->samplers[shader];
403 
404 		constbuf->dirty_mask = constbuf->enabled_mask;
405 		samplers->views.dirty_mask = samplers->views.enabled_mask;
406 		samplers->states.dirty_mask = samplers->states.enabled_mask;
407 
408 		r600_constant_buffers_dirty(ctx, constbuf);
409 		r600_sampler_views_dirty(ctx, &samplers->views);
410 		r600_sampler_states_dirty(ctx, &samplers->states);
411 	}
412 
413 	r600_postflush_resume_features(&ctx->b);
414 
415 	/* Re-emit the draw state. */
416 	ctx->last_primitive_type = -1;
417 	ctx->last_start_instance = -1;
418 	ctx->last_rast_prim      = -1;
419 	ctx->current_rast_prim   = -1;
420 
421 	assert(!ctx->b.gfx.cs->prev_dw);
422 	ctx->b.initial_gfx_cs_size = ctx->b.gfx.cs->current.cdw;
423 }
424 
r600_emit_pfp_sync_me(struct r600_context * rctx)425 void r600_emit_pfp_sync_me(struct r600_context *rctx)
426 {
427 	struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
428 
429 	if (rctx->b.chip_class >= EVERGREEN &&
430 	    rctx->b.screen->info.drm_minor >= 46) {
431 		radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
432 		radeon_emit(cs, 0);
433 	} else {
434 		/* Emulate PFP_SYNC_ME by writing a value to memory in ME and
435 		 * waiting for it in PFP.
436 		 */
437 		struct r600_resource *buf = NULL;
438 		unsigned offset, reloc;
439 		uint64_t va;
440 
441 		/* 16-byte address alignment is required by WAIT_REG_MEM. */
442 		u_suballocator_alloc(rctx->b.allocator_zeroed_memory, 4, 16,
443 				     &offset, (struct pipe_resource**)&buf);
444 		if (!buf) {
445 			/* This is too heavyweight, but will work. */
446 			rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
447 			return;
448 		}
449 
450 		reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, buf,
451 						  RADEON_USAGE_READWRITE,
452 						  RADEON_PRIO_FENCE);
453 
454 		va = buf->gpu_address + offset;
455 		assert(va % 16 == 0);
456 
457 		/* Write 1 to memory in ME. */
458 		radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
459 		radeon_emit(cs, va);
460 		radeon_emit(cs, ((va >> 32) & 0xff) | MEM_WRITE_32_BITS);
461 		radeon_emit(cs, 1);
462 		radeon_emit(cs, 0);
463 
464 		radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
465 		radeon_emit(cs, reloc);
466 
467 		/* Wait in PFP (PFP can only do GEQUAL against memory). */
468 		radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
469 		radeon_emit(cs, WAIT_REG_MEM_GEQUAL |
470 			        WAIT_REG_MEM_MEMORY |
471 			        WAIT_REG_MEM_PFP);
472 		radeon_emit(cs, va);
473 		radeon_emit(cs, va >> 32);
474 		radeon_emit(cs, 1); /* reference value */
475 		radeon_emit(cs, 0xffffffff); /* mask */
476 		radeon_emit(cs, 4); /* poll interval */
477 
478 		radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
479 		radeon_emit(cs, reloc);
480 
481 		r600_resource_reference(&buf, NULL);
482 	}
483 }
484 
485 /* The max number of bytes to copy per packet. */
486 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
487 
r600_cp_dma_copy_buffer(struct r600_context * rctx,struct pipe_resource * dst,uint64_t dst_offset,struct pipe_resource * src,uint64_t src_offset,unsigned size)488 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
489 			     struct pipe_resource *dst, uint64_t dst_offset,
490 			     struct pipe_resource *src, uint64_t src_offset,
491 			     unsigned size)
492 {
493 	struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
494 
495 	assert(size);
496 	assert(rctx->screen->b.has_cp_dma);
497 
498 	/* Mark the buffer range of destination as valid (initialized),
499 	 * so that transfer_map knows it should wait for the GPU when mapping
500 	 * that range. */
501 	util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
502 		       dst_offset + size);
503 
504 	dst_offset += r600_resource(dst)->gpu_address;
505 	src_offset += r600_resource(src)->gpu_address;
506 
507 	/* Flush the caches where the resources are bound. */
508 	rctx->b.flags |= r600_get_flush_flags(R600_COHERENCY_SHADER) |
509 			 R600_CONTEXT_WAIT_3D_IDLE;
510 
511 	/* There are differences between R700 and EG in CP DMA,
512 	 * but we only use the common bits here. */
513 	while (size) {
514 		unsigned sync = 0;
515 		unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
516 		unsigned src_reloc, dst_reloc;
517 
518 		r600_need_cs_space(rctx,
519 				   10 + (rctx->b.flags ? R600_MAX_FLUSH_CS_DWORDS : 0) +
520 				   3 + R600_MAX_PFP_SYNC_ME_DWORDS, FALSE);
521 
522 		/* Flush the caches for the first copy only. */
523 		if (rctx->b.flags) {
524 			r600_flush_emit(rctx);
525 		}
526 
527 		/* Do the synchronization after the last copy, so that all data is written to memory. */
528 		if (size == byte_count) {
529 			sync = PKT3_CP_DMA_CP_SYNC;
530 		}
531 
532 		/* This must be done after r600_need_cs_space. */
533 		src_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, (struct r600_resource*)src,
534 						  RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
535 		dst_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, (struct r600_resource*)dst,
536 						  RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
537 
538 		radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
539 		radeon_emit(cs, src_offset);	/* SRC_ADDR_LO [31:0] */
540 		radeon_emit(cs, sync | ((src_offset >> 32) & 0xff));		/* CP_SYNC [31] | SRC_ADDR_HI [7:0] */
541 		radeon_emit(cs, dst_offset);	/* DST_ADDR_LO [31:0] */
542 		radeon_emit(cs, (dst_offset >> 32) & 0xff);		/* DST_ADDR_HI [7:0] */
543 		radeon_emit(cs, byte_count);	/* COMMAND [29:22] | BYTE_COUNT [20:0] */
544 
545 		radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
546 		radeon_emit(cs, src_reloc);
547 		radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
548 		radeon_emit(cs, dst_reloc);
549 
550 		size -= byte_count;
551 		src_offset += byte_count;
552 		dst_offset += byte_count;
553 	}
554 
555 	/* CP_DMA_CP_SYNC doesn't wait for idle on R6xx, but this does. */
556 	if (rctx->b.chip_class == R600)
557 		radeon_set_config_reg(cs, R_008040_WAIT_UNTIL,
558 				      S_008040_WAIT_CP_DMA_IDLE(1));
559 
560 	/* CP DMA is executed in ME, but index buffers are read by PFP.
561 	 * This ensures that ME (CP DMA) is idle before PFP starts fetching
562 	 * indices. If we wanted to execute CP DMA in PFP, this packet
563 	 * should precede it.
564 	 */
565 	r600_emit_pfp_sync_me(rctx);
566 }
567 
r600_dma_copy_buffer(struct r600_context * rctx,struct pipe_resource * dst,struct pipe_resource * src,uint64_t dst_offset,uint64_t src_offset,uint64_t size)568 void r600_dma_copy_buffer(struct r600_context *rctx,
569 			  struct pipe_resource *dst,
570 			  struct pipe_resource *src,
571 			  uint64_t dst_offset,
572 			  uint64_t src_offset,
573 			  uint64_t size)
574 {
575 	struct radeon_winsys_cs *cs = rctx->b.dma.cs;
576 	unsigned i, ncopy, csize;
577 	struct r600_resource *rdst = (struct r600_resource*)dst;
578 	struct r600_resource *rsrc = (struct r600_resource*)src;
579 
580 	/* Mark the buffer range of destination as valid (initialized),
581 	 * so that transfer_map knows it should wait for the GPU when mapping
582 	 * that range. */
583 	util_range_add(&rdst->valid_buffer_range, dst_offset,
584 		       dst_offset + size);
585 
586 	size >>= 2; /* convert to dwords */
587 	ncopy = (size / R600_DMA_COPY_MAX_SIZE_DW) + !!(size % R600_DMA_COPY_MAX_SIZE_DW);
588 
589 	r600_need_dma_space(&rctx->b, ncopy * 5, rdst, rsrc);
590 	for (i = 0; i < ncopy; i++) {
591 		csize = size < R600_DMA_COPY_MAX_SIZE_DW ? size : R600_DMA_COPY_MAX_SIZE_DW;
592 		/* emit reloc before writing cs so that cs is always in consistent state */
593 		radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rsrc, RADEON_USAGE_READ,
594 				      RADEON_PRIO_SDMA_BUFFER);
595 		radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, rdst, RADEON_USAGE_WRITE,
596 				      RADEON_PRIO_SDMA_BUFFER);
597 		radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 0, 0, csize));
598 		radeon_emit(cs, dst_offset & 0xfffffffc);
599 		radeon_emit(cs, src_offset & 0xfffffffc);
600 		radeon_emit(cs, (dst_offset >> 32UL) & 0xff);
601 		radeon_emit(cs, (src_offset >> 32UL) & 0xff);
602 		dst_offset += csize << 2;
603 		src_offset += csize << 2;
604 		size -= csize;
605 	}
606 }
607