1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #ifndef RADV_CS_H
26 #define RADV_CS_H
27
28 #include <string.h>
29 #include <stdint.h>
30 #include <assert.h>
31 #include "sid.h"
32
radeon_check_space(struct radeon_winsys * ws,struct radeon_winsys_cs * cs,unsigned needed)33 static inline unsigned radeon_check_space(struct radeon_winsys *ws,
34 struct radeon_winsys_cs *cs,
35 unsigned needed)
36 {
37 if (cs->max_dw - cs->cdw < needed)
38 ws->cs_grow(cs, needed);
39 return cs->cdw + needed;
40 }
41
radeon_set_config_reg_seq(struct radeon_winsys_cs * cs,unsigned reg,unsigned num)42 static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
43 {
44 assert(reg < SI_CONTEXT_REG_OFFSET);
45 assert(cs->cdw + 2 + num <= cs->max_dw);
46 assert(num);
47 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
48 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
49 }
50
radeon_set_config_reg(struct radeon_winsys_cs * cs,unsigned reg,unsigned value)51 static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
52 {
53 radeon_set_config_reg_seq(cs, reg, 1);
54 radeon_emit(cs, value);
55 }
56
radeon_set_context_reg_seq(struct radeon_winsys_cs * cs,unsigned reg,unsigned num)57 static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
58 {
59 assert(reg >= SI_CONTEXT_REG_OFFSET);
60 assert(cs->cdw + 2 + num <= cs->max_dw);
61 assert(num);
62 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
63 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
64 }
65
radeon_set_context_reg(struct radeon_winsys_cs * cs,unsigned reg,unsigned value)66 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
67 {
68 radeon_set_context_reg_seq(cs, reg, 1);
69 radeon_emit(cs, value);
70 }
71
72
radeon_set_context_reg_idx(struct radeon_winsys_cs * cs,unsigned reg,unsigned idx,unsigned value)73 static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,
74 unsigned reg, unsigned idx,
75 unsigned value)
76 {
77 assert(reg >= SI_CONTEXT_REG_OFFSET);
78 assert(cs->cdw + 3 <= cs->max_dw);
79 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
80 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
81 radeon_emit(cs, value);
82 }
83
radeon_set_sh_reg_seq(struct radeon_winsys_cs * cs,unsigned reg,unsigned num)84 static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
85 {
86 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
87 assert(cs->cdw + 2 + num <= cs->max_dw);
88 assert(num);
89 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
90 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
91 }
92
radeon_set_sh_reg(struct radeon_winsys_cs * cs,unsigned reg,unsigned value)93 static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
94 {
95 radeon_set_sh_reg_seq(cs, reg, 1);
96 radeon_emit(cs, value);
97 }
98
radeon_set_uconfig_reg_seq(struct radeon_winsys_cs * cs,unsigned reg,unsigned num)99 static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
100 {
101 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
102 assert(cs->cdw + 2 + num <= cs->max_dw);
103 assert(num);
104 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
105 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
106 }
107
radeon_set_uconfig_reg(struct radeon_winsys_cs * cs,unsigned reg,unsigned value)108 static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
109 {
110 radeon_set_uconfig_reg_seq(cs, reg, 1);
111 radeon_emit(cs, value);
112 }
113
radeon_set_uconfig_reg_idx(struct radeon_winsys_cs * cs,unsigned reg,unsigned idx,unsigned value)114 static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs,
115 unsigned reg, unsigned idx,
116 unsigned value)
117 {
118 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
119 assert(cs->cdw + 3 <= cs->max_dw);
120 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0));
121 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
122 radeon_emit(cs, value);
123 }
124
125 #endif /* RADV_CS_H */
126