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1 /*
2  * Copyright © 2016 Red Hat.
3  * Copyright © 2016 Bas Nieuwenhuizen
4  *
5  * based in part on anv driver which is:
6  * Copyright © 2015 Intel Corporation
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the "Software"),
10  * to deal in the Software without restriction, including without limitation
11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12  * and/or sell copies of the Software, and to permit persons to whom the
13  * Software is furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the next
16  * paragraph) shall be included in all copies or substantial portions of the
17  * Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25  * IN THE SOFTWARE.
26  */
27 
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <sys/utsname.h>
31 
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "ac_debug.h"
35 #include "radv_debug.h"
36 #include "radv_shader.h"
37 
38 #define TRACE_BO_SIZE 4096
39 
40 #define COLOR_RESET	"\033[0m"
41 #define COLOR_RED	"\033[31m"
42 #define COLOR_GREEN	"\033[1;32m"
43 #define COLOR_YELLOW	"\033[1;33m"
44 #define COLOR_CYAN	"\033[1;36m"
45 
46 /* Trace BO layout (offsets are 4 bytes):
47  *
48  * [0]: primary trace ID
49  * [1]: secondary trace ID
50  * [2-3]: 64-bit GFX pipeline pointer
51  * [4-5]: 64-bit COMPUTE pipeline pointer
52  * [6-7]: 64-bit descriptor set #0 pointer
53  * ...
54  * [68-69]: 64-bit descriptor set #31 pointer
55  */
56 
57 bool
radv_init_trace(struct radv_device * device)58 radv_init_trace(struct radv_device *device)
59 {
60 	struct radeon_winsys *ws = device->ws;
61 
62 	device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8,
63 					     RADEON_DOMAIN_VRAM,
64 					     RADEON_FLAG_CPU_ACCESS|
65 					     RADEON_FLAG_NO_INTERPROCESS_SHARING);
66 	if (!device->trace_bo)
67 		return false;
68 
69 	device->trace_id_ptr = ws->buffer_map(device->trace_bo);
70 	if (!device->trace_id_ptr)
71 		return false;
72 
73 	memset(device->trace_id_ptr, 0, TRACE_BO_SIZE);
74 
75 	ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
76 			    &device->dmesg_timestamp, NULL);
77 
78 	return true;
79 }
80 
81 static void
radv_dump_trace(struct radv_device * device,struct radeon_winsys_cs * cs)82 radv_dump_trace(struct radv_device *device, struct radeon_winsys_cs *cs)
83 {
84 	const char *filename = getenv("RADV_TRACE_FILE");
85 	FILE *f = fopen(filename, "w");
86 
87 	if (!f) {
88 		fprintf(stderr, "Failed to write trace dump to %s\n", filename);
89 		return;
90 	}
91 
92 	fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
93 	device->ws->cs_dump(cs, f, (const int*)device->trace_id_ptr, 2);
94 	fclose(f);
95 }
96 
97 static void
radv_dump_mmapped_reg(struct radv_device * device,FILE * f,unsigned offset)98 radv_dump_mmapped_reg(struct radv_device *device, FILE *f, unsigned offset)
99 {
100 	struct radeon_winsys *ws = device->ws;
101 	uint32_t value;
102 
103 	if (ws->read_registers(ws, offset, 1, &value))
104 		ac_dump_reg(f, device->physical_device->rad_info.chip_class,
105 			    offset, value, ~0);
106 }
107 
108 static void
radv_dump_debug_registers(struct radv_device * device,FILE * f)109 radv_dump_debug_registers(struct radv_device *device, FILE *f)
110 {
111 	struct radeon_info *info = &device->physical_device->rad_info;
112 
113 	if (info->drm_major == 2 && info->drm_minor < 42)
114 		return; /* no radeon support */
115 
116 	fprintf(f, "Memory-mapped registers:\n");
117 	radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
118 
119 	/* No other registers can be read on DRM < 3.1.0. */
120 	if (info->drm_major < 3 || info->drm_minor < 1) {
121 		fprintf(f, "\n");
122 		return;
123 	}
124 
125 	radv_dump_mmapped_reg(device, f, R_008008_GRBM_STATUS2);
126 	radv_dump_mmapped_reg(device, f, R_008014_GRBM_STATUS_SE0);
127 	radv_dump_mmapped_reg(device, f, R_008018_GRBM_STATUS_SE1);
128 	radv_dump_mmapped_reg(device, f, R_008038_GRBM_STATUS_SE2);
129 	radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3);
130 	radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG);
131 	radv_dump_mmapped_reg(device, f, R_00D834_SDMA1_STATUS_REG);
132 	if (info->chip_class <= VI) {
133 		radv_dump_mmapped_reg(device, f, R_000E50_SRBM_STATUS);
134 		radv_dump_mmapped_reg(device, f, R_000E4C_SRBM_STATUS2);
135 		radv_dump_mmapped_reg(device, f, R_000E54_SRBM_STATUS3);
136 	}
137 	radv_dump_mmapped_reg(device, f, R_008680_CP_STAT);
138 	radv_dump_mmapped_reg(device, f, R_008674_CP_STALLED_STAT1);
139 	radv_dump_mmapped_reg(device, f, R_008678_CP_STALLED_STAT2);
140 	radv_dump_mmapped_reg(device, f, R_008670_CP_STALLED_STAT3);
141 	radv_dump_mmapped_reg(device, f, R_008210_CP_CPC_STATUS);
142 	radv_dump_mmapped_reg(device, f, R_008214_CP_CPC_BUSY_STAT);
143 	radv_dump_mmapped_reg(device, f, R_008218_CP_CPC_STALLED_STAT1);
144 	radv_dump_mmapped_reg(device, f, R_00821C_CP_CPF_STATUS);
145 	radv_dump_mmapped_reg(device, f, R_008220_CP_CPF_BUSY_STAT);
146 	radv_dump_mmapped_reg(device, f, R_008224_CP_CPF_STALLED_STAT1);
147 	fprintf(f, "\n");
148 }
149 
150 static const char *
radv_get_descriptor_name(enum VkDescriptorType type)151 radv_get_descriptor_name(enum VkDescriptorType type)
152 {
153 	switch (type) {
154 	case VK_DESCRIPTOR_TYPE_SAMPLER:
155 		return "SAMPLER";
156 	case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
157 		return "COMBINED_IMAGE_SAMPLER";
158 	case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
159 		return "SAMPLED_IMAGE";
160 	case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
161 		return "STORAGE_IMAGE";
162 	case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
163 		return "UNIFORM_TEXEL_BUFFER";
164 	case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
165 		return "STORAGE_TEXEL_BUFFER";
166 	case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
167 		return "UNIFORM_BUFFER";
168 	case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
169 		return "STORAGE_BUFFER";
170 	case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
171 		return "UNIFORM_BUFFER_DYNAMIC";
172 	case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
173 		return "STORAGE_BUFFER_DYNAMIC";
174 	case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
175 		return "INPUT_ATTACHMENT";
176 	default:
177 		return "UNKNOWN";
178 	}
179 }
180 
181 static void
radv_dump_buffer_descriptor(enum chip_class chip_class,const uint32_t * desc,FILE * f)182 radv_dump_buffer_descriptor(enum chip_class chip_class, const uint32_t *desc,
183 			    FILE *f)
184 {
185 	fprintf(f, COLOR_CYAN "    Buffer:" COLOR_RESET "\n");
186 	for (unsigned j = 0; j < 4; j++)
187 		ac_dump_reg(f, chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4,
188 			    desc[j], 0xffffffff);
189 }
190 
191 static void
radv_dump_image_descriptor(enum chip_class chip_class,const uint32_t * desc,FILE * f)192 radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc,
193 			   FILE *f)
194 {
195 	fprintf(f, COLOR_CYAN "    Image:" COLOR_RESET "\n");
196 	for (unsigned j = 0; j < 8; j++)
197 		ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4,
198 			    desc[j], 0xffffffff);
199 
200 	fprintf(f, COLOR_CYAN "    FMASK:" COLOR_RESET "\n");
201 	for (unsigned j = 0; j < 8; j++)
202 		ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4,
203 			    desc[8 + j], 0xffffffff);
204 }
205 
206 static void
radv_dump_sampler_descriptor(enum chip_class chip_class,const uint32_t * desc,FILE * f)207 radv_dump_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc,
208 			     FILE *f)
209 {
210 	fprintf(f, COLOR_CYAN "    Sampler state:" COLOR_RESET "\n");
211 	for (unsigned j = 0; j < 4; j++) {
212 		ac_dump_reg(f, chip_class, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4,
213 			    desc[j], 0xffffffff);
214 	}
215 }
216 
217 static void
radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class,const uint32_t * desc,FILE * f)218 radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class,
219 					    const uint32_t *desc, FILE *f)
220 {
221 	radv_dump_image_descriptor(chip_class, desc, f);
222 	radv_dump_sampler_descriptor(chip_class, desc + 16, f);
223 }
224 
225 static void
radv_dump_descriptor_set(enum chip_class chip_class,struct radv_descriptor_set * set,unsigned id,FILE * f)226 radv_dump_descriptor_set(enum chip_class chip_class,
227 			 struct radv_descriptor_set *set, unsigned id, FILE *f)
228 {
229 	const struct radv_descriptor_set_layout *layout;
230 	int i;
231 
232 	if (!set)
233 		return;
234 	layout = set->layout;
235 
236 	fprintf(f, "** descriptor set (%d) **\n", id);
237 	fprintf(f, "va: 0x%"PRIx64"\n", set->va);
238 	fprintf(f, "size: %d\n", set->size);
239 	fprintf(f, "mapped_ptr:\n");
240 
241 	for (i = 0; i < set->size / 4; i++) {
242 		fprintf(f, "\t[0x%x] = 0x%08x\n", i, set->mapped_ptr[i]);
243 	}
244 	fprintf(f, "\n");
245 
246 	fprintf(f, "\t*** layout ***\n");
247 	fprintf(f, "\tbinding_count: %d\n", layout->binding_count);
248 	fprintf(f, "\tsize: %d\n", layout->size);
249 	fprintf(f, "\tshader_stages: %x\n", layout->shader_stages);
250 	fprintf(f, "\tdynamic_shader_stages: %x\n",
251 		layout->dynamic_shader_stages);
252 	fprintf(f, "\tbuffer_count: %d\n", layout->buffer_count);
253 	fprintf(f, "\tdynamic_offset_count: %d\n",
254 		layout->dynamic_offset_count);
255 	fprintf(f, "\n");
256 
257 	for (i = 0; i < set->layout->binding_count; i++) {
258 		uint32_t *desc =
259 			set->mapped_ptr + layout->binding[i].offset / 4;
260 
261 		fprintf(f, "\t\t**** binding layout (%d) ****\n", i);
262 		fprintf(f, "\t\ttype: %s\n",
263 			radv_get_descriptor_name(layout->binding[i].type));
264 		fprintf(f, "\t\tarray_size: %d\n",
265 			layout->binding[i].array_size);
266 		fprintf(f, "\t\toffset: %d\n",
267 			layout->binding[i].offset);
268 		fprintf(f, "\t\tbuffer_offset: %d\n",
269 			layout->binding[i].buffer_offset);
270 		fprintf(f, "\t\tdynamic_offset_offset: %d\n",
271 			layout->binding[i].dynamic_offset_offset);
272 		fprintf(f, "\t\tdynamic_offset_count: %d\n",
273 			layout->binding[i].dynamic_offset_count);
274 		fprintf(f, "\t\tsize: %d\n",
275 			layout->binding[i].size);
276 		fprintf(f, "\t\timmutable_samplers_offset: %d\n",
277 			layout->binding[i].immutable_samplers_offset);
278 		fprintf(f, "\t\timmutable_samplers_equal: %d\n",
279 			layout->binding[i].immutable_samplers_equal);
280 		fprintf(f, "\n");
281 
282 		switch (layout->binding[i].type) {
283 		case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
284 		case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
285 		case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
286 		case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
287 			radv_dump_buffer_descriptor(chip_class, desc, f);
288 			break;
289 		case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
290 		case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
291 		case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
292 			radv_dump_image_descriptor(chip_class, desc, f);
293 			break;
294 		case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
295 			radv_dump_combined_image_sampler_descriptor(chip_class, desc, f);
296 			break;
297 		case VK_DESCRIPTOR_TYPE_SAMPLER:
298 			radv_dump_sampler_descriptor(chip_class, desc, f);
299 			break;
300 		case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
301 		case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
302 			/* todo */
303 			break;
304 		default:
305 			assert(!"unknown descriptor type");
306 			break;
307 		}
308 		fprintf(f, "\n");
309 	}
310 	fprintf(f, "\n\n");
311 }
312 
313 static void
radv_dump_descriptors(struct radv_pipeline * pipeline,FILE * f)314 radv_dump_descriptors(struct radv_pipeline *pipeline, FILE *f)
315 {
316 	struct radv_device *device = pipeline->device;
317 	enum chip_class chip_class = device->physical_device->rad_info.chip_class;
318 	uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
319 	int i;
320 
321 	fprintf(f, "List of descriptors:\n");
322 	for (i = 0; i < MAX_SETS; i++) {
323 		struct radv_descriptor_set *set =
324 			(struct radv_descriptor_set *)ptr[i + 3];
325 
326 		radv_dump_descriptor_set(chip_class, set, i, f);
327 	}
328 }
329 
330 struct radv_shader_inst {
331 	char text[160];  /* one disasm line */
332 	unsigned offset; /* instruction offset */
333 	unsigned size;   /* instruction size = 4 or 8 */
334 };
335 
336 /* Split a disassembly string into lines and add them to the array pointed
337  * to by "instructions". */
si_add_split_disasm(const char * disasm,uint64_t start_addr,unsigned * num,struct radv_shader_inst * instructions)338 static void si_add_split_disasm(const char *disasm,
339 				uint64_t start_addr,
340 				unsigned *num,
341 				struct radv_shader_inst *instructions)
342 {
343 	struct radv_shader_inst *last_inst = *num ? &instructions[*num - 1] : NULL;
344 	char *next;
345 
346 	while ((next = strchr(disasm, '\n'))) {
347 		struct radv_shader_inst *inst = &instructions[*num];
348 		unsigned len = next - disasm;
349 
350 		assert(len < ARRAY_SIZE(inst->text));
351 		memcpy(inst->text, disasm, len);
352 		inst->text[len] = 0;
353 		inst->offset = last_inst ? last_inst->offset + last_inst->size : 0;
354 
355 		const char *semicolon = strchr(disasm, ';');
356 		assert(semicolon);
357 		/* More than 16 chars after ";" means the instruction is 8 bytes long. */
358 		inst->size = next - semicolon > 16 ? 8 : 4;
359 
360 		snprintf(inst->text + len, ARRAY_SIZE(inst->text) - len,
361 			" [PC=0x%"PRIx64", off=%u, size=%u]",
362 			start_addr + inst->offset, inst->offset, inst->size);
363 
364 		last_inst = inst;
365 		(*num)++;
366 		disasm = next + 1;
367 	}
368 }
369 
370 static void
radv_dump_annotated_shader(struct radv_pipeline * pipeline,struct radv_shader_variant * shader,gl_shader_stage stage,struct ac_wave_info * waves,unsigned num_waves,FILE * f)371 radv_dump_annotated_shader(struct radv_pipeline *pipeline,
372 			   struct radv_shader_variant *shader,
373 			   gl_shader_stage stage,
374 			   struct ac_wave_info *waves, unsigned num_waves,
375 			   FILE *f)
376 {
377 	uint64_t start_addr, end_addr;
378 	unsigned i;
379 
380 	if (!shader)
381 		return;
382 
383 	start_addr = radv_buffer_get_va(shader->bo) + shader->bo_offset;
384 	end_addr = start_addr + shader->code_size;
385 
386 	/* See if any wave executes the shader. */
387 	for (i = 0; i < num_waves; i++) {
388 		if (start_addr <= waves[i].pc && waves[i].pc <= end_addr)
389 			break;
390 	}
391 
392 	if (i == num_waves)
393 		return; /* the shader is not being executed */
394 
395 	/* Remember the first found wave. The waves are sorted according to PC. */
396 	waves = &waves[i];
397 	num_waves -= i;
398 
399 	/* Get the list of instructions.
400 	 * Buffer size / 4 is the upper bound of the instruction count.
401 	 */
402 	unsigned num_inst = 0;
403 	struct radv_shader_inst *instructions =
404 		calloc(shader->code_size / 4, sizeof(struct radv_shader_inst));
405 
406 	si_add_split_disasm(shader->disasm_string,
407 			    start_addr, &num_inst, instructions);
408 
409 	fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n",
410 		radv_get_shader_name(shader, stage));
411 
412 	/* Print instructions with annotations. */
413 	for (i = 0; i < num_inst; i++) {
414 		struct radv_shader_inst *inst = &instructions[i];
415 
416 		fprintf(f, "%s\n", inst->text);
417 
418 		/* Print which waves execute the instruction right now. */
419 		while (num_waves && start_addr + inst->offset == waves->pc) {
420 			fprintf(f,
421 				"          " COLOR_GREEN "^ SE%u SH%u CU%u "
422 				"SIMD%u WAVE%u  EXEC=%016"PRIx64 "  ",
423 				waves->se, waves->sh, waves->cu, waves->simd,
424 				waves->wave, waves->exec);
425 
426 			if (inst->size == 4) {
427 				fprintf(f, "INST32=%08X" COLOR_RESET "\n",
428 					waves->inst_dw0);
429 			} else {
430 				fprintf(f, "INST64=%08X %08X" COLOR_RESET "\n",
431 					waves->inst_dw0, waves->inst_dw1);
432 			}
433 
434 			waves->matched = true;
435 			waves = &waves[1];
436 			num_waves--;
437 		}
438 	}
439 
440 	fprintf(f, "\n\n");
441 	free(instructions);
442 }
443 
444 static void
radv_dump_annotated_shaders(struct radv_pipeline * pipeline,struct radv_shader_variant * compute_shader,FILE * f)445 radv_dump_annotated_shaders(struct radv_pipeline *pipeline,
446 			    struct radv_shader_variant *compute_shader,
447 			    FILE *f)
448 {
449 	struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
450 	unsigned num_waves = ac_get_wave_info(waves);
451 	unsigned mask;
452 
453 	fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET
454 		"\n\n", num_waves);
455 
456 	/* Dump annotated active graphics shaders. */
457 	mask = pipeline->active_stages;
458 	while (mask) {
459 		int stage = u_bit_scan(&mask);
460 
461 		radv_dump_annotated_shader(pipeline, pipeline->shaders[stage],
462 					   stage, waves, num_waves, f);
463 	}
464 
465 	radv_dump_annotated_shader(pipeline, compute_shader,
466 				   MESA_SHADER_COMPUTE, waves, num_waves, f);
467 
468 	/* Print waves executing shaders that are not currently bound. */
469 	unsigned i;
470 	bool found = false;
471 	for (i = 0; i < num_waves; i++) {
472 		if (waves[i].matched)
473 			continue;
474 
475 		if (!found) {
476 			fprintf(f, COLOR_CYAN
477 				"Waves not executing currently-bound shaders:"
478 				COLOR_RESET "\n");
479 			found = true;
480 		}
481 		fprintf(f, "    SE%u SH%u CU%u SIMD%u WAVE%u  EXEC=%016"PRIx64
482 			"  INST=%08X %08X  PC=%"PRIx64"\n",
483 			waves[i].se, waves[i].sh, waves[i].cu, waves[i].simd,
484 			waves[i].wave, waves[i].exec, waves[i].inst_dw0,
485 			waves[i].inst_dw1, waves[i].pc);
486 	}
487 	if (found)
488 		fprintf(f, "\n\n");
489 }
490 
491 static void
radv_dump_shader(struct radv_pipeline * pipeline,struct radv_shader_variant * shader,gl_shader_stage stage,FILE * f)492 radv_dump_shader(struct radv_pipeline *pipeline,
493 		 struct radv_shader_variant *shader, gl_shader_stage stage,
494 		 FILE *f)
495 {
496 	if (!shader)
497 		return;
498 
499 	fprintf(f, "%s:\n\n", radv_get_shader_name(shader, stage));
500 
501 	if (shader->spirv) {
502 		fprintf(f, "SPIRV:\n");
503 		radv_print_spirv(shader->spirv, shader->spirv_size, f);
504 	}
505 
506 	if (shader->nir) {
507 		fprintf(f, "NIR:\n");
508 		nir_print_shader(shader->nir, f);
509 	}
510 
511 	fprintf(f, "DISASM:\n%s\n", shader->disasm_string);
512 
513 	radv_shader_dump_stats(pipeline->device, shader, stage, f);
514 }
515 
516 static void
radv_dump_shaders(struct radv_pipeline * pipeline,struct radv_shader_variant * compute_shader,FILE * f)517 radv_dump_shaders(struct radv_pipeline *pipeline,
518 		  struct radv_shader_variant *compute_shader, FILE *f)
519 {
520 	unsigned mask;
521 
522 	/* Dump active graphics shaders. */
523 	mask = pipeline->active_stages;
524 	while (mask) {
525 		int stage = u_bit_scan(&mask);
526 
527 		radv_dump_shader(pipeline, pipeline->shaders[stage], stage, f);
528 	}
529 
530 	radv_dump_shader(pipeline, compute_shader, MESA_SHADER_COMPUTE, f);
531 }
532 
533 static void
radv_dump_graphics_state(struct radv_pipeline * graphics_pipeline,struct radv_pipeline * compute_pipeline,FILE * f)534 radv_dump_graphics_state(struct radv_pipeline *graphics_pipeline,
535 			 struct radv_pipeline *compute_pipeline, FILE *f)
536 {
537 	struct radv_shader_variant *compute_shader =
538 		compute_pipeline ? compute_pipeline->shaders[MESA_SHADER_COMPUTE] : NULL;
539 
540 	if (!graphics_pipeline)
541 		return;
542 
543 	radv_dump_shaders(graphics_pipeline, compute_shader, f);
544 	radv_dump_annotated_shaders(graphics_pipeline, compute_shader, f);
545 	radv_dump_descriptors(graphics_pipeline, f);
546 }
547 
548 static void
radv_dump_compute_state(struct radv_pipeline * compute_pipeline,FILE * f)549 radv_dump_compute_state(struct radv_pipeline *compute_pipeline, FILE *f)
550 {
551 	if (!compute_pipeline)
552 		return;
553 
554 	radv_dump_shaders(compute_pipeline,
555 			  compute_pipeline->shaders[MESA_SHADER_COMPUTE], f);
556 	radv_dump_annotated_shaders(compute_pipeline,
557 				    compute_pipeline->shaders[MESA_SHADER_COMPUTE],
558 				    f);
559 	radv_dump_descriptors(compute_pipeline, f);
560 }
561 
562 static struct radv_pipeline *
radv_get_saved_graphics_pipeline(struct radv_device * device)563 radv_get_saved_graphics_pipeline(struct radv_device *device)
564 {
565 	uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
566 
567 	return (struct radv_pipeline *)ptr[1];
568 }
569 
570 static struct radv_pipeline *
radv_get_saved_compute_pipeline(struct radv_device * device)571 radv_get_saved_compute_pipeline(struct radv_device *device)
572 {
573 	uint64_t *ptr = (uint64_t *)device->trace_id_ptr;
574 
575 	return (struct radv_pipeline *)ptr[2];
576 }
577 
578 static void
radv_dump_dmesg(FILE * f)579 radv_dump_dmesg(FILE *f)
580 {
581 	char line[2000];
582 	FILE *p;
583 
584 	p = popen("dmesg | tail -n60", "r");
585 	if (!p)
586 		return;
587 
588 	fprintf(f, "\nLast 60 lines of dmesg:\n\n");
589 	while (fgets(line, sizeof(line), p))
590 		fputs(line, f);
591 	fprintf(f, "\n");
592 
593 	pclose(p);
594 }
595 
596 static void
radv_dump_enabled_options(struct radv_device * device,FILE * f)597 radv_dump_enabled_options(struct radv_device *device, FILE *f)
598 {
599 	uint64_t mask;
600 
601 	fprintf(f, "Enabled debug options: ");
602 
603 	mask = device->instance->debug_flags;
604 	while (mask) {
605 		int i = u_bit_scan64(&mask);
606 		fprintf(f, "%s, ", radv_get_debug_option_name(i));
607 	}
608 	fprintf(f, "\n");
609 
610 	fprintf(f, "Enabled perftest options: ");
611 
612 	mask = device->instance->perftest_flags;
613 	while (mask) {
614 		int i = u_bit_scan64(&mask);
615 		fprintf(f, "%s, ", radv_get_perftest_option_name(i));
616 	}
617 	fprintf(f, "\n");
618 }
619 
620 static void
radv_dump_device_name(struct radv_device * device,FILE * f)621 radv_dump_device_name(struct radv_device *device, FILE *f)
622 {
623 	struct radeon_info *info = &device->physical_device->rad_info;
624 	char llvm_string[32] = {}, kernel_version[128] = {};
625 	struct utsname uname_data;
626 	const char *chip_name;
627 
628 	chip_name = device->ws->get_chip_name(device->ws);
629 
630 	if (uname(&uname_data) == 0)
631 		snprintf(kernel_version, sizeof(kernel_version),
632 			 " / %s", uname_data.release);
633 
634 	if (HAVE_LLVM > 0) {
635 		snprintf(llvm_string, sizeof(llvm_string),
636 			 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
637 			 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
638 	}
639 
640 	fprintf(f, "Device name: %s (%s DRM %i.%i.%i%s%s)\n\n",
641 		chip_name, device->physical_device->name,
642 		info->drm_major, info->drm_minor, info->drm_patchlevel,
643 		kernel_version, llvm_string);
644 }
645 
646 static bool
radv_gpu_hang_occured(struct radv_queue * queue,enum ring_type ring)647 radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring)
648 {
649 	struct radeon_winsys *ws = queue->device->ws;
650 
651 	if (!ws->ctx_wait_idle(queue->hw_ctx, ring, queue->queue_idx))
652 		return true;
653 
654 	return false;
655 }
656 
657 void
radv_check_gpu_hangs(struct radv_queue * queue,struct radeon_winsys_cs * cs)658 radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs *cs)
659 {
660 	struct radv_pipeline *graphics_pipeline, *compute_pipeline;
661 	struct radv_device *device = queue->device;
662 	enum ring_type ring;
663 	uint64_t addr;
664 
665 	ring = radv_queue_family_to_ring(queue->queue_family_index);
666 
667 	bool hang_occurred = radv_gpu_hang_occured(queue, ring);
668 	bool vm_fault_occurred = false;
669 	if (queue->device->instance->debug_flags & RADV_DEBUG_VM_FAULTS)
670 		vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
671 		                                        &device->dmesg_timestamp, &addr);
672 	if (!hang_occurred && !vm_fault_occurred)
673 		return;
674 
675 	graphics_pipeline = radv_get_saved_graphics_pipeline(device);
676 	compute_pipeline = radv_get_saved_compute_pipeline(device);
677 
678 	fprintf(stderr, "GPU hang report:\n\n");
679 	radv_dump_device_name(device, stderr);
680 
681 	radv_dump_enabled_options(device, stderr);
682 	radv_dump_dmesg(stderr);
683 
684 	if (vm_fault_occurred) {
685 		fprintf(stderr, "VM fault report.\n\n");
686 		fprintf(stderr, "Failing VM page: 0x%08"PRIx64"\n\n", addr);
687 	}
688 
689 	radv_dump_debug_registers(device, stderr);
690 
691 	switch (ring) {
692 	case RING_GFX:
693 		radv_dump_graphics_state(graphics_pipeline, compute_pipeline,
694 					 stderr);
695 		break;
696 	case RING_COMPUTE:
697 		radv_dump_compute_state(compute_pipeline, stderr);
698 		break;
699 	default:
700 		assert(0);
701 		break;
702 	}
703 
704 	radv_dump_trace(queue->device, cs);
705 	abort();
706 }
707 
708 void
radv_print_spirv(uint32_t * data,uint32_t size,FILE * fp)709 radv_print_spirv(uint32_t *data, uint32_t size, FILE *fp)
710 {
711 	char path[] = "/tmp/fileXXXXXX";
712 	char line[2048], command[128];
713 	FILE *p;
714 	int fd;
715 
716 	/* Dump the binary into a temporary file. */
717 	fd = mkstemp(path);
718 	if (fd < 0)
719 		return;
720 
721 	if (write(fd, data, size) == -1)
722 		goto fail;
723 
724 	sprintf(command, "spirv-dis %s", path);
725 
726 	/* Disassemble using spirv-dis if installed. */
727 	p = popen(command, "r");
728 	if (p) {
729 		while (fgets(line, sizeof(line), p))
730 			fprintf(fp, "%s", line);
731 		pclose(p);
732 	}
733 
734 fail:
735 	close(fd);
736 	unlink(path);
737 }
738