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1 /*
2  * Copyright © 2016 Red Hat
3  *
4  * based on anv driver:
5  * Copyright © 2016 Intel Corporation
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the "Software"),
9  * to deal in the Software without restriction, including without limitation
10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11  * and/or sell copies of the Software, and to permit persons to whom the
12  * Software is furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the next
15  * paragraph) shall be included in all copies or substantial portions of the
16  * Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24  * IN THE SOFTWARE.
25  */
26 
27 #include "radv_meta.h"
28 #include "nir/nir_builder.h"
29 #include "vk_format.h"
30 
31 enum blit2d_src_type {
32 	BLIT2D_SRC_TYPE_IMAGE,
33 	BLIT2D_SRC_TYPE_IMAGE_3D,
34 	BLIT2D_SRC_TYPE_BUFFER,
35 	BLIT2D_NUM_SRC_TYPES,
36 };
37 
38 static void
create_iview(struct radv_cmd_buffer * cmd_buffer,struct radv_meta_blit2d_surf * surf,struct radv_image_view * iview,VkFormat depth_format,VkImageAspectFlagBits aspects)39 create_iview(struct radv_cmd_buffer *cmd_buffer,
40              struct radv_meta_blit2d_surf *surf,
41              struct radv_image_view *iview, VkFormat depth_format,
42               VkImageAspectFlagBits aspects)
43 {
44 	VkFormat format;
45 	VkImageViewType view_type = cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 ? VK_IMAGE_VIEW_TYPE_2D :
46 		radv_meta_get_view_type(surf->image);
47 
48 	if (depth_format)
49 		format = depth_format;
50 	else
51 		format = surf->format;
52 
53 	radv_image_view_init(iview, cmd_buffer->device,
54 			     &(VkImageViewCreateInfo) {
55 				     .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
56 					     .image = radv_image_to_handle(surf->image),
57 					     .viewType = view_type,
58 					     .format = format,
59 					     .subresourceRange = {
60 					     .aspectMask = aspects,
61 					     .baseMipLevel = surf->level,
62 					     .levelCount = 1,
63 					     .baseArrayLayer = surf->layer,
64 					     .layerCount = 1
65 				     },
66 			     });
67 }
68 
69 static void
create_bview(struct radv_cmd_buffer * cmd_buffer,struct radv_meta_blit2d_buffer * src,struct radv_buffer_view * bview,VkFormat depth_format)70 create_bview(struct radv_cmd_buffer *cmd_buffer,
71 	     struct radv_meta_blit2d_buffer *src,
72 	     struct radv_buffer_view *bview, VkFormat depth_format)
73 {
74 	VkFormat format;
75 
76 	if (depth_format)
77 		format = depth_format;
78 	else
79 		format = src->format;
80 	radv_buffer_view_init(bview, cmd_buffer->device,
81 			      &(VkBufferViewCreateInfo) {
82 				      .sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO,
83 				      .flags = 0,
84 				      .buffer = radv_buffer_to_handle(src->buffer),
85 				      .format = format,
86 				      .offset = src->offset,
87 				      .range = VK_WHOLE_SIZE,
88 			      });
89 
90 }
91 
92 struct blit2d_src_temps {
93 	struct radv_image_view iview;
94 	struct radv_buffer_view bview;
95 };
96 
97 static void
blit2d_bind_src(struct radv_cmd_buffer * cmd_buffer,struct radv_meta_blit2d_surf * src_img,struct radv_meta_blit2d_buffer * src_buf,struct blit2d_src_temps * tmp,enum blit2d_src_type src_type,VkFormat depth_format,VkImageAspectFlagBits aspects)98 blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
99                 struct radv_meta_blit2d_surf *src_img,
100                 struct radv_meta_blit2d_buffer *src_buf,
101                 struct blit2d_src_temps *tmp,
102                 enum blit2d_src_type src_type, VkFormat depth_format,
103                 VkImageAspectFlagBits aspects)
104 {
105 	struct radv_device *device = cmd_buffer->device;
106 
107 	if (src_type == BLIT2D_SRC_TYPE_BUFFER) {
108 		create_bview(cmd_buffer, src_buf, &tmp->bview, depth_format);
109 
110 		radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
111 					      device->meta_state.blit2d.p_layouts[src_type],
112 					      0, /* set */
113 					      1, /* descriptorWriteCount */
114 					      (VkWriteDescriptorSet[]) {
115 					              {
116 					                      .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
117 					                      .dstBinding = 0,
118 					                      .dstArrayElement = 0,
119 					                      .descriptorCount = 1,
120 					                      .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
121 					                      .pTexelBufferView = (VkBufferView[])  { radv_buffer_view_to_handle(&tmp->bview) }
122 					              }
123 					      });
124 
125 		radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
126 				      device->meta_state.blit2d.p_layouts[src_type],
127 				      VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4,
128 				      &src_buf->pitch);
129 	} else {
130 		create_iview(cmd_buffer, src_img, &tmp->iview, depth_format, aspects);
131 
132 		if (src_type == BLIT2D_SRC_TYPE_IMAGE_3D)
133 			radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
134 					      device->meta_state.blit2d.p_layouts[src_type],
135 					      VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4,
136 					      &src_img->layer);
137 
138 		radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
139 					      device->meta_state.blit2d.p_layouts[src_type],
140 					      0, /* set */
141 					      1, /* descriptorWriteCount */
142 					      (VkWriteDescriptorSet[]) {
143 					              {
144 					                      .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
145 					                      .dstBinding = 0,
146 					                      .dstArrayElement = 0,
147 					                      .descriptorCount = 1,
148 					                      .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
149 					                      .pImageInfo = (VkDescriptorImageInfo[]) {
150 					                              {
151 					                                      .sampler = VK_NULL_HANDLE,
152 					                                      .imageView = radv_image_view_to_handle(&tmp->iview),
153 					                                      .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
154 					                              },
155 					                      }
156 					              }
157 					      });
158 	}
159 }
160 
161 struct blit2d_dst_temps {
162 	VkImage image;
163 	struct radv_image_view iview;
164 	VkFramebuffer fb;
165 };
166 
167 static void
blit2d_bind_dst(struct radv_cmd_buffer * cmd_buffer,struct radv_meta_blit2d_surf * dst,uint32_t width,uint32_t height,VkFormat depth_format,struct blit2d_dst_temps * tmp,VkImageAspectFlagBits aspects)168 blit2d_bind_dst(struct radv_cmd_buffer *cmd_buffer,
169                 struct radv_meta_blit2d_surf *dst,
170                 uint32_t width,
171                 uint32_t height,
172 		VkFormat depth_format,
173                 struct blit2d_dst_temps *tmp,
174                 VkImageAspectFlagBits aspects)
175 {
176 	create_iview(cmd_buffer, dst, &tmp->iview, depth_format, aspects);
177 
178 	radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
179 			       &(VkFramebufferCreateInfo) {
180 				       .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
181 					       .attachmentCount = 1,
182 					       .pAttachments = (VkImageView[]) {
183 					       radv_image_view_to_handle(&tmp->iview),
184 				       },
185 				       .width = width,
186 				       .height = height,
187 				       .layers = 1
188 				}, &cmd_buffer->pool->alloc, &tmp->fb);
189 }
190 
191 static void
bind_pipeline(struct radv_cmd_buffer * cmd_buffer,enum blit2d_src_type src_type,unsigned fs_key)192 bind_pipeline(struct radv_cmd_buffer *cmd_buffer,
193               enum blit2d_src_type src_type, unsigned fs_key)
194 {
195 	VkPipeline pipeline =
196 		cmd_buffer->device->meta_state.blit2d.pipelines[src_type][fs_key];
197 
198 	radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
199 			     VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
200 }
201 
202 static void
bind_depth_pipeline(struct radv_cmd_buffer * cmd_buffer,enum blit2d_src_type src_type)203 bind_depth_pipeline(struct radv_cmd_buffer *cmd_buffer,
204 		    enum blit2d_src_type src_type)
205 {
206 	VkPipeline pipeline =
207 		cmd_buffer->device->meta_state.blit2d.depth_only_pipeline[src_type];
208 
209 	radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
210 			     VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
211 }
212 
213 static void
bind_stencil_pipeline(struct radv_cmd_buffer * cmd_buffer,enum blit2d_src_type src_type)214 bind_stencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
215 		      enum blit2d_src_type src_type)
216 {
217 	VkPipeline pipeline =
218 		cmd_buffer->device->meta_state.blit2d.stencil_only_pipeline[src_type];
219 
220 	radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
221 			     VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
222 }
223 
224 static void
radv_meta_blit2d_normal_dst(struct radv_cmd_buffer * cmd_buffer,struct radv_meta_blit2d_surf * src_img,struct radv_meta_blit2d_buffer * src_buf,struct radv_meta_blit2d_surf * dst,unsigned num_rects,struct radv_meta_blit2d_rect * rects,enum blit2d_src_type src_type)225 radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
226 			    struct radv_meta_blit2d_surf *src_img,
227 			    struct radv_meta_blit2d_buffer *src_buf,
228 			    struct radv_meta_blit2d_surf *dst,
229 			    unsigned num_rects,
230 			    struct radv_meta_blit2d_rect *rects, enum blit2d_src_type src_type)
231 {
232 	struct radv_device *device = cmd_buffer->device;
233 
234 	for (unsigned r = 0; r < num_rects; ++r) {
235 		unsigned i;
236 		for_each_bit(i, dst->aspect_mask) {
237 			unsigned aspect_mask = 1u << i;
238 			VkFormat depth_format = 0;
239 			if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
240 				depth_format = vk_format_stencil_only(dst->image->vk_format);
241 			else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT)
242 				depth_format = vk_format_depth_only(dst->image->vk_format);
243 			struct blit2d_src_temps src_temps;
244 			blit2d_bind_src(cmd_buffer, src_img, src_buf, &src_temps, src_type, depth_format, aspect_mask);
245 
246 			struct blit2d_dst_temps dst_temps;
247 			blit2d_bind_dst(cmd_buffer, dst, rects[r].dst_x + rects[r].width,
248 					rects[r].dst_y + rects[r].height, depth_format, &dst_temps, aspect_mask);
249 
250 			float vertex_push_constants[4] = {
251 				rects[r].src_x,
252 				rects[r].src_y,
253 				rects[r].src_x + rects[r].width,
254 				rects[r].src_y + rects[r].height,
255 			};
256 
257 			radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
258 					device->meta_state.blit2d.p_layouts[src_type],
259 					VK_SHADER_STAGE_VERTEX_BIT, 0, 16,
260 					vertex_push_constants);
261 
262 			if (aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT) {
263 				unsigned fs_key = radv_format_meta_fs_key(dst_temps.iview.vk_format);
264 				unsigned dst_layout = radv_meta_dst_layout_from_layout(dst->current_layout);
265 
266 				radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
267 							&(VkRenderPassBeginInfo) {
268 								.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
269 									.renderPass = device->meta_state.blit2d.render_passes[fs_key][dst_layout],
270 									.framebuffer = dst_temps.fb,
271 									.renderArea = {
272 									.offset = { rects[r].dst_x, rects[r].dst_y, },
273 									.extent = { rects[r].width, rects[r].height },
274 								},
275 									.clearValueCount = 0,
276 										.pClearValues = NULL,
277 										}, VK_SUBPASS_CONTENTS_INLINE);
278 
279 
280 				bind_pipeline(cmd_buffer, src_type, fs_key);
281 			} else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
282 				enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dst->current_layout);
283 				radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
284 							&(VkRenderPassBeginInfo) {
285 								.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
286 									.renderPass = device->meta_state.blit2d.depth_only_rp[ds_layout],
287 									.framebuffer = dst_temps.fb,
288 									.renderArea = {
289 									.offset = { rects[r].dst_x, rects[r].dst_y, },
290 									.extent = { rects[r].width, rects[r].height },
291 								},
292 									.clearValueCount = 0,
293 										.pClearValues = NULL,
294 										}, VK_SUBPASS_CONTENTS_INLINE);
295 
296 
297 				bind_depth_pipeline(cmd_buffer, src_type);
298 
299 			} else if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
300 				enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dst->current_layout);
301 				radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
302 							&(VkRenderPassBeginInfo) {
303 								.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
304 									.renderPass = device->meta_state.blit2d.stencil_only_rp[ds_layout],
305 									.framebuffer = dst_temps.fb,
306 									.renderArea = {
307 									.offset = { rects[r].dst_x, rects[r].dst_y, },
308 									.extent = { rects[r].width, rects[r].height },
309 								},
310 									.clearValueCount = 0,
311 										.pClearValues = NULL,
312 										}, VK_SUBPASS_CONTENTS_INLINE);
313 
314 
315 				bind_stencil_pipeline(cmd_buffer, src_type);
316 			} else
317 				unreachable("Processing blit2d with multiple aspects.");
318 
319 			radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
320 				.x = rects[r].dst_x,
321 				.y = rects[r].dst_y,
322 				.width = rects[r].width,
323 				.height = rects[r].height,
324 				.minDepth = 0.0f,
325 				.maxDepth = 1.0f
326 			});
327 
328 			radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
329 				.offset = (VkOffset2D) { rects[r].dst_x, rects[r].dst_y },
330 				.extent = (VkExtent2D) { rects[r].width, rects[r].height },
331 			});
332 
333 
334 
335 			radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
336 			radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
337 
338 			/* At the point where we emit the draw call, all data from the
339 			* descriptor sets, etc. has been used.  We are free to delete it.
340 			*/
341 			radv_DestroyFramebuffer(radv_device_to_handle(device),
342 						dst_temps.fb,
343 						&cmd_buffer->pool->alloc);
344 		}
345 	}
346 }
347 
348 void
radv_meta_blit2d(struct radv_cmd_buffer * cmd_buffer,struct radv_meta_blit2d_surf * src_img,struct radv_meta_blit2d_buffer * src_buf,struct radv_meta_blit2d_surf * dst,unsigned num_rects,struct radv_meta_blit2d_rect * rects)349 radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer,
350 		 struct radv_meta_blit2d_surf *src_img,
351 		 struct radv_meta_blit2d_buffer *src_buf,
352 		 struct radv_meta_blit2d_surf *dst,
353 		 unsigned num_rects,
354 		 struct radv_meta_blit2d_rect *rects)
355 {
356 	bool use_3d = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
357 		(src_img && src_img->image->type == VK_IMAGE_TYPE_3D);
358 	enum blit2d_src_type src_type = src_buf ? BLIT2D_SRC_TYPE_BUFFER :
359 		use_3d ? BLIT2D_SRC_TYPE_IMAGE_3D : BLIT2D_SRC_TYPE_IMAGE;
360 	radv_meta_blit2d_normal_dst(cmd_buffer, src_img, src_buf, dst,
361 				    num_rects, rects, src_type);
362 }
363 
364 static nir_shader *
build_nir_vertex_shader(void)365 build_nir_vertex_shader(void)
366 {
367 	const struct glsl_type *vec4 = glsl_vec4_type();
368 	const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
369 	nir_builder b;
370 
371 	nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
372 	b.shader->info.name = ralloc_strdup(b.shader, "meta_blit2d_vs");
373 
374 	nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
375 						    vec4, "gl_Position");
376 	pos_out->data.location = VARYING_SLOT_POS;
377 
378 	nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
379 							vec2, "v_tex_pos");
380 	tex_pos_out->data.location = VARYING_SLOT_VAR0;
381 	tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
382 
383 	nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
384 	nir_store_var(&b, pos_out, outvec, 0xf);
385 
386 	nir_intrinsic_instr *src_box = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
387 	src_box->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
388 	nir_intrinsic_set_base(src_box, 0);
389 	nir_intrinsic_set_range(src_box, 16);
390 	src_box->num_components = 4;
391 	nir_ssa_dest_init(&src_box->instr, &src_box->dest, 4, 32, "src_box");
392 	nir_builder_instr_insert(&b, &src_box->instr);
393 
394 	nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_vertex_id_zero_base);
395 	nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
396 	nir_builder_instr_insert(&b, &vertex_id->instr);
397 
398 	/* vertex 0 - src_x, src_y */
399 	/* vertex 1 - src_x, src_y+h */
400 	/* vertex 2 - src_x+w, src_y */
401 	/* so channel 0 is vertex_id != 2 ? src_x : src_x + w
402 	   channel 1 is vertex id != 1 ? src_y : src_y + w */
403 
404 	nir_ssa_def *c0cmp = nir_ine(&b, &vertex_id->dest.ssa,
405 				     nir_imm_int(&b, 2));
406 	nir_ssa_def *c1cmp = nir_ine(&b, &vertex_id->dest.ssa,
407 				     nir_imm_int(&b, 1));
408 
409 	nir_ssa_def *comp[2];
410 	comp[0] = nir_bcsel(&b, c0cmp,
411 			    nir_channel(&b, &src_box->dest.ssa, 0),
412 			    nir_channel(&b, &src_box->dest.ssa, 2));
413 
414 	comp[1] = nir_bcsel(&b, c1cmp,
415 			    nir_channel(&b, &src_box->dest.ssa, 1),
416 			    nir_channel(&b, &src_box->dest.ssa, 3));
417 	nir_ssa_def *out_tex_vec = nir_vec(&b, comp, 2);
418 	nir_store_var(&b, tex_pos_out, out_tex_vec, 0x3);
419 	return b.shader;
420 }
421 
422 typedef nir_ssa_def* (*texel_fetch_build_func)(struct nir_builder *,
423                                                struct radv_device *,
424                                                nir_ssa_def *, bool);
425 
426 static nir_ssa_def *
build_nir_texel_fetch(struct nir_builder * b,struct radv_device * device,nir_ssa_def * tex_pos,bool is_3d)427 build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
428                       nir_ssa_def *tex_pos, bool is_3d)
429 {
430 	enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D;
431 	const struct glsl_type *sampler_type =
432 		glsl_sampler_type(dim, false, false, GLSL_TYPE_UINT);
433 	nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
434 						    sampler_type, "s_tex");
435 	sampler->data.descriptor_set = 0;
436 	sampler->data.binding = 0;
437 
438 	nir_ssa_def *tex_pos_3d = NULL;
439 	if (is_3d) {
440 		nir_intrinsic_instr *layer = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
441 		nir_intrinsic_set_base(layer, 16);
442 		nir_intrinsic_set_range(layer, 4);
443 		layer->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
444 		layer->num_components = 1;
445 		nir_ssa_dest_init(&layer->instr, &layer->dest, 1, 32, "layer");
446 		nir_builder_instr_insert(b, &layer->instr);
447 
448 		nir_ssa_def *chans[3];
449 		chans[0] = nir_channel(b, tex_pos, 0);
450 		chans[1] = nir_channel(b, tex_pos, 1);
451 		chans[2] = &layer->dest.ssa;
452 		tex_pos_3d = nir_vec(b, chans, 3);
453 	}
454 	nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
455 	tex->sampler_dim = dim;
456 	tex->op = nir_texop_txf;
457 	tex->src[0].src_type = nir_tex_src_coord;
458 	tex->src[0].src = nir_src_for_ssa(is_3d ? tex_pos_3d : tex_pos);
459 	tex->src[1].src_type = nir_tex_src_lod;
460 	tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
461 	tex->dest_type = nir_type_uint;
462 	tex->is_array = false;
463 	tex->coord_components = is_3d ? 3 : 2;
464 	tex->texture = nir_deref_var_create(tex, sampler);
465 	tex->sampler = NULL;
466 
467 	nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
468 	nir_builder_instr_insert(b, &tex->instr);
469 
470 	return &tex->dest.ssa;
471 }
472 
473 
474 static nir_ssa_def *
build_nir_buffer_fetch(struct nir_builder * b,struct radv_device * device,nir_ssa_def * tex_pos,bool is_3d)475 build_nir_buffer_fetch(struct nir_builder *b, struct radv_device *device,
476 		       nir_ssa_def *tex_pos, bool is_3d)
477 {
478 	const struct glsl_type *sampler_type =
479 		glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_UINT);
480 	nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
481 						    sampler_type, "s_tex");
482 	sampler->data.descriptor_set = 0;
483 	sampler->data.binding = 0;
484 
485 	nir_intrinsic_instr *width = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
486 	nir_intrinsic_set_base(width, 16);
487 	nir_intrinsic_set_range(width, 4);
488 	width->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
489 	width->num_components = 1;
490 	nir_ssa_dest_init(&width->instr, &width->dest, 1, 32, "width");
491 	nir_builder_instr_insert(b, &width->instr);
492 
493 	nir_ssa_def *pos_x = nir_channel(b, tex_pos, 0);
494 	nir_ssa_def *pos_y = nir_channel(b, tex_pos, 1);
495 	pos_y = nir_imul(b, pos_y, &width->dest.ssa);
496 	pos_x = nir_iadd(b, pos_x, pos_y);
497 	//pos_x = nir_iadd(b, pos_x, nir_imm_int(b, 100000));
498 
499 	nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);
500 	tex->sampler_dim = GLSL_SAMPLER_DIM_BUF;
501 	tex->op = nir_texop_txf;
502 	tex->src[0].src_type = nir_tex_src_coord;
503 	tex->src[0].src = nir_src_for_ssa(pos_x);
504 	tex->dest_type = nir_type_uint;
505 	tex->is_array = false;
506 	tex->coord_components = 1;
507 	tex->texture = nir_deref_var_create(tex, sampler);
508 	tex->sampler = NULL;
509 
510 	nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
511 	nir_builder_instr_insert(b, &tex->instr);
512 
513 	return &tex->dest.ssa;
514 }
515 
516 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
517 	.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
518 	.vertexBindingDescriptionCount = 0,
519 	.vertexAttributeDescriptionCount = 0,
520 };
521 
522 static nir_shader *
build_nir_copy_fragment_shader(struct radv_device * device,texel_fetch_build_func txf_func,const char * name,bool is_3d)523 build_nir_copy_fragment_shader(struct radv_device *device,
524                                texel_fetch_build_func txf_func, const char* name, bool is_3d)
525 {
526 	const struct glsl_type *vec4 = glsl_vec4_type();
527 	const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
528 	nir_builder b;
529 
530 	nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
531 	b.shader->info.name = ralloc_strdup(b.shader, name);
532 
533 	nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
534 						       vec2, "v_tex_pos");
535 	tex_pos_in->data.location = VARYING_SLOT_VAR0;
536 
537 	nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
538 						      vec4, "f_color");
539 	color_out->data.location = FRAG_RESULT_DATA0;
540 
541 	nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
542 	unsigned swiz[4] = { 0, 1 };
543 	nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
544 
545 	nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d);
546 	nir_store_var(&b, color_out, color, 0xf);
547 
548 	return b.shader;
549 }
550 
551 static nir_shader *
build_nir_copy_fragment_shader_depth(struct radv_device * device,texel_fetch_build_func txf_func,const char * name,bool is_3d)552 build_nir_copy_fragment_shader_depth(struct radv_device *device,
553 				     texel_fetch_build_func txf_func, const char* name, bool is_3d)
554 {
555 	const struct glsl_type *vec4 = glsl_vec4_type();
556 	const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
557 	nir_builder b;
558 
559 	nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
560 	b.shader->info.name = ralloc_strdup(b.shader, name);
561 
562 	nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
563 						       vec2, "v_tex_pos");
564 	tex_pos_in->data.location = VARYING_SLOT_VAR0;
565 
566 	nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
567 						      vec4, "f_color");
568 	color_out->data.location = FRAG_RESULT_DEPTH;
569 
570 	nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
571 	unsigned swiz[4] = { 0, 1 };
572 	nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
573 
574 	nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d);
575 	nir_store_var(&b, color_out, color, 0x1);
576 
577 	return b.shader;
578 }
579 
580 static nir_shader *
build_nir_copy_fragment_shader_stencil(struct radv_device * device,texel_fetch_build_func txf_func,const char * name,bool is_3d)581 build_nir_copy_fragment_shader_stencil(struct radv_device *device,
582 				       texel_fetch_build_func txf_func, const char* name, bool is_3d)
583 {
584 	const struct glsl_type *vec4 = glsl_vec4_type();
585 	const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
586 	nir_builder b;
587 
588 	nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
589 	b.shader->info.name = ralloc_strdup(b.shader, name);
590 
591 	nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
592 						       vec2, "v_tex_pos");
593 	tex_pos_in->data.location = VARYING_SLOT_VAR0;
594 
595 	nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
596 						      vec4, "f_color");
597 	color_out->data.location = FRAG_RESULT_STENCIL;
598 
599 	nir_ssa_def *pos_int = nir_f2i32(&b, nir_load_var(&b, tex_pos_in));
600 	unsigned swiz[4] = { 0, 1 };
601 	nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
602 
603 	nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d);
604 	nir_store_var(&b, color_out, color, 0x1);
605 
606 	return b.shader;
607 }
608 
609 void
radv_device_finish_meta_blit2d_state(struct radv_device * device)610 radv_device_finish_meta_blit2d_state(struct radv_device *device)
611 {
612 	struct radv_meta_state *state = &device->meta_state;
613 
614 	for(unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
615 		for (unsigned k = 0; k < RADV_META_DST_LAYOUT_COUNT; ++k) {
616 			radv_DestroyRenderPass(radv_device_to_handle(device),
617 			                       state->blit2d.render_passes[j][k],
618 			                       &state->alloc);
619 		}
620 	}
621 
622 	for (enum radv_blit_ds_layout j = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; j < RADV_BLIT_DS_LAYOUT_COUNT; j++) {
623 		radv_DestroyRenderPass(radv_device_to_handle(device),
624 				       state->blit2d.depth_only_rp[j], &state->alloc);
625 		radv_DestroyRenderPass(radv_device_to_handle(device),
626 				       state->blit2d.stencil_only_rp[j], &state->alloc);
627 	}
628 
629 	for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
630 		radv_DestroyPipelineLayout(radv_device_to_handle(device),
631 					   state->blit2d.p_layouts[src],
632 					   &state->alloc);
633 		radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
634 						state->blit2d.ds_layouts[src],
635 						&state->alloc);
636 
637 		for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
638 			radv_DestroyPipeline(radv_device_to_handle(device),
639 					     state->blit2d.pipelines[src][j],
640 					     &state->alloc);
641 		}
642 
643 		radv_DestroyPipeline(radv_device_to_handle(device),
644 				     state->blit2d.depth_only_pipeline[src],
645 				     &state->alloc);
646 		radv_DestroyPipeline(radv_device_to_handle(device),
647 				     state->blit2d.stencil_only_pipeline[src],
648 				     &state->alloc);
649 	}
650 }
651 
652 static VkResult
blit2d_init_color_pipeline(struct radv_device * device,enum blit2d_src_type src_type,VkFormat format)653 blit2d_init_color_pipeline(struct radv_device *device,
654 			   enum blit2d_src_type src_type,
655 			   VkFormat format)
656 {
657 	VkResult result;
658 	unsigned fs_key = radv_format_meta_fs_key(format);
659 	const char *name;
660 
661 	texel_fetch_build_func src_func;
662 	switch(src_type) {
663 	case BLIT2D_SRC_TYPE_IMAGE:
664 		src_func = build_nir_texel_fetch;
665 		name = "meta_blit2d_image_fs";
666 		break;
667 	case BLIT2D_SRC_TYPE_IMAGE_3D:
668 		src_func = build_nir_texel_fetch;
669 		name = "meta_blit3d_image_fs";
670 		break;
671 	case BLIT2D_SRC_TYPE_BUFFER:
672 		src_func = build_nir_buffer_fetch;
673 		name = "meta_blit2d_buffer_fs";
674 		break;
675 	default:
676 		unreachable("unknown blit src type\n");
677 		break;
678 	}
679 
680 	const VkPipelineVertexInputStateCreateInfo *vi_create_info;
681 	struct radv_shader_module fs = { .nir = NULL };
682 
683 
684 	fs.nir = build_nir_copy_fragment_shader(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D);
685 	vi_create_info = &normal_vi_create_info;
686 
687 	struct radv_shader_module vs = {
688 		.nir = build_nir_vertex_shader(),
689 	};
690 
691 	VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
692 		{
693 			.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
694 			.stage = VK_SHADER_STAGE_VERTEX_BIT,
695 			.module = radv_shader_module_to_handle(&vs),
696 			.pName = "main",
697 			.pSpecializationInfo = NULL
698 		}, {
699 			.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
700 			.stage = VK_SHADER_STAGE_FRAGMENT_BIT,
701 			.module = radv_shader_module_to_handle(&fs),
702 			.pName = "main",
703 			.pSpecializationInfo = NULL
704 		},
705 	};
706 
707 	for (unsigned dst_layout = 0; dst_layout < RADV_META_DST_LAYOUT_COUNT; ++dst_layout) {
708 		if (!device->meta_state.blit2d.render_passes[fs_key][dst_layout]) {
709 			VkImageLayout layout = radv_meta_dst_layout_to_layout(dst_layout);
710 
711 			result = radv_CreateRenderPass(radv_device_to_handle(device),
712 						&(VkRenderPassCreateInfo) {
713 							.sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
714 							.attachmentCount = 1,
715 							.pAttachments = &(VkAttachmentDescription) {
716 							.format = format,
717 							.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
718 							.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
719 							.initialLayout = layout,
720 							.finalLayout = layout,
721 							},
722 						.subpassCount = 1,
723 						.pSubpasses = &(VkSubpassDescription) {
724 							.pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
725 							.inputAttachmentCount = 0,
726 							.colorAttachmentCount = 1,
727 							.pColorAttachments = &(VkAttachmentReference) {
728 								.attachment = 0,
729 								.layout = layout,
730 								},
731 						.pResolveAttachments = NULL,
732 						.pDepthStencilAttachment = &(VkAttachmentReference) {
733 							.attachment = VK_ATTACHMENT_UNUSED,
734 							.layout = layout,
735 						},
736 						.preserveAttachmentCount = 1,
737 						.pPreserveAttachments = (uint32_t[]) { 0 },
738 						},
739 						.dependencyCount = 0,
740 					}, &device->meta_state.alloc, &device->meta_state.blit2d.render_passes[fs_key][dst_layout]);
741 		}
742 	}
743 
744 	const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
745 		.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
746 		.stageCount = ARRAY_SIZE(pipeline_shader_stages),
747 		.pStages = pipeline_shader_stages,
748 		.pVertexInputState = vi_create_info,
749 		.pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
750 			.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
751 			.topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
752 			.primitiveRestartEnable = false,
753 		},
754 		.pViewportState = &(VkPipelineViewportStateCreateInfo) {
755 			.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
756 			.viewportCount = 1,
757 			.scissorCount = 1,
758 		},
759 		.pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
760 			.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
761 			.rasterizerDiscardEnable = false,
762 			.polygonMode = VK_POLYGON_MODE_FILL,
763 			.cullMode = VK_CULL_MODE_NONE,
764 			.frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
765 		},
766 		.pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
767 			.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
768 			.rasterizationSamples = 1,
769 			.sampleShadingEnable = false,
770 			.pSampleMask = (VkSampleMask[]) { UINT32_MAX },
771 		},
772 		.pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
773 			.sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
774 			.attachmentCount = 1,
775 			.pAttachments = (VkPipelineColorBlendAttachmentState []) {
776 				{ .colorWriteMask =
777 				  VK_COLOR_COMPONENT_A_BIT |
778 				  VK_COLOR_COMPONENT_R_BIT |
779 				  VK_COLOR_COMPONENT_G_BIT |
780 				  VK_COLOR_COMPONENT_B_BIT },
781 			}
782 		},
783 		.pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
784 			.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
785 			.dynamicStateCount = 9,
786 			.pDynamicStates = (VkDynamicState[]) {
787 				VK_DYNAMIC_STATE_VIEWPORT,
788 				VK_DYNAMIC_STATE_SCISSOR,
789 				VK_DYNAMIC_STATE_LINE_WIDTH,
790 				VK_DYNAMIC_STATE_DEPTH_BIAS,
791 				VK_DYNAMIC_STATE_BLEND_CONSTANTS,
792 				VK_DYNAMIC_STATE_DEPTH_BOUNDS,
793 				VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
794 				VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
795 				VK_DYNAMIC_STATE_STENCIL_REFERENCE,
796 			},
797 		},
798 		.flags = 0,
799 		.layout = device->meta_state.blit2d.p_layouts[src_type],
800 		.renderPass = device->meta_state.blit2d.render_passes[fs_key][0],
801 		.subpass = 0,
802 	};
803 
804 	const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
805 		.use_rectlist = true
806 	};
807 
808 	result = radv_graphics_pipeline_create(radv_device_to_handle(device),
809 					       radv_pipeline_cache_to_handle(&device->meta_state.cache),
810 					       &vk_pipeline_info, &radv_pipeline_info,
811 					       &device->meta_state.alloc,
812 					       &device->meta_state.blit2d.pipelines[src_type][fs_key]);
813 
814 
815 	ralloc_free(vs.nir);
816 	ralloc_free(fs.nir);
817 
818 	return result;
819 }
820 
821 static VkResult
blit2d_init_depth_only_pipeline(struct radv_device * device,enum blit2d_src_type src_type)822 blit2d_init_depth_only_pipeline(struct radv_device *device,
823 				enum blit2d_src_type src_type)
824 {
825 	VkResult result;
826 	const char *name;
827 
828 	texel_fetch_build_func src_func;
829 	switch(src_type) {
830 	case BLIT2D_SRC_TYPE_IMAGE:
831 		src_func = build_nir_texel_fetch;
832 		name = "meta_blit2d_depth_image_fs";
833 		break;
834 	case BLIT2D_SRC_TYPE_IMAGE_3D:
835 		src_func = build_nir_texel_fetch;
836 		name = "meta_blit3d_depth_image_fs";
837 		break;
838 	case BLIT2D_SRC_TYPE_BUFFER:
839 		src_func = build_nir_buffer_fetch;
840 		name = "meta_blit2d_depth_buffer_fs";
841 		break;
842 	default:
843 		unreachable("unknown blit src type\n");
844 		break;
845 	}
846 
847 	const VkPipelineVertexInputStateCreateInfo *vi_create_info;
848 	struct radv_shader_module fs = { .nir = NULL };
849 
850 	fs.nir = build_nir_copy_fragment_shader_depth(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D);
851 	vi_create_info = &normal_vi_create_info;
852 
853 	struct radv_shader_module vs = {
854 		.nir = build_nir_vertex_shader(),
855 	};
856 
857 	VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
858 		{
859 			.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
860 			.stage = VK_SHADER_STAGE_VERTEX_BIT,
861 			.module = radv_shader_module_to_handle(&vs),
862 			.pName = "main",
863 			.pSpecializationInfo = NULL
864 		}, {
865 			.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
866 			.stage = VK_SHADER_STAGE_FRAGMENT_BIT,
867 			.module = radv_shader_module_to_handle(&fs),
868 			.pName = "main",
869 			.pSpecializationInfo = NULL
870 		},
871 	};
872 
873 	for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
874 		if (!device->meta_state.blit2d.depth_only_rp[ds_layout]) {
875 			VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
876 			result = radv_CreateRenderPass(radv_device_to_handle(device),
877 						       &(VkRenderPassCreateInfo) {
878 							       .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
879 							       .attachmentCount = 1,
880 							       .pAttachments = &(VkAttachmentDescription) {
881 								       .format = VK_FORMAT_D32_SFLOAT,
882 								       .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
883 								       .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
884 								       .initialLayout = layout,
885 								       .finalLayout = layout,
886 							       },
887 							       .subpassCount = 1,
888 							       .pSubpasses = &(VkSubpassDescription) {
889 								       .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
890 								       .inputAttachmentCount = 0,
891 								       .colorAttachmentCount = 0,
892 								       .pColorAttachments = NULL,
893 								       .pResolveAttachments = NULL,
894 								       .pDepthStencilAttachment = &(VkAttachmentReference) {
895 									       .attachment = 0,
896 									       .layout = layout,
897 								       },
898 								       .preserveAttachmentCount = 1,
899 								       .pPreserveAttachments = (uint32_t[]) { 0 },
900 							       },
901 							       .dependencyCount = 0,
902 							}, &device->meta_state.alloc, &device->meta_state.blit2d.depth_only_rp[ds_layout]);
903 		}
904 	}
905 
906 	const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
907 		.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
908 		.stageCount = ARRAY_SIZE(pipeline_shader_stages),
909 		.pStages = pipeline_shader_stages,
910 		.pVertexInputState = vi_create_info,
911 		.pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
912 			.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
913 			.topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
914 			.primitiveRestartEnable = false,
915 		},
916 		.pViewportState = &(VkPipelineViewportStateCreateInfo) {
917 			.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
918 			.viewportCount = 1,
919 			.scissorCount = 1,
920 		},
921 		.pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
922 			.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
923 			.rasterizerDiscardEnable = false,
924 			.polygonMode = VK_POLYGON_MODE_FILL,
925 			.cullMode = VK_CULL_MODE_NONE,
926 			.frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
927 		},
928 		.pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
929 			.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
930 			.rasterizationSamples = 1,
931 			.sampleShadingEnable = false,
932 			.pSampleMask = (VkSampleMask[]) { UINT32_MAX },
933 		},
934 		.pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
935 			.sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
936 			.attachmentCount = 0,
937 			.pAttachments = NULL,
938 		},
939 		.pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
940 			.sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
941 			.depthTestEnable = true,
942 			.depthWriteEnable = true,
943 			.depthCompareOp = VK_COMPARE_OP_ALWAYS,
944 		},
945 		.pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
946 			.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
947 			.dynamicStateCount = 9,
948 			.pDynamicStates = (VkDynamicState[]) {
949 				VK_DYNAMIC_STATE_VIEWPORT,
950 				VK_DYNAMIC_STATE_SCISSOR,
951 				VK_DYNAMIC_STATE_LINE_WIDTH,
952 				VK_DYNAMIC_STATE_DEPTH_BIAS,
953 				VK_DYNAMIC_STATE_BLEND_CONSTANTS,
954 				VK_DYNAMIC_STATE_DEPTH_BOUNDS,
955 				VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
956 				VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
957 				VK_DYNAMIC_STATE_STENCIL_REFERENCE,
958 			},
959 		},
960 		.flags = 0,
961 		.layout = device->meta_state.blit2d.p_layouts[src_type],
962 		.renderPass = device->meta_state.blit2d.depth_only_rp[0],
963 		.subpass = 0,
964 	};
965 
966 	const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
967 		.use_rectlist = true
968 	};
969 
970 	result = radv_graphics_pipeline_create(radv_device_to_handle(device),
971 					       radv_pipeline_cache_to_handle(&device->meta_state.cache),
972 					       &vk_pipeline_info, &radv_pipeline_info,
973 					       &device->meta_state.alloc,
974 					       &device->meta_state.blit2d.depth_only_pipeline[src_type]);
975 
976 
977 	ralloc_free(vs.nir);
978 	ralloc_free(fs.nir);
979 
980 	return result;
981 }
982 
983 static VkResult
blit2d_init_stencil_only_pipeline(struct radv_device * device,enum blit2d_src_type src_type)984 blit2d_init_stencil_only_pipeline(struct radv_device *device,
985 				  enum blit2d_src_type src_type)
986 {
987 	VkResult result;
988 	const char *name;
989 
990 	texel_fetch_build_func src_func;
991 	switch(src_type) {
992 	case BLIT2D_SRC_TYPE_IMAGE:
993 		src_func = build_nir_texel_fetch;
994 		name = "meta_blit2d_stencil_image_fs";
995 		break;
996 	case BLIT2D_SRC_TYPE_IMAGE_3D:
997 		src_func = build_nir_texel_fetch;
998 		name = "meta_blit3d_stencil_image_fs";
999 		break;
1000 	case BLIT2D_SRC_TYPE_BUFFER:
1001 		src_func = build_nir_buffer_fetch;
1002 		name = "meta_blit2d_stencil_buffer_fs";
1003 		break;
1004 	default:
1005 		unreachable("unknown blit src type\n");
1006 		break;
1007 	}
1008 
1009 	const VkPipelineVertexInputStateCreateInfo *vi_create_info;
1010 	struct radv_shader_module fs = { .nir = NULL };
1011 
1012 	fs.nir = build_nir_copy_fragment_shader_stencil(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D);
1013 	vi_create_info = &normal_vi_create_info;
1014 
1015 	struct radv_shader_module vs = {
1016 		.nir = build_nir_vertex_shader(),
1017 	};
1018 
1019 	VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1020 		{
1021 			.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1022 			.stage = VK_SHADER_STAGE_VERTEX_BIT,
1023 			.module = radv_shader_module_to_handle(&vs),
1024 			.pName = "main",
1025 			.pSpecializationInfo = NULL
1026 		}, {
1027 			.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1028 			.stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1029 			.module = radv_shader_module_to_handle(&fs),
1030 			.pName = "main",
1031 			.pSpecializationInfo = NULL
1032 		},
1033 	};
1034 
1035 	for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
1036 		if (!device->meta_state.blit2d.stencil_only_rp[ds_layout]) {
1037 			VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
1038 			result = radv_CreateRenderPass(radv_device_to_handle(device),
1039 						       &(VkRenderPassCreateInfo) {
1040 							       .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1041 							       .attachmentCount = 1,
1042 							       .pAttachments = &(VkAttachmentDescription) {
1043 								       .format = VK_FORMAT_S8_UINT,
1044 								       .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1045 								       .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1046 								       .initialLayout = layout,
1047 								       .finalLayout = layout,
1048 							       },
1049 							       .subpassCount = 1,
1050 							       .pSubpasses = &(VkSubpassDescription) {
1051 								       .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1052 								       .inputAttachmentCount = 0,
1053 								       .colorAttachmentCount = 0,
1054 								       .pColorAttachments = NULL,
1055 								       .pResolveAttachments = NULL,
1056 								       .pDepthStencilAttachment = &(VkAttachmentReference) {
1057 									       .attachment = 0,
1058 									       .layout = layout,
1059 								       },
1060 								       .preserveAttachmentCount = 1,
1061 								       .pPreserveAttachments = (uint32_t[]) { 0 },
1062 							       },
1063 							       .dependencyCount = 0,
1064 						       }, &device->meta_state.alloc, &device->meta_state.blit2d.stencil_only_rp[ds_layout]);
1065 		}
1066 	}
1067 
1068 	const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1069 		.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1070 		.stageCount = ARRAY_SIZE(pipeline_shader_stages),
1071 		.pStages = pipeline_shader_stages,
1072 		.pVertexInputState = vi_create_info,
1073 		.pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1074 			.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1075 			.topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1076 			.primitiveRestartEnable = false,
1077 		},
1078 		.pViewportState = &(VkPipelineViewportStateCreateInfo) {
1079 			.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1080 			.viewportCount = 1,
1081 			.scissorCount = 1,
1082 		},
1083 		.pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1084 			.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1085 			.rasterizerDiscardEnable = false,
1086 			.polygonMode = VK_POLYGON_MODE_FILL,
1087 			.cullMode = VK_CULL_MODE_NONE,
1088 			.frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1089 		},
1090 		.pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1091 			.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1092 			.rasterizationSamples = 1,
1093 			.sampleShadingEnable = false,
1094 			.pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1095 		},
1096 		.pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1097 			.sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1098 			.attachmentCount = 0,
1099 			.pAttachments = NULL,
1100 		},
1101 		.pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1102 			.sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1103 			.depthTestEnable = false,
1104 			.depthWriteEnable = false,
1105 			.stencilTestEnable = true,
1106 			.front = {
1107 				.failOp = VK_STENCIL_OP_REPLACE,
1108 				.passOp = VK_STENCIL_OP_REPLACE,
1109 				.depthFailOp = VK_STENCIL_OP_REPLACE,
1110 				.compareOp = VK_COMPARE_OP_ALWAYS,
1111 				.compareMask = 0xff,
1112 				.writeMask = 0xff,
1113 				.reference = 0
1114 			},
1115 			.back = {
1116 				.failOp = VK_STENCIL_OP_REPLACE,
1117 				.passOp = VK_STENCIL_OP_REPLACE,
1118 				.depthFailOp = VK_STENCIL_OP_REPLACE,
1119 				.compareOp = VK_COMPARE_OP_ALWAYS,
1120 				.compareMask = 0xff,
1121 				.writeMask = 0xff,
1122 				.reference = 0
1123 			},
1124 			.depthCompareOp = VK_COMPARE_OP_ALWAYS,
1125 		},
1126 		.pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1127 			.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1128 			.dynamicStateCount = 6,
1129 			.pDynamicStates = (VkDynamicState[]) {
1130 				VK_DYNAMIC_STATE_VIEWPORT,
1131 				VK_DYNAMIC_STATE_SCISSOR,
1132 				VK_DYNAMIC_STATE_LINE_WIDTH,
1133 				VK_DYNAMIC_STATE_DEPTH_BIAS,
1134 				VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1135 				VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1136 			},
1137 		},
1138 		.flags = 0,
1139 		.layout = device->meta_state.blit2d.p_layouts[src_type],
1140 		.renderPass = device->meta_state.blit2d.stencil_only_rp[0],
1141 		.subpass = 0,
1142 	};
1143 
1144 	const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1145 		.use_rectlist = true
1146 	};
1147 
1148 	result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1149 					       radv_pipeline_cache_to_handle(&device->meta_state.cache),
1150 					       &vk_pipeline_info, &radv_pipeline_info,
1151 					       &device->meta_state.alloc,
1152 					       &device->meta_state.blit2d.stencil_only_pipeline[src_type]);
1153 
1154 
1155 	ralloc_free(vs.nir);
1156 	ralloc_free(fs.nir);
1157 
1158 	return result;
1159 }
1160 
1161 static VkFormat pipeline_formats[] = {
1162    VK_FORMAT_R8G8B8A8_UNORM,
1163    VK_FORMAT_R8G8B8A8_UINT,
1164    VK_FORMAT_R8G8B8A8_SINT,
1165    VK_FORMAT_A2R10G10B10_UINT_PACK32,
1166    VK_FORMAT_A2R10G10B10_SINT_PACK32,
1167    VK_FORMAT_R16G16B16A16_UNORM,
1168    VK_FORMAT_R16G16B16A16_SNORM,
1169    VK_FORMAT_R16G16B16A16_UINT,
1170    VK_FORMAT_R16G16B16A16_SINT,
1171    VK_FORMAT_R32_SFLOAT,
1172    VK_FORMAT_R32G32_SFLOAT,
1173    VK_FORMAT_R32G32B32A32_SFLOAT
1174 };
1175 
1176 static VkResult
meta_blit2d_create_pipe_layout(struct radv_device * device,int idx)1177 meta_blit2d_create_pipe_layout(struct radv_device *device,
1178 			       int idx)
1179 {
1180 	VkResult result;
1181 	VkDescriptorType desc_type = (idx == BLIT2D_SRC_TYPE_BUFFER) ? VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER : VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE;
1182 	const VkPushConstantRange push_constant_ranges[] = {
1183 		{VK_SHADER_STAGE_VERTEX_BIT, 0, 16},
1184 		{VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4},
1185 	};
1186 	int num_push_constant_range = (idx != BLIT2D_SRC_TYPE_IMAGE) ? 2 : 1;
1187 
1188 	result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1189 						&(VkDescriptorSetLayoutCreateInfo) {
1190 							.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1191 							.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1192 							.bindingCount = 1,
1193 							.pBindings = (VkDescriptorSetLayoutBinding[]) {
1194 							{
1195 								.binding = 0,
1196 								.descriptorType = desc_type,
1197 								.descriptorCount = 1,
1198 								.stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1199 								.pImmutableSamplers = NULL
1200 							},
1201 							}
1202 						}, &device->meta_state.alloc, &device->meta_state.blit2d.ds_layouts[idx]);
1203 	if (result != VK_SUCCESS)
1204 		goto fail;
1205 
1206 	result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1207 					   &(VkPipelineLayoutCreateInfo) {
1208 						   .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1209 							   .setLayoutCount = 1,
1210 							   .pSetLayouts = &device->meta_state.blit2d.ds_layouts[idx],
1211 							   .pushConstantRangeCount = num_push_constant_range,
1212 							   .pPushConstantRanges = push_constant_ranges,
1213 							   },
1214 					   &device->meta_state.alloc, &device->meta_state.blit2d.p_layouts[idx]);
1215 	if (result != VK_SUCCESS)
1216 		goto fail;
1217 	return VK_SUCCESS;
1218 fail:
1219 	return result;
1220 }
1221 
1222 VkResult
radv_device_init_meta_blit2d_state(struct radv_device * device)1223 radv_device_init_meta_blit2d_state(struct radv_device *device)
1224 {
1225 	VkResult result;
1226 	bool create_3d = device->physical_device->rad_info.chip_class >= GFX9;
1227 
1228 	for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
1229 		if (src == BLIT2D_SRC_TYPE_IMAGE_3D && !create_3d)
1230 			continue;
1231 
1232 		result = meta_blit2d_create_pipe_layout(device, src);
1233 		if (result != VK_SUCCESS)
1234 			goto fail;
1235 
1236 		for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
1237 			result = blit2d_init_color_pipeline(device, src, pipeline_formats[j]);
1238 			if (result != VK_SUCCESS)
1239 				goto fail;
1240 		}
1241 
1242 		result = blit2d_init_depth_only_pipeline(device, src);
1243 		if (result != VK_SUCCESS)
1244 			goto fail;
1245 
1246 		result = blit2d_init_stencil_only_pipeline(device, src);
1247 		if (result != VK_SUCCESS)
1248 			goto fail;
1249 	}
1250 
1251 	return VK_SUCCESS;
1252 
1253 fail:
1254 	radv_device_finish_meta_blit2d_state(device);
1255 	return result;
1256 }
1257