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1 /*
2  * Copyright © 2015 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #include "radv_meta.h"
25 #include "nir/nir_builder.h"
26 
27 struct blit_region {
28 	VkOffset3D src_offset;
29 	VkExtent3D src_extent;
30 	VkOffset3D dest_offset;
31 	VkExtent3D dest_extent;
32 };
33 
34 static nir_shader *
build_nir_vertex_shader(void)35 build_nir_vertex_shader(void)
36 {
37 	const struct glsl_type *vec4 = glsl_vec4_type();
38 	nir_builder b;
39 
40 	nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
41 	b.shader->info.name = ralloc_strdup(b.shader, "meta_blit_vs");
42 
43 	nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
44 						    vec4, "gl_Position");
45 	pos_out->data.location = VARYING_SLOT_POS;
46 
47 	nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
48 							vec4, "v_tex_pos");
49 	tex_pos_out->data.location = VARYING_SLOT_VAR0;
50 	tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
51 
52 	nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
53 
54 	nir_store_var(&b, pos_out, outvec, 0xf);
55 
56 	nir_intrinsic_instr *src_box = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
57 	src_box->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
58 	nir_intrinsic_set_base(src_box, 0);
59 	nir_intrinsic_set_range(src_box, 16);
60 	src_box->num_components = 4;
61 	nir_ssa_dest_init(&src_box->instr, &src_box->dest, 4, 32, "src_box");
62 	nir_builder_instr_insert(&b, &src_box->instr);
63 
64 	nir_intrinsic_instr *src0_z = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
65 	src0_z->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
66 	nir_intrinsic_set_base(src0_z, 16);
67 	nir_intrinsic_set_range(src0_z, 4);
68 	src0_z->num_components = 1;
69 	nir_ssa_dest_init(&src0_z->instr, &src0_z->dest, 1, 32, "src0_z");
70 	nir_builder_instr_insert(&b, &src0_z->instr);
71 
72 	nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_vertex_id_zero_base);
73 	nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
74 	nir_builder_instr_insert(&b, &vertex_id->instr);
75 
76 	/* vertex 0 - src0_x, src0_y, src0_z */
77 	/* vertex 1 - src0_x, src1_y, src0_z*/
78 	/* vertex 2 - src1_x, src0_y, src0_z */
79 	/* so channel 0 is vertex_id != 2 ? src_x : src_x + w
80 	   channel 1 is vertex id != 1 ? src_y : src_y + w */
81 
82 	nir_ssa_def *c0cmp = nir_ine(&b, &vertex_id->dest.ssa,
83 				     nir_imm_int(&b, 2));
84 	nir_ssa_def *c1cmp = nir_ine(&b, &vertex_id->dest.ssa,
85 				     nir_imm_int(&b, 1));
86 
87 	nir_ssa_def *comp[4];
88 	comp[0] = nir_bcsel(&b, c0cmp,
89 			    nir_channel(&b, &src_box->dest.ssa, 0),
90 			    nir_channel(&b, &src_box->dest.ssa, 2));
91 
92 	comp[1] = nir_bcsel(&b, c1cmp,
93 			    nir_channel(&b, &src_box->dest.ssa, 1),
94 			    nir_channel(&b, &src_box->dest.ssa, 3));
95 	comp[2] = &src0_z->dest.ssa;
96 	comp[3] = nir_imm_float(&b, 1.0);
97 	nir_ssa_def *out_tex_vec = nir_vec(&b, comp, 4);
98 	nir_store_var(&b, tex_pos_out, out_tex_vec, 0xf);
99 	return b.shader;
100 }
101 
102 static nir_shader *
build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim)103 build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim)
104 {
105 	char shader_name[64];
106 	const struct glsl_type *vec4 = glsl_vec4_type();
107 	nir_builder b;
108 
109 	nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
110 
111 	sprintf(shader_name, "meta_blit_fs.%d", tex_dim);
112 	b.shader->info.name = ralloc_strdup(b.shader, shader_name);
113 
114 	nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
115 						       vec4, "v_tex_pos");
116 	tex_pos_in->data.location = VARYING_SLOT_VAR0;
117 
118 	/* Swizzle the array index which comes in as Z coordinate into the right
119 	 * position.
120 	 */
121 	unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
122 	nir_ssa_def *const tex_pos =
123 		nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
124 			    (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
125 
126 	const struct glsl_type *sampler_type =
127 		glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
128 				  glsl_get_base_type(vec4));
129 	nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
130 						    sampler_type, "s_tex");
131 	sampler->data.descriptor_set = 0;
132 	sampler->data.binding = 0;
133 
134 	nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
135 	tex->sampler_dim = tex_dim;
136 	tex->op = nir_texop_tex;
137 	tex->src[0].src_type = nir_tex_src_coord;
138 	tex->src[0].src = nir_src_for_ssa(tex_pos);
139 	tex->dest_type = nir_type_float; /* TODO */
140 	tex->is_array = glsl_sampler_type_is_array(sampler_type);
141 	tex->coord_components = tex_pos->num_components;
142 	tex->texture = nir_deref_var_create(tex, sampler);
143 	tex->sampler = nir_deref_var_create(tex, sampler);
144 
145 	nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
146 	nir_builder_instr_insert(&b, &tex->instr);
147 
148 	nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
149 						      vec4, "f_color");
150 	color_out->data.location = FRAG_RESULT_DATA0;
151 	nir_store_var(&b, color_out, &tex->dest.ssa, 0xf);
152 
153 	return b.shader;
154 }
155 
156 static nir_shader *
build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)157 build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)
158 {
159 	char shader_name[64];
160 	const struct glsl_type *vec4 = glsl_vec4_type();
161 	nir_builder b;
162 
163 	nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
164 
165 	sprintf(shader_name, "meta_blit_depth_fs.%d", tex_dim);
166 	b.shader->info.name = ralloc_strdup(b.shader, shader_name);
167 
168 	nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
169 						       vec4, "v_tex_pos");
170 	tex_pos_in->data.location = VARYING_SLOT_VAR0;
171 
172 	/* Swizzle the array index which comes in as Z coordinate into the right
173 	 * position.
174 	 */
175 	unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
176 	nir_ssa_def *const tex_pos =
177 		nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
178 			    (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
179 
180 	const struct glsl_type *sampler_type =
181 		glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
182 				  glsl_get_base_type(vec4));
183 	nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
184 						    sampler_type, "s_tex");
185 	sampler->data.descriptor_set = 0;
186 	sampler->data.binding = 0;
187 
188 	nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
189 	tex->sampler_dim = tex_dim;
190 	tex->op = nir_texop_tex;
191 	tex->src[0].src_type = nir_tex_src_coord;
192 	tex->src[0].src = nir_src_for_ssa(tex_pos);
193 	tex->dest_type = nir_type_float; /* TODO */
194 	tex->is_array = glsl_sampler_type_is_array(sampler_type);
195 	tex->coord_components = tex_pos->num_components;
196 	tex->texture = nir_deref_var_create(tex, sampler);
197 	tex->sampler = nir_deref_var_create(tex, sampler);
198 
199 	nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
200 	nir_builder_instr_insert(&b, &tex->instr);
201 
202 	nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
203 						      vec4, "f_color");
204 	color_out->data.location = FRAG_RESULT_DEPTH;
205 	nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
206 
207 	return b.shader;
208 }
209 
210 static nir_shader *
build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim)211 build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim)
212 {
213 	char shader_name[64];
214 	const struct glsl_type *vec4 = glsl_vec4_type();
215 	nir_builder b;
216 
217 	nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
218 
219 	sprintf(shader_name, "meta_blit_stencil_fs.%d", tex_dim);
220 	b.shader->info.name = ralloc_strdup(b.shader, shader_name);
221 
222 	nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
223 						       vec4, "v_tex_pos");
224 	tex_pos_in->data.location = VARYING_SLOT_VAR0;
225 
226 	/* Swizzle the array index which comes in as Z coordinate into the right
227 	 * position.
228 	 */
229 	unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
230 	nir_ssa_def *const tex_pos =
231 		nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
232 			    (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
233 
234 	const struct glsl_type *sampler_type =
235 		glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
236 				  glsl_get_base_type(vec4));
237 	nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
238 						    sampler_type, "s_tex");
239 	sampler->data.descriptor_set = 0;
240 	sampler->data.binding = 0;
241 
242 	nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
243 	tex->sampler_dim = tex_dim;
244 	tex->op = nir_texop_tex;
245 	tex->src[0].src_type = nir_tex_src_coord;
246 	tex->src[0].src = nir_src_for_ssa(tex_pos);
247 	tex->dest_type = nir_type_float; /* TODO */
248 	tex->is_array = glsl_sampler_type_is_array(sampler_type);
249 	tex->coord_components = tex_pos->num_components;
250 	tex->texture = nir_deref_var_create(tex, sampler);
251 	tex->sampler = nir_deref_var_create(tex, sampler);
252 
253 	nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
254 	nir_builder_instr_insert(&b, &tex->instr);
255 
256 	nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
257 						      vec4, "f_color");
258 	color_out->data.location = FRAG_RESULT_STENCIL;
259 	nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
260 
261 	return b.shader;
262 }
263 
264 static void
meta_emit_blit(struct radv_cmd_buffer * cmd_buffer,struct radv_image * src_image,struct radv_image_view * src_iview,VkImageLayout src_image_layout,VkOffset3D src_offset_0,VkOffset3D src_offset_1,struct radv_image * dest_image,struct radv_image_view * dest_iview,VkImageLayout dest_image_layout,VkOffset2D dest_offset_0,VkOffset2D dest_offset_1,VkRect2D dest_box,VkFilter blit_filter)265 meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
266                struct radv_image *src_image,
267                struct radv_image_view *src_iview,
268 	       VkImageLayout src_image_layout,
269                VkOffset3D src_offset_0,
270                VkOffset3D src_offset_1,
271                struct radv_image *dest_image,
272                struct radv_image_view *dest_iview,
273 	       VkImageLayout dest_image_layout,
274                VkOffset2D dest_offset_0,
275                VkOffset2D dest_offset_1,
276                VkRect2D dest_box,
277                VkFilter blit_filter)
278 {
279 	struct radv_device *device = cmd_buffer->device;
280 	uint32_t src_width = radv_minify(src_iview->image->info.width, src_iview->base_mip);
281 	uint32_t src_height = radv_minify(src_iview->image->info.height, src_iview->base_mip);
282 	uint32_t src_depth = radv_minify(src_iview->image->info.depth, src_iview->base_mip);
283 	uint32_t dst_width = radv_minify(dest_iview->image->info.width, dest_iview->base_mip);
284 	uint32_t dst_height = radv_minify(dest_iview->image->info.height, dest_iview->base_mip);
285 
286 	assert(src_image->info.samples == dest_image->info.samples);
287 
288 	float vertex_push_constants[5] = {
289 		(float)src_offset_0.x / (float)src_width,
290 		(float)src_offset_0.y / (float)src_height,
291 		(float)src_offset_1.x / (float)src_width,
292 		(float)src_offset_1.y / (float)src_height,
293 		(float)src_offset_0.z / (float)src_depth,
294 	};
295 
296 	radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
297 			      device->meta_state.blit.pipeline_layout,
298 			      VK_SHADER_STAGE_VERTEX_BIT, 0, 20,
299 			      vertex_push_constants);
300 
301 	VkSampler sampler;
302 	radv_CreateSampler(radv_device_to_handle(device),
303 				 &(VkSamplerCreateInfo) {
304 					 .sType = VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO,
305 						 .magFilter = blit_filter,
306 						 .minFilter = blit_filter,
307 						 .addressModeU = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
308 						 .addressModeV = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
309 						 .addressModeW = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
310 						 }, &cmd_buffer->pool->alloc, &sampler);
311 
312 	VkFramebuffer fb;
313 	radv_CreateFramebuffer(radv_device_to_handle(device),
314 			       &(VkFramebufferCreateInfo) {
315 				       .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
316 					       .attachmentCount = 1,
317 					       .pAttachments = (VkImageView[]) {
318 					       radv_image_view_to_handle(dest_iview),
319 				       },
320 				       .width = dst_width,
321 				       .height = dst_height,
322 				       .layers = 1,
323 				}, &cmd_buffer->pool->alloc, &fb);
324 	VkPipeline pipeline;
325 	switch (src_iview->aspect_mask) {
326 	case VK_IMAGE_ASPECT_COLOR_BIT: {
327 		unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
328 		unsigned dst_layout = radv_meta_dst_layout_from_layout(dest_image_layout);
329 
330 		radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
331 					      &(VkRenderPassBeginInfo) {
332 						      .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
333 							      .renderPass = device->meta_state.blit.render_pass[fs_key][dst_layout],
334 							      .framebuffer = fb,
335 							      .renderArea = {
336 							      .offset = { dest_box.offset.x, dest_box.offset.y },
337 							      .extent = { dest_box.extent.width, dest_box.extent.height },
338 						      },
339 							      .clearValueCount = 0,
340 								       .pClearValues = NULL,
341 						       }, VK_SUBPASS_CONTENTS_INLINE);
342 		switch (src_image->type) {
343 		case VK_IMAGE_TYPE_1D:
344 			pipeline = device->meta_state.blit.pipeline_1d_src[fs_key];
345 			break;
346 		case VK_IMAGE_TYPE_2D:
347 			pipeline = device->meta_state.blit.pipeline_2d_src[fs_key];
348 			break;
349 		case VK_IMAGE_TYPE_3D:
350 			pipeline = device->meta_state.blit.pipeline_3d_src[fs_key];
351 			break;
352 		default:
353 			unreachable(!"bad VkImageType");
354 		}
355 		break;
356 	}
357 	case VK_IMAGE_ASPECT_DEPTH_BIT: {
358 		enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dest_image_layout);
359 		radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
360 					      &(VkRenderPassBeginInfo) {
361 						      .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
362 							      .renderPass = device->meta_state.blit.depth_only_rp[ds_layout],
363 							      .framebuffer = fb,
364 							      .renderArea = {
365 							      .offset = { dest_box.offset.x, dest_box.offset.y },
366 							      .extent = { dest_box.extent.width, dest_box.extent.height },
367 						      },
368 							      .clearValueCount = 0,
369 								       .pClearValues = NULL,
370 						       }, VK_SUBPASS_CONTENTS_INLINE);
371 		switch (src_image->type) {
372 		case VK_IMAGE_TYPE_1D:
373 			pipeline = device->meta_state.blit.depth_only_1d_pipeline;
374 			break;
375 		case VK_IMAGE_TYPE_2D:
376 			pipeline = device->meta_state.blit.depth_only_2d_pipeline;
377 			break;
378 		case VK_IMAGE_TYPE_3D:
379 			pipeline = device->meta_state.blit.depth_only_3d_pipeline;
380 			break;
381 		default:
382 			unreachable(!"bad VkImageType");
383 		}
384 		break;
385 	}
386 	case VK_IMAGE_ASPECT_STENCIL_BIT: {
387 		enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dest_image_layout);
388 		radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
389 					      &(VkRenderPassBeginInfo) {
390 						      .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
391 							      .renderPass = device->meta_state.blit.stencil_only_rp[ds_layout],
392 							      .framebuffer = fb,
393 							      .renderArea = {
394 							      .offset = { dest_box.offset.x, dest_box.offset.y },
395 							      .extent = { dest_box.extent.width, dest_box.extent.height },
396 						              },
397 							      .clearValueCount = 0,
398 								       .pClearValues = NULL,
399 						       }, VK_SUBPASS_CONTENTS_INLINE);
400 		switch (src_image->type) {
401 		case VK_IMAGE_TYPE_1D:
402 			pipeline = device->meta_state.blit.stencil_only_1d_pipeline;
403 			break;
404 		case VK_IMAGE_TYPE_2D:
405 			pipeline = device->meta_state.blit.stencil_only_2d_pipeline;
406 			break;
407 		case VK_IMAGE_TYPE_3D:
408 			pipeline = device->meta_state.blit.stencil_only_3d_pipeline;
409 			break;
410 		default:
411 			unreachable(!"bad VkImageType");
412 		}
413 		break;
414 	}
415 	default:
416 		unreachable(!"bad VkImageType");
417 	}
418 
419 	radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
420 			     VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
421 
422 	radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
423 			              device->meta_state.blit.pipeline_layout,
424 				      0, /* set */
425 				      1, /* descriptorWriteCount */
426 				      (VkWriteDescriptorSet[]) {
427 				              {
428 				                      .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
429 				                      .dstBinding = 0,
430 				                      .dstArrayElement = 0,
431 				                      .descriptorCount = 1,
432 				                      .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
433 				                      .pImageInfo = (VkDescriptorImageInfo[]) {
434 				                              {
435 				                                      .sampler = sampler,
436 				                                      .imageView = radv_image_view_to_handle(src_iview),
437 				                                      .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
438 				                              },
439 				                      }
440 				              }
441 				      });
442 
443 	radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
444 		.x = dest_offset_0.x,
445 		.y = dest_offset_0.y,
446 		.width = dest_offset_1.x - dest_offset_0.x,
447 		.height = dest_offset_1.y - dest_offset_0.y,
448 		.minDepth = 0.0f,
449 		.maxDepth = 1.0f
450 	});
451 
452 	radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
453 		.offset = (VkOffset2D) { MIN2(dest_offset_0.x, dest_offset_1.x), MIN2(dest_offset_0.y, dest_offset_1.y) },
454 		.extent = (VkExtent2D) {
455 			abs(dest_offset_1.x - dest_offset_0.x),
456 			abs(dest_offset_1.y - dest_offset_0.y)
457 		},
458 	});
459 
460 	radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
461 
462 	radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
463 
464 	/* At the point where we emit the draw call, all data from the
465 	 * descriptor sets, etc. has been used.  We are free to delete it.
466 	 */
467 	/* TODO: above comment is not valid for at least descriptor sets/pools,
468 	 * as we may not free them till after execution finishes. Check others. */
469 
470 	radv_DestroySampler(radv_device_to_handle(device), sampler,
471 			    &cmd_buffer->pool->alloc);
472 	radv_DestroyFramebuffer(radv_device_to_handle(device), fb,
473 				&cmd_buffer->pool->alloc);
474 }
475 
476 static bool
flip_coords(unsigned * src0,unsigned * src1,unsigned * dst0,unsigned * dst1)477 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1)
478 {
479 	bool flip = false;
480 	if (*src0 > *src1) {
481 		unsigned tmp = *src0;
482 		*src0 = *src1;
483 		*src1 = tmp;
484 		flip = !flip;
485 	}
486 
487 	if (*dst0 > *dst1) {
488 		unsigned tmp = *dst0;
489 		*dst0 = *dst1;
490 		*dst1 = tmp;
491 		flip = !flip;
492 	}
493 	return flip;
494 }
495 
radv_CmdBlitImage(VkCommandBuffer commandBuffer,VkImage srcImage,VkImageLayout srcImageLayout,VkImage destImage,VkImageLayout destImageLayout,uint32_t regionCount,const VkImageBlit * pRegions,VkFilter filter)496 void radv_CmdBlitImage(
497 	VkCommandBuffer                             commandBuffer,
498 	VkImage                                     srcImage,
499 	VkImageLayout                               srcImageLayout,
500 	VkImage                                     destImage,
501 	VkImageLayout                               destImageLayout,
502 	uint32_t                                    regionCount,
503 	const VkImageBlit*                          pRegions,
504 	VkFilter                                    filter)
505 
506 {
507 	RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
508 	RADV_FROM_HANDLE(radv_image, src_image, srcImage);
509 	RADV_FROM_HANDLE(radv_image, dest_image, destImage);
510 	struct radv_meta_saved_state saved_state;
511 
512 	/* From the Vulkan 1.0 spec:
513 	 *
514 	 *    vkCmdBlitImage must not be used for multisampled source or
515 	 *    destination images. Use vkCmdResolveImage for this purpose.
516 	 */
517 	assert(src_image->info.samples == 1);
518 	assert(dest_image->info.samples == 1);
519 
520 	radv_meta_save(&saved_state, cmd_buffer,
521 		       RADV_META_SAVE_GRAPHICS_PIPELINE |
522 		       RADV_META_SAVE_CONSTANTS |
523 		       RADV_META_SAVE_DESCRIPTORS);
524 
525 	for (unsigned r = 0; r < regionCount; r++) {
526 		const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
527 		const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
528 
529 		unsigned dst_start, dst_end;
530 		if (dest_image->type == VK_IMAGE_TYPE_3D) {
531 			assert(dst_res->baseArrayLayer == 0);
532 			dst_start = pRegions[r].dstOffsets[0].z;
533 			dst_end = pRegions[r].dstOffsets[1].z;
534 		} else {
535 			dst_start = dst_res->baseArrayLayer;
536 			dst_end = dst_start + dst_res->layerCount;
537 		}
538 
539 		unsigned src_start, src_end;
540 		if (src_image->type == VK_IMAGE_TYPE_3D) {
541 			assert(src_res->baseArrayLayer == 0);
542 			src_start = pRegions[r].srcOffsets[0].z;
543 			src_end = pRegions[r].srcOffsets[1].z;
544 		} else {
545 			src_start = src_res->baseArrayLayer;
546 			src_end = src_start + src_res->layerCount;
547 		}
548 
549 		bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
550 		float src_z_step = (float)(src_end + 1 - src_start) /
551 			(float)(dst_end + 1 - dst_start);
552 
553 		if (flip_z) {
554 			src_start = src_end;
555 			src_z_step *= -1;
556 		}
557 
558 		unsigned src_x0 = pRegions[r].srcOffsets[0].x;
559 		unsigned src_x1 = pRegions[r].srcOffsets[1].x;
560 		unsigned dst_x0 = pRegions[r].dstOffsets[0].x;
561 		unsigned dst_x1 = pRegions[r].dstOffsets[1].x;
562 
563 		unsigned src_y0 = pRegions[r].srcOffsets[0].y;
564 		unsigned src_y1 = pRegions[r].srcOffsets[1].y;
565 		unsigned dst_y0 = pRegions[r].dstOffsets[0].y;
566 		unsigned dst_y1 = pRegions[r].dstOffsets[1].y;
567 
568 		VkRect2D dest_box;
569 		dest_box.offset.x = MIN2(dst_x0, dst_x1);
570 		dest_box.offset.y = MIN2(dst_y0, dst_y1);
571 		dest_box.extent.width = abs(dst_x1 - dst_x0);
572 		dest_box.extent.height = abs(dst_y1 - dst_y0);
573 
574 		const unsigned num_layers = dst_end - dst_start;
575 		for (unsigned i = 0; i < num_layers; i++) {
576 			struct radv_image_view dest_iview, src_iview;
577 
578 			const VkOffset2D dest_offset_0 = {
579 				.x = dst_x0,
580 				.y = dst_y0,
581 			};
582 			const VkOffset2D dest_offset_1 = {
583 				.x = dst_x1,
584 				.y = dst_y1,
585 			};
586 			VkOffset3D src_offset_0 = {
587 				.x = src_x0,
588 				.y = src_y0,
589 				.z = src_start + i * src_z_step,
590 			};
591 			VkOffset3D src_offset_1 = {
592 				.x = src_x1,
593 				.y = src_y1,
594 				.z = src_start + i * src_z_step,
595 			};
596 			const uint32_t dest_array_slice = dst_start + i;
597 
598 			/* 3D images have just 1 layer */
599 			const uint32_t src_array_slice = src_image->type == VK_IMAGE_TYPE_3D ? 0 : src_start + i;
600 
601 			radv_image_view_init(&dest_iview, cmd_buffer->device,
602 					     &(VkImageViewCreateInfo) {
603 						     .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
604 							     .image = destImage,
605 							     .viewType = radv_meta_get_view_type(dest_image),
606 							     .format = dest_image->vk_format,
607 							     .subresourceRange = {
608 							     .aspectMask = dst_res->aspectMask,
609 							     .baseMipLevel = dst_res->mipLevel,
610 							     .levelCount = 1,
611 							     .baseArrayLayer = dest_array_slice,
612 							     .layerCount = 1
613 						     },
614 					     });
615 			radv_image_view_init(&src_iview, cmd_buffer->device,
616 					     &(VkImageViewCreateInfo) {
617 						.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
618 							.image = srcImage,
619 							.viewType = radv_meta_get_view_type(src_image),
620 							.format = src_image->vk_format,
621 							.subresourceRange = {
622 							.aspectMask = src_res->aspectMask,
623 							.baseMipLevel = src_res->mipLevel,
624 							.levelCount = 1,
625 							.baseArrayLayer = src_array_slice,
626 							.layerCount = 1
627 						},
628 					});
629 			meta_emit_blit(cmd_buffer,
630 				       src_image, &src_iview, srcImageLayout,
631 				       src_offset_0, src_offset_1,
632 				       dest_image, &dest_iview, destImageLayout,
633 				       dest_offset_0, dest_offset_1,
634 				       dest_box,
635 				       filter);
636 		}
637 	}
638 
639 	radv_meta_restore(&saved_state, cmd_buffer);
640 }
641 
642 void
radv_device_finish_meta_blit_state(struct radv_device * device)643 radv_device_finish_meta_blit_state(struct radv_device *device)
644 {
645 	struct radv_meta_state *state = &device->meta_state;
646 
647 	for (unsigned i = 0; i < NUM_META_FS_KEYS; ++i) {
648 		for (unsigned j = 0; j < RADV_META_DST_LAYOUT_COUNT; ++j) {
649 			radv_DestroyRenderPass(radv_device_to_handle(device),
650 			                       state->blit.render_pass[i][j],
651 			                       &state->alloc);
652 		}
653 		radv_DestroyPipeline(radv_device_to_handle(device),
654 				     state->blit.pipeline_1d_src[i],
655 				     &state->alloc);
656 		radv_DestroyPipeline(radv_device_to_handle(device),
657 				     state->blit.pipeline_2d_src[i],
658 				     &state->alloc);
659 		radv_DestroyPipeline(radv_device_to_handle(device),
660 				     state->blit.pipeline_3d_src[i],
661 				     &state->alloc);
662 	}
663 
664 	for (enum radv_blit_ds_layout i = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; i < RADV_BLIT_DS_LAYOUT_COUNT; i++) {
665 		radv_DestroyRenderPass(radv_device_to_handle(device),
666 				       state->blit.depth_only_rp[i], &state->alloc);
667 		radv_DestroyRenderPass(radv_device_to_handle(device),
668 				       state->blit.stencil_only_rp[i], &state->alloc);
669 	}
670 
671 	radv_DestroyPipeline(radv_device_to_handle(device),
672 			     state->blit.depth_only_1d_pipeline, &state->alloc);
673 	radv_DestroyPipeline(radv_device_to_handle(device),
674 			     state->blit.depth_only_2d_pipeline, &state->alloc);
675 	radv_DestroyPipeline(radv_device_to_handle(device),
676 			     state->blit.depth_only_3d_pipeline, &state->alloc);
677 
678 	radv_DestroyPipeline(radv_device_to_handle(device),
679 			     state->blit.stencil_only_1d_pipeline,
680 			     &state->alloc);
681 	radv_DestroyPipeline(radv_device_to_handle(device),
682 			     state->blit.stencil_only_2d_pipeline,
683 			     &state->alloc);
684 	radv_DestroyPipeline(radv_device_to_handle(device),
685 			     state->blit.stencil_only_3d_pipeline,
686 			     &state->alloc);
687 
688 
689 	radv_DestroyPipelineLayout(radv_device_to_handle(device),
690 				   state->blit.pipeline_layout, &state->alloc);
691 	radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
692 					state->blit.ds_layout, &state->alloc);
693 }
694 
695 static VkFormat pipeline_formats[] = {
696    VK_FORMAT_R8G8B8A8_UNORM,
697    VK_FORMAT_R8G8B8A8_UINT,
698    VK_FORMAT_R8G8B8A8_SINT,
699    VK_FORMAT_A2R10G10B10_UINT_PACK32,
700    VK_FORMAT_A2R10G10B10_SINT_PACK32,
701    VK_FORMAT_R16G16B16A16_UNORM,
702    VK_FORMAT_R16G16B16A16_SNORM,
703    VK_FORMAT_R16G16B16A16_UINT,
704    VK_FORMAT_R16G16B16A16_SINT,
705    VK_FORMAT_R32_SFLOAT,
706    VK_FORMAT_R32G32_SFLOAT,
707    VK_FORMAT_R32G32B32A32_SFLOAT
708 };
709 
710 static VkResult
radv_device_init_meta_blit_color(struct radv_device * device,struct radv_shader_module * vs)711 radv_device_init_meta_blit_color(struct radv_device *device,
712 				 struct radv_shader_module *vs)
713 {
714 	struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
715 	VkResult result;
716 
717 	fs_1d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_1D);
718 	fs_2d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_2D);
719 	fs_3d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_3D);
720 
721 	for (unsigned i = 0; i < ARRAY_SIZE(pipeline_formats); ++i) {
722 		unsigned key = radv_format_meta_fs_key(pipeline_formats[i]);
723 		for(unsigned j = 0; j < RADV_META_DST_LAYOUT_COUNT; ++j) {
724 			VkImageLayout layout = radv_meta_dst_layout_to_layout(j);
725 			result = radv_CreateRenderPass(radv_device_to_handle(device),
726 						&(VkRenderPassCreateInfo) {
727 							.sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
728 								.attachmentCount = 1,
729 								.pAttachments = &(VkAttachmentDescription) {
730 								.format = pipeline_formats[i],
731 								.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
732 								.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
733 								.initialLayout = layout,
734 								.finalLayout = layout,
735 							},
736 								.subpassCount = 1,
737 										.pSubpasses = &(VkSubpassDescription) {
738 								.pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
739 								.inputAttachmentCount = 0,
740 								.colorAttachmentCount = 1,
741 								.pColorAttachments = &(VkAttachmentReference) {
742 									.attachment = 0,
743 									.layout = layout,
744 								},
745 								.pResolveAttachments = NULL,
746 								.pDepthStencilAttachment = &(VkAttachmentReference) {
747 									.attachment = VK_ATTACHMENT_UNUSED,
748 									.layout = VK_IMAGE_LAYOUT_GENERAL,
749 								},
750 								.preserveAttachmentCount = 1,
751 								.pPreserveAttachments = (uint32_t[]) { 0 },
752 							},
753 							.dependencyCount = 0,
754 						}, &device->meta_state.alloc, &device->meta_state.blit.render_pass[key][j]);
755 			if (result != VK_SUCCESS)
756 				goto fail;
757 		}
758 
759 		VkPipelineVertexInputStateCreateInfo vi_create_info = {
760 			.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
761 			.vertexBindingDescriptionCount = 0,
762 			.vertexAttributeDescriptionCount = 0,
763 		};
764 
765 		VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
766 			{
767 				.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
768 				.stage = VK_SHADER_STAGE_VERTEX_BIT,
769 				.module = radv_shader_module_to_handle(vs),
770 				.pName = "main",
771 				.pSpecializationInfo = NULL
772 			}, {
773 				.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
774 				.stage = VK_SHADER_STAGE_FRAGMENT_BIT,
775 				.module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
776 				.pName = "main",
777 				.pSpecializationInfo = NULL
778 			},
779 		};
780 
781 		const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
782 			.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
783 			.stageCount = ARRAY_SIZE(pipeline_shader_stages),
784 			.pStages = pipeline_shader_stages,
785 			.pVertexInputState = &vi_create_info,
786 			.pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
787 				.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
788 				.topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
789 				.primitiveRestartEnable = false,
790 			},
791 			.pViewportState = &(VkPipelineViewportStateCreateInfo) {
792 				.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
793 				.viewportCount = 1,
794 				.scissorCount = 1,
795 			},
796 			.pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
797 				.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
798 				.rasterizerDiscardEnable = false,
799 				.polygonMode = VK_POLYGON_MODE_FILL,
800 				.cullMode = VK_CULL_MODE_NONE,
801 				.frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
802 			},
803 			.pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
804 				.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
805 				.rasterizationSamples = 1,
806 				.sampleShadingEnable = false,
807 				.pSampleMask = (VkSampleMask[]) { UINT32_MAX },
808 			},
809 			.pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
810 				.sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
811 				.attachmentCount = 1,
812 				.pAttachments = (VkPipelineColorBlendAttachmentState []) {
813 					{ .colorWriteMask =
814 					VK_COLOR_COMPONENT_A_BIT |
815 					VK_COLOR_COMPONENT_R_BIT |
816 					VK_COLOR_COMPONENT_G_BIT |
817 					VK_COLOR_COMPONENT_B_BIT },
818 				}
819 			},
820 			.pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
821 				.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
822 				.dynamicStateCount = 4,
823 				.pDynamicStates = (VkDynamicState[]) {
824 					VK_DYNAMIC_STATE_VIEWPORT,
825 					VK_DYNAMIC_STATE_SCISSOR,
826 					VK_DYNAMIC_STATE_LINE_WIDTH,
827 					VK_DYNAMIC_STATE_BLEND_CONSTANTS,
828 				},
829 			},
830 			.flags = 0,
831 			.layout = device->meta_state.blit.pipeline_layout,
832 			.renderPass = device->meta_state.blit.render_pass[key][0],
833 			.subpass = 0,
834 		};
835 
836 		const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
837 			.use_rectlist = true
838 		};
839 
840 		pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
841 		result = radv_graphics_pipeline_create(radv_device_to_handle(device),
842 						radv_pipeline_cache_to_handle(&device->meta_state.cache),
843 						&vk_pipeline_info, &radv_pipeline_info,
844 						&device->meta_state.alloc, &device->meta_state.blit.pipeline_1d_src[key]);
845 		if (result != VK_SUCCESS)
846 			goto fail;
847 
848 		pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
849 		result = radv_graphics_pipeline_create(radv_device_to_handle(device),
850 						radv_pipeline_cache_to_handle(&device->meta_state.cache),
851 						&vk_pipeline_info, &radv_pipeline_info,
852 						&device->meta_state.alloc, &device->meta_state.blit.pipeline_2d_src[key]);
853 		if (result != VK_SUCCESS)
854 			goto fail;
855 
856 		pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
857 		result = radv_graphics_pipeline_create(radv_device_to_handle(device),
858 						radv_pipeline_cache_to_handle(&device->meta_state.cache),
859 						&vk_pipeline_info, &radv_pipeline_info,
860 						&device->meta_state.alloc, &device->meta_state.blit.pipeline_3d_src[key]);
861 		if (result != VK_SUCCESS)
862 			goto fail;
863 
864 	}
865 
866 	result = VK_SUCCESS;
867 fail:
868 	ralloc_free(fs_1d.nir);
869 	ralloc_free(fs_2d.nir);
870 	ralloc_free(fs_3d.nir);
871 	return result;
872 }
873 
874 static VkResult
radv_device_init_meta_blit_depth(struct radv_device * device,struct radv_shader_module * vs)875 radv_device_init_meta_blit_depth(struct radv_device *device,
876 				 struct radv_shader_module *vs)
877 {
878 	struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
879 	VkResult result;
880 
881 	fs_1d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_1D);
882 	fs_2d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_2D);
883 	fs_3d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_3D);
884 
885 	for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
886 		VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
887 		result = radv_CreateRenderPass(radv_device_to_handle(device),
888 					       &(VkRenderPassCreateInfo) {
889 						       .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
890 						       .attachmentCount = 1,
891 						       .pAttachments = &(VkAttachmentDescription) {
892 							       .format = VK_FORMAT_D32_SFLOAT,
893 							       .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
894 							       .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
895 							       .initialLayout = layout,
896 							       .finalLayout = layout,
897 						       },
898 						       .subpassCount = 1,
899 						       .pSubpasses = &(VkSubpassDescription) {
900 							       .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
901 							       .inputAttachmentCount = 0,
902 							       .colorAttachmentCount = 0,
903 							       .pColorAttachments = NULL,
904 							       .pResolveAttachments = NULL,
905 							       .pDepthStencilAttachment = &(VkAttachmentReference) {
906 								       .attachment = 0,
907 								       .layout = layout,
908 								},
909 							       .preserveAttachmentCount = 1,
910 							       .pPreserveAttachments = (uint32_t[]) { 0 },
911 							},
912 						        .dependencyCount = 0,
913 						}, &device->meta_state.alloc, &device->meta_state.blit.depth_only_rp[ds_layout]);
914 		if (result != VK_SUCCESS)
915 			goto fail;
916 	}
917 
918 	VkPipelineVertexInputStateCreateInfo vi_create_info = {
919 		.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
920 		.vertexBindingDescriptionCount = 0,
921 		.vertexAttributeDescriptionCount = 0,
922 	};
923 
924 	VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
925 		{
926 			.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
927 			.stage = VK_SHADER_STAGE_VERTEX_BIT,
928 			.module = radv_shader_module_to_handle(vs),
929 			.pName = "main",
930 			.pSpecializationInfo = NULL
931 		}, {
932 			.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
933 			.stage = VK_SHADER_STAGE_FRAGMENT_BIT,
934 			.module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
935 			.pName = "main",
936 			.pSpecializationInfo = NULL
937 		},
938 	};
939 
940 	const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
941 		.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
942 		.stageCount = ARRAY_SIZE(pipeline_shader_stages),
943 		.pStages = pipeline_shader_stages,
944 		.pVertexInputState = &vi_create_info,
945 		.pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
946 			.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
947 			.topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
948 			.primitiveRestartEnable = false,
949 		},
950 		.pViewportState = &(VkPipelineViewportStateCreateInfo) {
951 			.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
952 			.viewportCount = 1,
953 			.scissorCount = 1,
954 		},
955 		.pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
956 			.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
957 			.rasterizerDiscardEnable = false,
958 			.polygonMode = VK_POLYGON_MODE_FILL,
959 			.cullMode = VK_CULL_MODE_NONE,
960 			.frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
961 		},
962 		.pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
963 			.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
964 			.rasterizationSamples = 1,
965 			.sampleShadingEnable = false,
966 			.pSampleMask = (VkSampleMask[]) { UINT32_MAX },
967 		},
968 		.pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
969 			.sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
970 			.attachmentCount = 0,
971 			.pAttachments = NULL,
972 		},
973 		.pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
974 			.sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
975 			.depthTestEnable = true,
976 			.depthWriteEnable = true,
977 			.depthCompareOp = VK_COMPARE_OP_ALWAYS,
978 		},
979 		.pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
980 			.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
981 			.dynamicStateCount = 9,
982 			.pDynamicStates = (VkDynamicState[]) {
983 				VK_DYNAMIC_STATE_VIEWPORT,
984 				VK_DYNAMIC_STATE_SCISSOR,
985 				VK_DYNAMIC_STATE_LINE_WIDTH,
986 				VK_DYNAMIC_STATE_DEPTH_BIAS,
987 				VK_DYNAMIC_STATE_BLEND_CONSTANTS,
988 				VK_DYNAMIC_STATE_DEPTH_BOUNDS,
989 				VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
990 				VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
991 				VK_DYNAMIC_STATE_STENCIL_REFERENCE,
992 			},
993 		},
994 		.flags = 0,
995 		.layout = device->meta_state.blit.pipeline_layout,
996 		.renderPass = device->meta_state.blit.depth_only_rp[0],
997 		.subpass = 0,
998 	};
999 
1000 	const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1001 		.use_rectlist = true
1002 	};
1003 
1004 	pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
1005 	result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1006 					       radv_pipeline_cache_to_handle(&device->meta_state.cache),
1007 					       &vk_pipeline_info, &radv_pipeline_info,
1008 					       &device->meta_state.alloc, &device->meta_state.blit.depth_only_1d_pipeline);
1009 	if (result != VK_SUCCESS)
1010 		goto fail;
1011 
1012 	pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
1013 	result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1014 					       radv_pipeline_cache_to_handle(&device->meta_state.cache),
1015 					       &vk_pipeline_info, &radv_pipeline_info,
1016 					       &device->meta_state.alloc, &device->meta_state.blit.depth_only_2d_pipeline);
1017 	if (result != VK_SUCCESS)
1018 		goto fail;
1019 
1020 	pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1021 	result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1022 					       radv_pipeline_cache_to_handle(&device->meta_state.cache),
1023 					       &vk_pipeline_info, &radv_pipeline_info,
1024 					       &device->meta_state.alloc, &device->meta_state.blit.depth_only_3d_pipeline);
1025 	if (result != VK_SUCCESS)
1026 		goto fail;
1027 
1028 fail:
1029 	ralloc_free(fs_1d.nir);
1030 	ralloc_free(fs_2d.nir);
1031 	ralloc_free(fs_3d.nir);
1032 	return result;
1033 }
1034 
1035 static VkResult
radv_device_init_meta_blit_stencil(struct radv_device * device,struct radv_shader_module * vs)1036 radv_device_init_meta_blit_stencil(struct radv_device *device,
1037 				   struct radv_shader_module *vs)
1038 {
1039 	struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
1040 	VkResult result;
1041 
1042 	fs_1d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_1D);
1043 	fs_2d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_2D);
1044 	fs_3d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_3D);
1045 
1046 	for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
1047 		VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
1048 		result = radv_CreateRenderPass(radv_device_to_handle(device),
1049 					       &(VkRenderPassCreateInfo) {
1050 						       .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1051 						       .attachmentCount = 1,
1052 						       .pAttachments = &(VkAttachmentDescription) {
1053 							       .format = VK_FORMAT_S8_UINT,
1054 							       .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1055 							       .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1056 							       .initialLayout = layout,
1057 							       .finalLayout = layout,
1058 						       },
1059 						       .subpassCount = 1,
1060 						       .pSubpasses = &(VkSubpassDescription) {
1061 							       .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1062 							       .inputAttachmentCount = 0,
1063 							       .colorAttachmentCount = 0,
1064 							       .pColorAttachments = NULL,
1065 							       .pResolveAttachments = NULL,
1066 							       .pDepthStencilAttachment = &(VkAttachmentReference) {
1067 								       .attachment = 0,
1068 								       .layout = layout,
1069 							       },
1070 							       .preserveAttachmentCount = 1,
1071 							       .pPreserveAttachments = (uint32_t[]) { 0 },
1072 						       },
1073 						       .dependencyCount = 0,
1074 					 }, &device->meta_state.alloc, &device->meta_state.blit.stencil_only_rp[ds_layout]);
1075 	}
1076 	if (result != VK_SUCCESS)
1077 		goto fail;
1078 
1079 	VkPipelineVertexInputStateCreateInfo vi_create_info = {
1080 		.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
1081 		.vertexBindingDescriptionCount = 0,
1082 		.vertexAttributeDescriptionCount = 0,
1083 	};
1084 
1085 	VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1086 		{
1087 			.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1088 			.stage = VK_SHADER_STAGE_VERTEX_BIT,
1089 			.module = radv_shader_module_to_handle(vs),
1090 			.pName = "main",
1091 			.pSpecializationInfo = NULL
1092 		}, {
1093 			.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1094 			.stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1095 			.module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
1096 			.pName = "main",
1097 			.pSpecializationInfo = NULL
1098 		},
1099 	};
1100 
1101 	const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1102 		.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1103 		.stageCount = ARRAY_SIZE(pipeline_shader_stages),
1104 		.pStages = pipeline_shader_stages,
1105 		.pVertexInputState = &vi_create_info,
1106 		.pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1107 			.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1108 			.topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1109 			.primitiveRestartEnable = false,
1110 		},
1111 		.pViewportState = &(VkPipelineViewportStateCreateInfo) {
1112 			.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1113 			.viewportCount = 1,
1114 			.scissorCount = 1,
1115 		},
1116 		.pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1117 			.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1118 			.rasterizerDiscardEnable = false,
1119 			.polygonMode = VK_POLYGON_MODE_FILL,
1120 			.cullMode = VK_CULL_MODE_NONE,
1121 			.frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1122 		},
1123 		.pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1124 			.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1125 			.rasterizationSamples = 1,
1126 			.sampleShadingEnable = false,
1127 			.pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1128 		},
1129 		.pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1130 			.sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1131 			.attachmentCount = 0,
1132 			.pAttachments = NULL,
1133 		},
1134 		.pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1135 			.sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1136 			.depthTestEnable = false,
1137 			.depthWriteEnable = false,
1138 			.stencilTestEnable = true,
1139 			.front = {
1140 				.failOp = VK_STENCIL_OP_REPLACE,
1141 				.passOp = VK_STENCIL_OP_REPLACE,
1142 				.depthFailOp = VK_STENCIL_OP_REPLACE,
1143 				.compareOp = VK_COMPARE_OP_ALWAYS,
1144 				.compareMask = 0xff,
1145 				.writeMask = 0xff,
1146 				.reference = 0
1147 			},
1148 			.back = {
1149 				.failOp = VK_STENCIL_OP_REPLACE,
1150 				.passOp = VK_STENCIL_OP_REPLACE,
1151 				.depthFailOp = VK_STENCIL_OP_REPLACE,
1152 				.compareOp = VK_COMPARE_OP_ALWAYS,
1153 				.compareMask = 0xff,
1154 				.writeMask = 0xff,
1155 				.reference = 0
1156 			},
1157 			.depthCompareOp = VK_COMPARE_OP_ALWAYS,
1158 		},
1159 		.pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1160 			.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1161 			.dynamicStateCount = 6,
1162 			.pDynamicStates = (VkDynamicState[]) {
1163 				VK_DYNAMIC_STATE_VIEWPORT,
1164 				VK_DYNAMIC_STATE_SCISSOR,
1165 				VK_DYNAMIC_STATE_LINE_WIDTH,
1166 				VK_DYNAMIC_STATE_DEPTH_BIAS,
1167 				VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1168 				VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1169 			},
1170 		},
1171 		.flags = 0,
1172 		.layout = device->meta_state.blit.pipeline_layout,
1173 		.renderPass = device->meta_state.blit.stencil_only_rp[0],
1174 		.subpass = 0,
1175 	};
1176 
1177 	const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1178 		.use_rectlist = true
1179 	};
1180 
1181 	pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
1182 	result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1183 					       radv_pipeline_cache_to_handle(&device->meta_state.cache),
1184 					       &vk_pipeline_info, &radv_pipeline_info,
1185 					       &device->meta_state.alloc, &device->meta_state.blit.stencil_only_1d_pipeline);
1186 	if (result != VK_SUCCESS)
1187 		goto fail;
1188 
1189 	pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
1190 	result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1191 					       radv_pipeline_cache_to_handle(&device->meta_state.cache),
1192 					       &vk_pipeline_info, &radv_pipeline_info,
1193 					       &device->meta_state.alloc, &device->meta_state.blit.stencil_only_2d_pipeline);
1194 	if (result != VK_SUCCESS)
1195 		goto fail;
1196 
1197 	pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1198 	result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1199 					       radv_pipeline_cache_to_handle(&device->meta_state.cache),
1200 					       &vk_pipeline_info, &radv_pipeline_info,
1201 					       &device->meta_state.alloc, &device->meta_state.blit.stencil_only_3d_pipeline);
1202 	if (result != VK_SUCCESS)
1203 		goto fail;
1204 
1205 
1206 fail:
1207 	ralloc_free(fs_1d.nir);
1208 	ralloc_free(fs_2d.nir);
1209 	ralloc_free(fs_3d.nir);
1210 	return result;
1211 }
1212 
1213 VkResult
radv_device_init_meta_blit_state(struct radv_device * device)1214 radv_device_init_meta_blit_state(struct radv_device *device)
1215 {
1216 	VkResult result;
1217 	struct radv_shader_module vs = {0};
1218 
1219 	VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1220 		.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1221 		.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1222 		.bindingCount = 1,
1223 		.pBindings = (VkDescriptorSetLayoutBinding[]) {
1224 			{
1225 				.binding = 0,
1226 				.descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
1227 				.descriptorCount = 1,
1228 				.stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1229 				.pImmutableSamplers = NULL
1230 			},
1231 		}
1232 	};
1233 	result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1234 						&ds_layout_info,
1235 						&device->meta_state.alloc,
1236 						&device->meta_state.blit.ds_layout);
1237 	if (result != VK_SUCCESS)
1238 		goto fail;
1239 
1240 	const VkPushConstantRange push_constant_range = {VK_SHADER_STAGE_VERTEX_BIT, 0, 20};
1241 
1242 	result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1243 					   &(VkPipelineLayoutCreateInfo) {
1244 						   .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1245 							   .setLayoutCount = 1,
1246 							   .pSetLayouts = &device->meta_state.blit.ds_layout,
1247 							   .pushConstantRangeCount = 1,
1248 							   .pPushConstantRanges = &push_constant_range,
1249 							   },
1250 					   &device->meta_state.alloc, &device->meta_state.blit.pipeline_layout);
1251 	if (result != VK_SUCCESS)
1252 		goto fail;
1253 
1254 	vs.nir = build_nir_vertex_shader();
1255 
1256 	result = radv_device_init_meta_blit_color(device, &vs);
1257 	if (result != VK_SUCCESS)
1258 		goto fail;
1259 
1260 	result = radv_device_init_meta_blit_depth(device, &vs);
1261 	if (result != VK_SUCCESS)
1262 		goto fail;
1263 
1264 	result = radv_device_init_meta_blit_stencil(device, &vs);
1265 
1266 fail:
1267 	ralloc_free(vs.nir);
1268 	if (result != VK_SUCCESS)
1269 		radv_device_finish_meta_blit_state(device);
1270 	return result;
1271 }
1272