1 /*
2 * Copyright © 2016 Dave Airlie
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24
25 #include <assert.h>
26 #include <stdbool.h>
27
28 #include "radv_meta.h"
29 #include "radv_private.h"
30 #include "nir/nir_builder.h"
31 #include "sid.h"
32 #include "vk_format.h"
33
radv_meta_build_resolve_srgb_conversion(nir_builder * b,nir_ssa_def * input)34 static nir_ssa_def *radv_meta_build_resolve_srgb_conversion(nir_builder *b,
35 nir_ssa_def *input)
36 {
37 nir_const_value v;
38 unsigned i;
39 v.u32[0] = 0x3b4d2e1c; // 0.00313080009
40
41 nir_ssa_def *cmp[3];
42 for (i = 0; i < 3; i++)
43 cmp[i] = nir_flt(b, nir_channel(b, input, i),
44 nir_build_imm(b, 1, 32, v));
45
46 nir_ssa_def *ltvals[3];
47 v.f32[0] = 12.92;
48 for (i = 0; i < 3; i++)
49 ltvals[i] = nir_fmul(b, nir_channel(b, input, i),
50 nir_build_imm(b, 1, 32, v));
51
52 nir_ssa_def *gtvals[3];
53
54 for (i = 0; i < 3; i++) {
55 v.f32[0] = 1.0/2.4;
56 gtvals[i] = nir_fpow(b, nir_channel(b, input, i),
57 nir_build_imm(b, 1, 32, v));
58 v.f32[0] = 1.055;
59 gtvals[i] = nir_fmul(b, gtvals[i],
60 nir_build_imm(b, 1, 32, v));
61 v.f32[0] = 0.055;
62 gtvals[i] = nir_fsub(b, gtvals[i],
63 nir_build_imm(b, 1, 32, v));
64 }
65
66 nir_ssa_def *comp[4];
67 for (i = 0; i < 3; i++)
68 comp[i] = nir_bcsel(b, cmp[i], ltvals[i], gtvals[i]);
69 comp[3] = nir_channels(b, input, 1 << 3);
70 return nir_vec(b, comp, 4);
71 }
72
73 static nir_shader *
build_resolve_compute_shader(struct radv_device * dev,bool is_integer,bool is_srgb,int samples)74 build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_srgb, int samples)
75 {
76 nir_builder b;
77 char name[64];
78 const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS,
79 false,
80 false,
81 GLSL_TYPE_FLOAT);
82 const struct glsl_type *img_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D,
83 false,
84 false,
85 GLSL_TYPE_FLOAT);
86 snprintf(name, 64, "meta_resolve_cs-%d-%s", samples, is_integer ? "int" : (is_srgb ? "srgb" : "float"));
87 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
88 b.shader->info.name = ralloc_strdup(b.shader, name);
89 b.shader->info.cs.local_size[0] = 16;
90 b.shader->info.cs.local_size[1] = 16;
91 b.shader->info.cs.local_size[2] = 1;
92
93 nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
94 sampler_type, "s_tex");
95 input_img->data.descriptor_set = 0;
96 input_img->data.binding = 0;
97
98 nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform,
99 img_type, "out_img");
100 output_img->data.descriptor_set = 0;
101 output_img->data.binding = 1;
102 nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
103 nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
104 nir_ssa_def *block_size = nir_imm_ivec4(&b,
105 b.shader->info.cs.local_size[0],
106 b.shader->info.cs.local_size[1],
107 b.shader->info.cs.local_size[2], 0);
108
109 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
110
111 nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
112 nir_intrinsic_set_base(src_offset, 0);
113 nir_intrinsic_set_range(src_offset, 16);
114 src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
115 src_offset->num_components = 2;
116 nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
117 nir_builder_instr_insert(&b, &src_offset->instr);
118
119 nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
120 nir_intrinsic_set_base(dst_offset, 0);
121 nir_intrinsic_set_range(dst_offset, 16);
122 dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
123 dst_offset->num_components = 2;
124 nir_ssa_dest_init(&dst_offset->instr, &dst_offset->dest, 2, 32, "dst_offset");
125 nir_builder_instr_insert(&b, &dst_offset->instr);
126
127 nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, global_id, &src_offset->dest.ssa), 0x3);
128 nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
129
130 radv_meta_build_resolve_shader_core(&b, is_integer, samples, input_img,
131 color, img_coord);
132
133 nir_ssa_def *outval = nir_load_var(&b, color);
134 if (is_srgb)
135 outval = radv_meta_build_resolve_srgb_conversion(&b, outval);
136
137 nir_ssa_def *coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa);
138 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store);
139 store->src[0] = nir_src_for_ssa(coord);
140 store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
141 store->src[2] = nir_src_for_ssa(outval);
142 store->variables[0] = nir_deref_var_create(store, output_img);
143 nir_builder_instr_insert(&b, &store->instr);
144 return b.shader;
145 }
146
147
148 static VkResult
create_layout(struct radv_device * device)149 create_layout(struct radv_device *device)
150 {
151 VkResult result;
152 /*
153 * two descriptors one for the image being sampled
154 * one for the buffer being written.
155 */
156 VkDescriptorSetLayoutCreateInfo ds_create_info = {
157 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
158 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
159 .bindingCount = 2,
160 .pBindings = (VkDescriptorSetLayoutBinding[]) {
161 {
162 .binding = 0,
163 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
164 .descriptorCount = 1,
165 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
166 .pImmutableSamplers = NULL
167 },
168 {
169 .binding = 1,
170 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
171 .descriptorCount = 1,
172 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
173 .pImmutableSamplers = NULL
174 },
175 }
176 };
177
178 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
179 &ds_create_info,
180 &device->meta_state.alloc,
181 &device->meta_state.resolve_compute.ds_layout);
182 if (result != VK_SUCCESS)
183 goto fail;
184
185
186 VkPipelineLayoutCreateInfo pl_create_info = {
187 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
188 .setLayoutCount = 1,
189 .pSetLayouts = &device->meta_state.resolve_compute.ds_layout,
190 .pushConstantRangeCount = 1,
191 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
192 };
193
194 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
195 &pl_create_info,
196 &device->meta_state.alloc,
197 &device->meta_state.resolve_compute.p_layout);
198 if (result != VK_SUCCESS)
199 goto fail;
200 return VK_SUCCESS;
201 fail:
202 return result;
203 }
204
205 static VkResult
create_resolve_pipeline(struct radv_device * device,int samples,bool is_integer,bool is_srgb,VkPipeline * pipeline)206 create_resolve_pipeline(struct radv_device *device,
207 int samples,
208 bool is_integer,
209 bool is_srgb,
210 VkPipeline *pipeline)
211 {
212 VkResult result;
213 struct radv_shader_module cs = { .nir = NULL };
214
215 cs.nir = build_resolve_compute_shader(device, is_integer, is_srgb, samples);
216
217 /* compute shader */
218
219 VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
220 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
221 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
222 .module = radv_shader_module_to_handle(&cs),
223 .pName = "main",
224 .pSpecializationInfo = NULL,
225 };
226
227 VkComputePipelineCreateInfo vk_pipeline_info = {
228 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
229 .stage = pipeline_shader_stage,
230 .flags = 0,
231 .layout = device->meta_state.resolve_compute.p_layout,
232 };
233
234 result = radv_CreateComputePipelines(radv_device_to_handle(device),
235 radv_pipeline_cache_to_handle(&device->meta_state.cache),
236 1, &vk_pipeline_info, NULL,
237 pipeline);
238 if (result != VK_SUCCESS)
239 goto fail;
240
241 ralloc_free(cs.nir);
242 return VK_SUCCESS;
243 fail:
244 ralloc_free(cs.nir);
245 return result;
246 }
247
248 VkResult
radv_device_init_meta_resolve_compute_state(struct radv_device * device)249 radv_device_init_meta_resolve_compute_state(struct radv_device *device)
250 {
251 struct radv_meta_state *state = &device->meta_state;
252 VkResult res;
253
254 res = create_layout(device);
255 if (res != VK_SUCCESS)
256 goto fail;
257
258 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
259 uint32_t samples = 1 << i;
260
261 res = create_resolve_pipeline(device, samples, false, false,
262 &state->resolve_compute.rc[i].pipeline);
263 if (res != VK_SUCCESS)
264 goto fail;
265
266 res = create_resolve_pipeline(device, samples, true, false,
267 &state->resolve_compute.rc[i].i_pipeline);
268 if (res != VK_SUCCESS)
269 goto fail;
270
271 res = create_resolve_pipeline(device, samples, false, true,
272 &state->resolve_compute.rc[i].srgb_pipeline);
273 if (res != VK_SUCCESS)
274 goto fail;
275
276 }
277
278 return VK_SUCCESS;
279 fail:
280 radv_device_finish_meta_resolve_compute_state(device);
281 return res;
282 }
283
284 void
radv_device_finish_meta_resolve_compute_state(struct radv_device * device)285 radv_device_finish_meta_resolve_compute_state(struct radv_device *device)
286 {
287 struct radv_meta_state *state = &device->meta_state;
288 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
289 radv_DestroyPipeline(radv_device_to_handle(device),
290 state->resolve_compute.rc[i].pipeline,
291 &state->alloc);
292
293 radv_DestroyPipeline(radv_device_to_handle(device),
294 state->resolve_compute.rc[i].i_pipeline,
295 &state->alloc);
296
297 radv_DestroyPipeline(radv_device_to_handle(device),
298 state->resolve_compute.rc[i].srgb_pipeline,
299 &state->alloc);
300 }
301
302 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
303 state->resolve_compute.ds_layout,
304 &state->alloc);
305 radv_DestroyPipelineLayout(radv_device_to_handle(device),
306 state->resolve_compute.p_layout,
307 &state->alloc);
308 }
309
310 static void
emit_resolve(struct radv_cmd_buffer * cmd_buffer,struct radv_image_view * src_iview,struct radv_image_view * dest_iview,const VkOffset2D * src_offset,const VkOffset2D * dest_offset,const VkExtent2D * resolve_extent)311 emit_resolve(struct radv_cmd_buffer *cmd_buffer,
312 struct radv_image_view *src_iview,
313 struct radv_image_view *dest_iview,
314 const VkOffset2D *src_offset,
315 const VkOffset2D *dest_offset,
316 const VkExtent2D *resolve_extent)
317 {
318 struct radv_device *device = cmd_buffer->device;
319 const uint32_t samples = src_iview->image->info.samples;
320 const uint32_t samples_log2 = ffs(samples) - 1;
321 radv_meta_push_descriptor_set(cmd_buffer,
322 VK_PIPELINE_BIND_POINT_COMPUTE,
323 device->meta_state.resolve_compute.p_layout,
324 0, /* set */
325 2, /* descriptorWriteCount */
326 (VkWriteDescriptorSet[]) {
327 {
328 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
329 .dstBinding = 0,
330 .dstArrayElement = 0,
331 .descriptorCount = 1,
332 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
333 .pImageInfo = (VkDescriptorImageInfo[]) {
334 {
335 .sampler = VK_NULL_HANDLE,
336 .imageView = radv_image_view_to_handle(src_iview),
337 .imageLayout = VK_IMAGE_LAYOUT_GENERAL },
338 }
339 },
340 {
341 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
342 .dstBinding = 1,
343 .dstArrayElement = 0,
344 .descriptorCount = 1,
345 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
346 .pImageInfo = (VkDescriptorImageInfo[]) {
347 {
348 .sampler = VK_NULL_HANDLE,
349 .imageView = radv_image_view_to_handle(dest_iview),
350 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
351 },
352 }
353 }
354 });
355
356 VkPipeline pipeline;
357 if (vk_format_is_int(src_iview->image->vk_format))
358 pipeline = device->meta_state.resolve_compute.rc[samples_log2].i_pipeline;
359 else if (vk_format_is_srgb(src_iview->image->vk_format))
360 pipeline = device->meta_state.resolve_compute.rc[samples_log2].srgb_pipeline;
361 else
362 pipeline = device->meta_state.resolve_compute.rc[samples_log2].pipeline;
363
364 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
365 VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
366
367 unsigned push_constants[4] = {
368 src_offset->x,
369 src_offset->y,
370 dest_offset->x,
371 dest_offset->y,
372 };
373 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
374 device->meta_state.resolve_compute.p_layout,
375 VK_SHADER_STAGE_COMPUTE_BIT, 0, 16,
376 push_constants);
377 radv_unaligned_dispatch(cmd_buffer, resolve_extent->width, resolve_extent->height, 1);
378
379 }
380
radv_meta_resolve_compute_image(struct radv_cmd_buffer * cmd_buffer,struct radv_image * src_image,VkImageLayout src_image_layout,struct radv_image * dest_image,VkImageLayout dest_image_layout,uint32_t region_count,const VkImageResolve * regions)381 void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
382 struct radv_image *src_image,
383 VkImageLayout src_image_layout,
384 struct radv_image *dest_image,
385 VkImageLayout dest_image_layout,
386 uint32_t region_count,
387 const VkImageResolve *regions)
388 {
389 struct radv_meta_saved_state saved_state;
390
391 for (uint32_t r = 0; r < region_count; ++r) {
392 const VkImageResolve *region = ®ions[r];
393 const uint32_t src_base_layer =
394 radv_meta_get_iview_layer(src_image, ®ion->srcSubresource,
395 ®ion->srcOffset);
396 VkImageSubresourceRange range;
397 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
398 range.baseMipLevel = region->srcSubresource.mipLevel;
399 range.levelCount = 1;
400 range.baseArrayLayer = src_base_layer;
401 range.layerCount = region->srcSubresource.layerCount;
402 radv_fast_clear_flush_image_inplace(cmd_buffer, src_image, &range);
403 }
404
405 radv_meta_save(&saved_state, cmd_buffer,
406 RADV_META_SAVE_COMPUTE_PIPELINE |
407 RADV_META_SAVE_CONSTANTS |
408 RADV_META_SAVE_DESCRIPTORS);
409
410 for (uint32_t r = 0; r < region_count; ++r) {
411 const VkImageResolve *region = ®ions[r];
412
413 assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
414 assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
415 assert(region->srcSubresource.layerCount == region->dstSubresource.layerCount);
416
417 const uint32_t src_base_layer =
418 radv_meta_get_iview_layer(src_image, ®ion->srcSubresource,
419 ®ion->srcOffset);
420
421 const uint32_t dest_base_layer =
422 radv_meta_get_iview_layer(dest_image, ®ion->dstSubresource,
423 ®ion->dstOffset);
424
425 const struct VkExtent3D extent =
426 radv_sanitize_image_extent(src_image->type, region->extent);
427 const struct VkOffset3D srcOffset =
428 radv_sanitize_image_offset(src_image->type, region->srcOffset);
429 const struct VkOffset3D dstOffset =
430 radv_sanitize_image_offset(dest_image->type, region->dstOffset);
431
432 for (uint32_t layer = 0; layer < region->srcSubresource.layerCount;
433 ++layer) {
434
435 struct radv_image_view src_iview;
436 radv_image_view_init(&src_iview, cmd_buffer->device,
437 &(VkImageViewCreateInfo) {
438 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
439 .image = radv_image_to_handle(src_image),
440 .viewType = radv_meta_get_view_type(src_image),
441 .format = src_image->vk_format,
442 .subresourceRange = {
443 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
444 .baseMipLevel = region->srcSubresource.mipLevel,
445 .levelCount = 1,
446 .baseArrayLayer = src_base_layer + layer,
447 .layerCount = 1,
448 },
449 });
450
451 struct radv_image_view dest_iview;
452 radv_image_view_init(&dest_iview, cmd_buffer->device,
453 &(VkImageViewCreateInfo) {
454 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
455 .image = radv_image_to_handle(dest_image),
456 .viewType = radv_meta_get_view_type(dest_image),
457 .format = vk_to_non_srgb_format(dest_image->vk_format),
458 .subresourceRange = {
459 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
460 .baseMipLevel = region->dstSubresource.mipLevel,
461 .levelCount = 1,
462 .baseArrayLayer = dest_base_layer + layer,
463 .layerCount = 1,
464 },
465 });
466
467 emit_resolve(cmd_buffer,
468 &src_iview,
469 &dest_iview,
470 &(VkOffset2D) {srcOffset.x, srcOffset.y },
471 &(VkOffset2D) {dstOffset.x, dstOffset.y },
472 &(VkExtent2D) {extent.width, extent.height });
473 }
474 }
475 radv_meta_restore(&saved_state, cmd_buffer);
476 }
477
478 /**
479 * Emit any needed resolves for the current subpass.
480 */
481 void
radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer * cmd_buffer)482 radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer)
483 {
484 struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
485 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
486 struct radv_meta_saved_state saved_state;
487 /* FINISHME(perf): Skip clears for resolve attachments.
488 *
489 * From the Vulkan 1.0 spec:
490 *
491 * If the first use of an attachment in a render pass is as a resolve
492 * attachment, then the loadOp is effectively ignored as the resolve is
493 * guaranteed to overwrite all pixels in the render area.
494 */
495
496 if (!subpass->has_resolve)
497 return;
498
499 /* Resolves happen before the end-of-subpass barriers get executed,
500 * so we have to make the attachment shader-readable */
501 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
502 RADV_CMD_FLAG_FLUSH_AND_INV_CB |
503 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
504 RADV_CMD_FLAG_INV_GLOBAL_L2 |
505 RADV_CMD_FLAG_INV_VMEM_L1;
506
507 for (uint32_t i = 0; i < subpass->color_count; ++i) {
508 VkAttachmentReference src_att = subpass->color_attachments[i];
509 VkAttachmentReference dest_att = subpass->resolve_attachments[i];
510
511 if (src_att.attachment == VK_ATTACHMENT_UNUSED ||
512 dest_att.attachment == VK_ATTACHMENT_UNUSED)
513 continue;
514
515 struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
516
517 VkImageSubresourceRange range;
518 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
519 range.baseMipLevel = 0;
520 range.levelCount = 1;
521 range.baseArrayLayer = 0;
522 range.layerCount = 1;
523 radv_fast_clear_flush_image_inplace(cmd_buffer, src_iview->image, &range);
524 }
525
526 radv_meta_save(&saved_state, cmd_buffer,
527 RADV_META_SAVE_COMPUTE_PIPELINE |
528 RADV_META_SAVE_CONSTANTS |
529 RADV_META_SAVE_DESCRIPTORS);
530
531 for (uint32_t i = 0; i < subpass->color_count; ++i) {
532 VkAttachmentReference src_att = subpass->color_attachments[i];
533 VkAttachmentReference dest_att = subpass->resolve_attachments[i];
534 struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
535 struct radv_image_view *dst_iview = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
536 if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
537 continue;
538
539 emit_resolve(cmd_buffer,
540 src_iview,
541 dst_iview,
542 &(VkOffset2D) { 0, 0 },
543 &(VkOffset2D) { 0, 0 },
544 &(VkExtent2D) { fb->width, fb->height });
545 }
546
547 radv_meta_restore(&saved_state, cmd_buffer);
548
549 for (uint32_t i = 0; i < subpass->color_count; ++i) {
550 VkAttachmentReference dest_att = subpass->resolve_attachments[i];
551 struct radv_image *dst_img = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment->image;
552 if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
553 continue;
554 VkImageSubresourceRange range;
555 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
556 range.baseMipLevel = 0;
557 range.levelCount = 1;
558 range.baseArrayLayer = 0;
559 range.layerCount = 1;
560 radv_fast_clear_flush_image_inplace(cmd_buffer, dst_img, &range);
561 }
562 }
563