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Searched defs:rd (Results 1 – 11 of 11) sorted by relevance

/art/runtime/interpreter/mterp/mips/
Dmain.S161 #define SEB(rd, rt) \ argument
163 #define SEH(rd, rt) \ argument
168 #define SEB(rd, rt) \ argument
171 #define SEH(rd, rt) \ argument
191 #define LSA(rd, rs, rt, sa) \ argument
200 #define LSA(rd, rs, rt, sa) \ argument
283 #define FETCH_ADVANCE_INST_RB(rd) \ argument
293 #define FETCH(rd, _count) lhu rd, ((_count) * 2)(rPC) argument
294 #define FETCH_S(rd, _count) lh rd, ((_count) * 2)(rPC) argument
301 #define FETCH_B(rd, _count, _byte) lbu rd, ((_count) * 2 + _byte)(rPC) argument
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/art/compiler/utils/arm/
Dassembler_arm_vixl.h113 void Rrx(vixl32::Register rd, vixl32::Register rn) { in Rrx()
118 void Mul(vixl32::Register rd, vixl32::Register rn, vixl32::Register rm) { in Mul()
125 void Add(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { in Add()
142 void Vmov(vixl32::DRegister rd, double imm) { in Vmov()
Dassembler_arm_vixl.cc99 void ArmVIXLAssembler::LoadImmediate(vixl32::Register rd, int32_t value) { in LoadImmediate()
425 void ArmVIXLAssembler::AddConstant(vixl32::Register rd, int32_t value) { in AddConstant()
430 void ArmVIXLAssembler::AddConstant(vixl32::Register rd, in AddConstant()
445 void ArmVIXLAssembler::AddConstantInIt(vixl32::Register rd, in AddConstantInIt()
/art/compiler/utils/mips64/
Dassembler_mips64.cc99 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, in EmitR()
113 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, in EmitRsd()
126 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, in EmitRtd()
303 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Addu()
311 void Mips64Assembler::Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Daddu()
319 void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Subu()
323 void Mips64Assembler::Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dsubu()
327 void Mips64Assembler::MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in MulR6()
331 void Mips64Assembler::MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in MuhR6()
335 void Mips64Assembler::DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in DivR6()
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Dassembler_mips64.h66 void TemplateLoadConst32(Asm* a, GpuRegister rd, int32_t value) { in TemplateLoadConst32()
97 void TemplateLoadConst64(Asm* a, Rtype rd, Vtype value) { in TemplateLoadConst64()
/art/compiler/utils/mips/
Dassembler_mips.cc258 Register rd, in EmitR()
454 void MipsAssembler::Addu(Register rd, Register rs, Register rt) { in Addu()
469 void MipsAssembler::Subu(Register rd, Register rs, Register rt) { in Subu()
493 void MipsAssembler::MulR2(Register rd, Register rs, Register rt) { in MulR2()
498 void MipsAssembler::DivR2(Register rd, Register rs, Register rt) { in DivR2()
504 void MipsAssembler::ModR2(Register rd, Register rs, Register rt) { in ModR2()
510 void MipsAssembler::DivuR2(Register rd, Register rs, Register rt) { in DivuR2()
516 void MipsAssembler::ModuR2(Register rd, Register rs, Register rt) { in ModuR2()
522 void MipsAssembler::MulR6(Register rd, Register rs, Register rt) { in MulR6()
527 void MipsAssembler::MuhR6(Register rd, Register rs, Register rt) { in MuhR6()
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/art/disassembler/
Ddisassembler_mips.cc524 uint32_t rd = (instruction >> 11) & 0x1f; // R-type. in Dump() local
/art/compiler/utils/arm64/
Djni_macro_assembler_arm64.cc72 void Arm64JNIMacroAssembler::AddConstant(XRegister rd, int32_t value, Condition cond) { in AddConstant()
76 void Arm64JNIMacroAssembler::AddConstant(XRegister rd, in AddConstant()
/art/libartbase/base/
Dmem_map_test.cc42 std::random_device rd; in RandomData() local
/art/compiler/utils/x86_64/
Dassembler_x86_64_test.cc58 std::random_device rd; in TEST() local
/art/compiler/optimizing/
Dcode_generator_arm_vixl.cc112 EmitAdrCode(ArmVIXLMacroAssembler* assembler, vixl32::Register rd, vixl32::Label* label) in EmitAdrCode()