1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Andy Fleming <afleming@gmail.com>
5 *
6 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
7 */
8
9 #ifndef _PHY_H
10 #define _PHY_H
11
12 #include <linux/list.h>
13 #include <linux/mii.h>
14 #include <linux/ethtool.h>
15 #include <linux/mdio.h>
16
17 #define PHY_FIXED_ID 0xa5a55a5a
18
19 #define PHY_MAX_ADDR 32
20
21 #define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */
22
23 #define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \
24 SUPPORTED_TP | \
25 SUPPORTED_MII)
26
27 #define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \
28 SUPPORTED_10baseT_Full)
29
30 #define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \
31 SUPPORTED_100baseT_Full)
32
33 #define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \
34 SUPPORTED_1000baseT_Full)
35
36 #define PHY_BASIC_FEATURES (PHY_10BT_FEATURES | \
37 PHY_100BT_FEATURES | \
38 PHY_DEFAULT_FEATURES)
39
40 #define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \
41 PHY_1000BT_FEATURES)
42
43 #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
44 SUPPORTED_10000baseT_Full)
45
46 #ifndef PHY_ANEG_TIMEOUT
47 #define PHY_ANEG_TIMEOUT 4000
48 #endif
49
50
51 typedef enum {
52 PHY_INTERFACE_MODE_MII,
53 PHY_INTERFACE_MODE_GMII,
54 PHY_INTERFACE_MODE_SGMII,
55 PHY_INTERFACE_MODE_SGMII_2500,
56 PHY_INTERFACE_MODE_QSGMII,
57 PHY_INTERFACE_MODE_TBI,
58 PHY_INTERFACE_MODE_RMII,
59 PHY_INTERFACE_MODE_RGMII,
60 PHY_INTERFACE_MODE_RGMII_ID,
61 PHY_INTERFACE_MODE_RGMII_RXID,
62 PHY_INTERFACE_MODE_RGMII_TXID,
63 PHY_INTERFACE_MODE_RTBI,
64 PHY_INTERFACE_MODE_XGMII,
65 PHY_INTERFACE_MODE_XAUI,
66 PHY_INTERFACE_MODE_RXAUI,
67 PHY_INTERFACE_MODE_SFI,
68 PHY_INTERFACE_MODE_INTERNAL,
69 PHY_INTERFACE_MODE_NONE, /* Must be last */
70
71 PHY_INTERFACE_MODE_COUNT,
72 } phy_interface_t;
73
74 static const char *phy_interface_strings[] = {
75 [PHY_INTERFACE_MODE_MII] = "mii",
76 [PHY_INTERFACE_MODE_GMII] = "gmii",
77 [PHY_INTERFACE_MODE_SGMII] = "sgmii",
78 [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
79 [PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
80 [PHY_INTERFACE_MODE_TBI] = "tbi",
81 [PHY_INTERFACE_MODE_RMII] = "rmii",
82 [PHY_INTERFACE_MODE_RGMII] = "rgmii",
83 [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
84 [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
85 [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
86 [PHY_INTERFACE_MODE_RTBI] = "rtbi",
87 [PHY_INTERFACE_MODE_XGMII] = "xgmii",
88 [PHY_INTERFACE_MODE_XAUI] = "xaui",
89 [PHY_INTERFACE_MODE_RXAUI] = "rxaui",
90 [PHY_INTERFACE_MODE_SFI] = "sfi",
91 [PHY_INTERFACE_MODE_INTERNAL] = "internal",
92 [PHY_INTERFACE_MODE_NONE] = "",
93 };
94
phy_string_for_interface(phy_interface_t i)95 static inline const char *phy_string_for_interface(phy_interface_t i)
96 {
97 /* Default to unknown */
98 if (i > PHY_INTERFACE_MODE_NONE)
99 i = PHY_INTERFACE_MODE_NONE;
100
101 return phy_interface_strings[i];
102 }
103
104
105 struct phy_device;
106
107 #define MDIO_NAME_LEN 32
108
109 struct mii_dev {
110 struct list_head link;
111 char name[MDIO_NAME_LEN];
112 void *priv;
113 int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
114 int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
115 u16 val);
116 int (*reset)(struct mii_dev *bus);
117 struct phy_device *phymap[PHY_MAX_ADDR];
118 u32 phy_mask;
119 };
120
121 /* struct phy_driver: a structure which defines PHY behavior
122 *
123 * uid will contain a number which represents the PHY. During
124 * startup, the driver will poll the PHY to find out what its
125 * UID--as defined by registers 2 and 3--is. The 32-bit result
126 * gotten from the PHY will be masked to
127 * discard any bits which may change based on revision numbers
128 * unimportant to functionality
129 *
130 */
131 struct phy_driver {
132 char *name;
133 unsigned int uid;
134 unsigned int mask;
135 unsigned int mmds;
136
137 u32 features;
138
139 /* Called to do any driver startup necessities */
140 /* Will be called during phy_connect */
141 int (*probe)(struct phy_device *phydev);
142
143 /* Called to configure the PHY, and modify the controller
144 * based on the results. Should be called after phy_connect */
145 int (*config)(struct phy_device *phydev);
146
147 /* Called when starting up the controller */
148 int (*startup)(struct phy_device *phydev);
149
150 /* Called when bringing down the controller */
151 int (*shutdown)(struct phy_device *phydev);
152
153 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
154 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
155 u16 val);
156 struct list_head list;
157 };
158
159 struct phy_device {
160 /* Information about the PHY type */
161 /* And management functions */
162 struct mii_dev *bus;
163 struct phy_driver *drv;
164 void *priv;
165
166 #ifdef CONFIG_DM_ETH
167 struct udevice *dev;
168 #else
169 struct eth_device *dev;
170 #endif
171
172 /* forced speed & duplex (no autoneg)
173 * partner speed & duplex & pause (autoneg)
174 */
175 int speed;
176 int duplex;
177
178 /* The most recently read link state */
179 int link;
180 int port;
181 phy_interface_t interface;
182
183 u32 advertising;
184 u32 supported;
185 u32 mmds;
186
187 int autoneg;
188 int addr;
189 int pause;
190 int asym_pause;
191 u32 phy_id;
192 u32 flags;
193 };
194
195 struct fixed_link {
196 int phy_id;
197 int duplex;
198 int link_speed;
199 int pause;
200 int asym_pause;
201 };
202
phy_read(struct phy_device * phydev,int devad,int regnum)203 static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
204 {
205 struct mii_dev *bus = phydev->bus;
206
207 return bus->read(bus, phydev->addr, devad, regnum);
208 }
209
phy_write(struct phy_device * phydev,int devad,int regnum,u16 val)210 static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
211 u16 val)
212 {
213 struct mii_dev *bus = phydev->bus;
214
215 return bus->write(bus, phydev->addr, devad, regnum, val);
216 }
217
218 #ifdef CONFIG_PHYLIB_10G
219 extern struct phy_driver gen10g_driver;
220
221 /* For now, XGMII is the only 10G interface */
is_10g_interface(phy_interface_t interface)222 static inline int is_10g_interface(phy_interface_t interface)
223 {
224 return interface == PHY_INTERFACE_MODE_XGMII;
225 }
226
227 #endif
228
229 int phy_init(void);
230 int phy_reset(struct phy_device *phydev);
231 struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
232 phy_interface_t interface);
233 #ifdef CONFIG_DM_ETH
234 void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
235 struct phy_device *phy_connect(struct mii_dev *bus, int addr,
236 struct udevice *dev,
237 phy_interface_t interface);
238 #else
239 void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
240 struct phy_device *phy_connect(struct mii_dev *bus, int addr,
241 struct eth_device *dev,
242 phy_interface_t interface);
243 #endif
244 int phy_startup(struct phy_device *phydev);
245 int phy_config(struct phy_device *phydev);
246 int phy_shutdown(struct phy_device *phydev);
247 int phy_register(struct phy_driver *drv);
248 int phy_set_supported(struct phy_device *phydev, u32 max_speed);
249 int genphy_config_aneg(struct phy_device *phydev);
250 int genphy_restart_aneg(struct phy_device *phydev);
251 int genphy_update_link(struct phy_device *phydev);
252 int genphy_parse_link(struct phy_device *phydev);
253 int genphy_config(struct phy_device *phydev);
254 int genphy_startup(struct phy_device *phydev);
255 int genphy_shutdown(struct phy_device *phydev);
256 int gen10g_config(struct phy_device *phydev);
257 int gen10g_startup(struct phy_device *phydev);
258 int gen10g_shutdown(struct phy_device *phydev);
259 int gen10g_discover_mmds(struct phy_device *phydev);
260
261 int phy_b53_init(void);
262 int phy_mv88e61xx_init(void);
263 int phy_aquantia_init(void);
264 int phy_atheros_init(void);
265 int phy_broadcom_init(void);
266 int phy_cortina_init(void);
267 int phy_davicom_init(void);
268 int phy_et1011c_init(void);
269 int phy_lxt_init(void);
270 int phy_marvell_init(void);
271 int phy_micrel_ksz8xxx_init(void);
272 int phy_micrel_ksz90x1_init(void);
273 int phy_meson_gxl_init(void);
274 int phy_natsemi_init(void);
275 int phy_realtek_init(void);
276 int phy_smsc_init(void);
277 int phy_teranetics_init(void);
278 int phy_ti_init(void);
279 int phy_vitesse_init(void);
280 int phy_xilinx_init(void);
281 int phy_mscc_init(void);
282 int phy_fixed_init(void);
283
284 int board_phy_config(struct phy_device *phydev);
285 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
286
287 /**
288 * phy_get_interface_by_name() - Look up a PHY interface name
289 *
290 * @str: PHY interface name, e.g. "mii"
291 * @return PHY_INTERFACE_MODE_... value, or -1 if not found
292 */
293 int phy_get_interface_by_name(const char *str);
294
295 /**
296 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
297 * is RGMII (all variants)
298 * @phydev: the phy_device struct
299 */
phy_interface_is_rgmii(struct phy_device * phydev)300 static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
301 {
302 return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
303 phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
304 }
305
306 /**
307 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
308 * is SGMII (all variants)
309 * @phydev: the phy_device struct
310 */
phy_interface_is_sgmii(struct phy_device * phydev)311 static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
312 {
313 return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
314 phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
315 }
316
317 /* PHY UIDs for various PHYs that are referenced in external code */
318 #define PHY_UID_CS4340 0x13e51002
319 #define PHY_UID_CS4223 0x03e57003
320 #define PHY_UID_TN2020 0x00a19410
321
322 #endif
323