| /art/compiler/debug/ |
| D | elf_debug_frame_writer.h | 45 for (int reg = 0; reg < 13; reg++) { in WriteCIE() local
53 for (int reg = 0; reg < 32; reg++) { in WriteCIE() local
68 for (int reg = 0; reg < 30; reg++) { in WriteCIE() local
76 for (int reg = 0; reg < 32; reg++) { in WriteCIE() local
92 for (int reg = 1; reg < 26; reg++) { in WriteCIE() local
100 for (int reg = 0; reg < 32; reg++) { in WriteCIE() local
118 for (int reg = 0; reg < 8; reg++) { in WriteCIE() local
129 for (int reg = 0; reg < 8; reg++) { in WriteCIE() local
142 for (int reg = 0; reg < 16; reg++) { in WriteCIE() local
152 for (int reg = 0; reg < 16; reg++) { in WriteCIE() local
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| /art/libelffile/dwarf/ |
| D | debug_frame_opcode_writer.h | 73 void ALWAYS_INLINE RelOffset(Reg reg, int offset) { in RelOffset()
117 void ALWAYS_INLINE Offset(Reg reg, int offset) { in Offset()
139 void ALWAYS_INLINE Restore(Reg reg) { in Restore()
151 void ALWAYS_INLINE Undefined(Reg reg) { in Undefined()
159 void ALWAYS_INLINE SameValue(Reg reg) { in SameValue()
168 void ALWAYS_INLINE Register(Reg reg, Reg new_reg) { in Register()
191 void ALWAYS_INLINE DefCFA(Reg reg, int offset) { in DefCFA()
208 void ALWAYS_INLINE DefCFARegister(Reg reg) { in DefCFARegister()
234 void ALWAYS_INLINE ValOffset(Reg reg, int offset) { in ValOffset()
261 void ALWAYS_INLINE Expression(Reg reg, uint8_t* expr, int expr_size) { in Expression()
[all …]
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| /art/runtime/arch/mips64/ |
| D | context_mips64.h | 48 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
53 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
58 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
66 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
71 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
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| D | context_mips64.cc | 58 void Mips64Context::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR()
65 void Mips64Context::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR()
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| /art/runtime/arch/arm/ |
| D | context_arm.h | 53 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
58 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
63 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
71 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
76 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
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| D | context_arm.cc | 61 void ArmContext::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR()
68 void ArmContext::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR()
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| /art/runtime/arch/x86_64/ |
| D | context_x86_64.h | 52 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
57 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
62 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
70 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
75 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
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| D | asm_support_x86_64.S | 75 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
76 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
77 #define CFI_RESTORE(reg) .cfi_restore reg argument
78 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
86 #define CFI_DEF_CFA(reg,size) argument
87 #define CFI_DEF_CFA_REGISTER(reg) argument
88 #define CFI_RESTORE(reg) argument
89 #define CFI_REL_OFFSET(reg,size) argument
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| /art/runtime/arch/mips/ |
| D | context_mips.h | 48 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
53 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
58 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
66 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
71 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
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| D | context_mips.cc | 67 void MipsContext::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR()
74 void MipsContext::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR()
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| /art/compiler/utils/x86/ |
| D | managed_register_x86_test.cc | 26 X86ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
32 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); in TEST() local
66 X86ManagedRegister reg = X86ManagedRegister::FromXmmRegister(XMM0); in TEST() local
92 X86ManagedRegister reg = X86ManagedRegister::FromX87Register(ST0); in TEST() local
118 X86ManagedRegister reg = X86ManagedRegister::FromRegisterPair(EAX_EDX); in TEST() local
256 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); in TEST() local
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| D | assembler_x86.h | 87 bool IsRegister(Register reg) const { in IsRegister()
137 explicit Operand(Register reg) : fixup_(nullptr) { SetModRM(3, reg); } in Operand()
753 void LockCmpxchgl(const Address& address, Register reg) { in LockCmpxchgl()
777 void PoisonHeapReference(Register reg) { negl(reg); } in PoisonHeapReference()
779 void UnpoisonHeapReference(Register reg) { negl(reg); } in UnpoisonHeapReference()
781 void MaybePoisonHeapReference(Register reg) { in MaybePoisonHeapReference()
787 void MaybeUnpoisonHeapReference(Register reg) { in MaybeUnpoisonHeapReference()
863 inline void X86Assembler::EmitRegisterOperand(int rm, int reg) { in EmitRegisterOperand()
869 inline void X86Assembler::EmitXmmRegisterOperand(int rm, XmmRegister reg) { in EmitXmmRegisterOperand()
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| D | managed_register_x86.cc | 41 RegisterPair reg; // Used to verify that the enum is in sync. member
53 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { in operator <<()
114 std::ostream& operator<<(std::ostream& os, const X86ManagedRegister& reg) { in operator <<()
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| /art/compiler/utils/x86_64/ |
| D | managed_register_x86_64_test.cc | 25 X86_64ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
31 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); in TEST() local
65 X86_64ManagedRegister reg = X86_64ManagedRegister::FromXmmRegister(XMM0); in TEST() local
91 X86_64ManagedRegister reg = X86_64ManagedRegister::FromX87Register(ST0); in TEST() local
117 X86_64ManagedRegister reg = X86_64ManagedRegister::FromRegisterPair(EAX_EDX); in TEST() local
255 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); in TEST() local
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| D | assembler_x86_64.h | 114 bool IsRegister(CpuRegister reg) const { in IsRegister()
173 explicit Operand(CpuRegister reg) : rex_(0), length_(0), fixup_(nullptr) { SetModRM(3, reg); } in Operand()
839 void LockCmpxchgl(const Address& address, CpuRegister reg) { in LockCmpxchgl()
843 void LockCmpxchgq(const Address& address, CpuRegister reg) { in LockCmpxchgq()
896 void PoisonHeapReference(CpuRegister reg) { negl(reg); } in PoisonHeapReference()
898 void UnpoisonHeapReference(CpuRegister reg) { negl(reg); } in UnpoisonHeapReference()
900 void MaybePoisonHeapReference(CpuRegister reg) { in MaybePoisonHeapReference()
906 void MaybeUnpoisonHeapReference(CpuRegister reg) { in MaybeUnpoisonHeapReference()
985 inline void X86_64Assembler::EmitRegisterOperand(uint8_t rm, uint8_t reg) { in EmitRegisterOperand()
991 inline void X86_64Assembler::EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg) { in EmitXmmRegisterOperand()
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| D | managed_register_x86_64.cc | 40 RegisterPair reg; // Used to verify that the enum is in sync. member
52 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { in operator <<()
109 std::ostream& operator<<(std::ostream& os, const X86_64ManagedRegister& reg) { in operator <<()
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| /art/runtime/arch/arm64/ |
| D | context_arm64.h | 53 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
58 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
63 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
72 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
77 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
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| /art/compiler/utils/arm/ |
| D | managed_register_arm_test.cc | 25 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm(); in TEST() local
31 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); in TEST() local
69 ArmManagedRegister reg = ArmManagedRegister::FromSRegister(S0); in TEST() local
126 ArmManagedRegister reg = ArmManagedRegister::FromDRegister(D0); in TEST() local
227 ArmManagedRegister reg = ArmManagedRegister::FromRegisterPair(R0_R1); in TEST() local
459 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); in TEST() local
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| /art/compiler/utils/mips64/ |
| D | managed_register_mips64_test.cc | 26 Mips64ManagedRegister reg = ManagedRegister::NoRegister().AsMips64(); in TEST() local
32 Mips64ManagedRegister reg = Mips64ManagedRegister::FromGpuRegister(ZERO); in TEST() local
111 Mips64ManagedRegister reg = Mips64ManagedRegister::FromFpuRegister(F0); in TEST() local
157 Mips64ManagedRegister reg = Mips64ManagedRegister::FromVectorRegister(W0); in TEST() local
279 Mips64ManagedRegister reg = Mips64ManagedRegister::FromFpuRegister(F0); in TEST() local
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| /art/compiler/utils/arm64/ |
| D | managed_register_arm64_test.cc | 27 Arm64ManagedRegister reg = ManagedRegister::NoRegister().AsArm64(); in TEST() local
34 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); in TEST() local
107 Arm64ManagedRegister reg = Arm64ManagedRegister::FromWRegister(W0); in TEST() local
169 Arm64ManagedRegister reg = Arm64ManagedRegister::FromDRegister(D0); in TEST() local
220 Arm64ManagedRegister reg = Arm64ManagedRegister::FromSRegister(S0); in TEST() local
376 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); in TEST() local
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| D | assembler_arm64.cc | 106 static inline dwarf::Reg DWARFReg(CPURegister reg) { in DWARFReg()
169 void Arm64Assembler::PoisonHeapReference(Register reg) { in PoisonHeapReference()
175 void Arm64Assembler::UnpoisonHeapReference(Register reg) { in UnpoisonHeapReference()
181 void Arm64Assembler::MaybePoisonHeapReference(Register reg) { in MaybePoisonHeapReference()
187 void Arm64Assembler::MaybeUnpoisonHeapReference(Register reg) { in MaybeUnpoisonHeapReference()
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| /art/runtime/arch/x86/ |
| D | context_x86.h | 52 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
57 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
62 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
70 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
75 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
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| D | asm_support_x86.S | 76 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
77 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
78 #define CFI_RESTORE(reg) .cfi_restore reg argument
79 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
88 #define CFI_DEF_CFA(reg,size) argument
89 #define CFI_DEF_CFA_REGISTER(reg) argument
90 #define CFI_RESTORE(reg) argument
91 #define CFI_REL_OFFSET(reg,size) argument
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| /art/runtime/verifier/ |
| D | register_line.h | 373 const uint32_t reg = pair.first; in IterateRegToLockDepths() local
394 bool IsSetLockDepth(size_t reg, size_t depth) { in IsSetLockDepth()
403 bool SetRegToLockDepth(size_t reg, size_t depth) { in SetRegToLockDepth()
419 void ClearAllRegToLockDepths(size_t reg) { in ClearAllRegToLockDepths()
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| /art/compiler/utils/mips/ |
| D | managed_register_mips.cc | 92 std::ostream& operator<<(std::ostream& os, const MipsManagedRegister& reg) { in operator <<()
97 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { in operator <<()
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