| /external/libvpx/libvpx/vpx_ports/ |
| D | asmdefs_mmi.h | 21 #define MMI_ADDU(reg1, reg2, reg3) \ argument
24 #define MMI_ADDIU(reg1, reg2, immediate) \ argument
27 #define MMI_ADDI(reg1, reg2, immediate) \ argument
30 #define MMI_SUBU(reg1, reg2, reg3) \ argument
36 #define MMI_SRL(reg1, reg2, shift) \ argument
39 #define MMI_SLL(reg1, reg2, shift) \ argument
50 #define MMI_ADDU(reg1, reg2, reg3) \ argument
53 #define MMI_ADDIU(reg1, reg2, immediate) \ argument
56 #define MMI_ADDI(reg1, reg2, immediate) \ argument
59 #define MMI_SUBU(reg1, reg2, reg3) \ argument
[all …]
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| /external/u-boot/arch/arm/mach-imx/ |
| D | sip.c | 10 unsigned long reg1, unsigned long reg2) in call_imx_sip()
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| /external/u-boot/post/lib_powerpc/ |
| D | two.c | 82 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_two() local
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| D | twox.c | 82 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_twox() local
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| D | andi.c | 62 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_andi() local
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| D | threei.c | 76 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_threei() local
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| D | srawi.c | 62 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_srawi() local
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| D | three.c | 156 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_three() local
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| D | threex.c | 126 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_threex() local
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| D | rlwinm.c | 60 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_rlwinm() local
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| D | rlwnm.c | 61 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_rlwnm() local
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| D | rlwimi.c | 63 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_rlwimi() local
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| /external/u-boot/drivers/mtd/nand/ |
| D | nand_ecc.c | 68 uint8_t idx, reg1, reg2, reg3, tmp1, tmp2; in nand_calculate_ecc() local
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| /external/capstone/arch/X86/ |
| D | X86Mapping.c | 47236 x86_reg reg1, reg2; member
47505 bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, x86_reg *reg2) in X86_insn_reg_intel2()
47522 bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, x86_reg *reg2) in X86_insn_reg_att2()
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| /external/libvpx/libvpx/third_party/libyuv/source/ |
| D | compare_msa.cc | 59 v4i32 reg0 = {0}, reg1 = {0}, reg2 = {0}, reg3 = {0}; in SumSquareError_MSA() local
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| D | scale_msa.cc | 78 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
304 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
567 v8u16 reg0, reg1; in ScaleFilterCols_MSA() local
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
766 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_0_Box_MSA() local
860 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_1_Box_MSA() local
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| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
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| D | row_msa.cc | 481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
570 v8u16 reg0, reg1, reg2; in I422ToARGB4444Row_MSA() local
610 v8u16 reg0, reg1, reg2; in I422ToARGB1555Row_MSA() local
774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
1089 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; in ARGBToUV444Row_MSA() local
1163 v4u32 reg0, reg1, reg2, reg3; in ARGBMultiplyRow_MSA() local
1243 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1311 v8i16 reg0, reg1, reg2; in ARGBToRGB565DitherRow_MSA() local
1379 v4u32 reg0, reg1, reg2, reg3, rgba_scale; in ARGBShadeRow_MSA() local
[all …]
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| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_odd_process_store() local
354 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_even_process_store() local
434 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_odd_process_store() local
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| D | txfm_macros_msa.h | 16 #define DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) \ argument
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| /external/v8/src/interpreter/ |
| D | bytecode-register.cc | 97 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, in AreContiguous()
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| /external/libyuv/files/source/ |
| D | row_msa.cc | 481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
570 v8u16 reg0, reg1, reg2; in I422ToARGB4444Row_MSA() local
610 v8u16 reg0, reg1, reg2; in I422ToARGB1555Row_MSA() local
774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
1085 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; in ARGBToUV444Row_MSA() local
1159 v4u32 reg0, reg1, reg2, reg3; in ARGBMultiplyRow_MSA() local
1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1305 v8i16 reg0, reg1, reg2; in ARGBToRGB565DitherRow_MSA() local
1373 v4u32 reg0, reg1, reg2, reg3, rgba_scale; in ARGBShadeRow_MSA() local
[all …]
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| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
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| /external/v8/src/arm64/ |
| D | deoptimizer-arm64.cc | 44 CPURegister reg1 = copy_to_input.PopLowestIndex(); in CopyRegListToFrame() local
75 CPURegister reg1 = restore_list.PopLowestIndex(); in RestoreRegList() local
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| /external/perfetto/src/profiling/memory/ |
| D | shared_ring_buffer.cc | 151 void* reg1 = mmap(region, size_with_meta, PROT_READ | PROT_WRITE, in Initialize() local
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