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Searched defs:reg3 (Results 1 – 23 of 23) sorted by relevance

/external/libvpx/libvpx/vpx_ports/
Dasmdefs_mmi.h21 #define MMI_ADDU(reg1, reg2, reg3) \ argument
30 #define MMI_SUBU(reg1, reg2, reg3) \ argument
50 #define MMI_ADDU(reg1, reg2, reg3) \ argument
59 #define MMI_SUBU(reg1, reg2, reg3) \ argument
/external/u-boot/drivers/mtd/nand/
Dnand_ecc.c68 uint8_t idx, reg1, reg2, reg3, tmp1, tmp2; in nand_calculate_ecc() local
/external/libvpx/libvpx/third_party/libyuv/source/
Dcompare_msa.cc59 v4i32 reg0 = {0}, reg1 = {0}, reg2 = {0}, reg3 = {0}; in SumSquareError_MSA() local
Drotate_msa.cc85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
Dscale_msa.cc78 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
304 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
766 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_0_Box_MSA() local
860 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_1_Box_MSA() local
Drow_msa.cc481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
1089 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; in ARGBToUV444Row_MSA() local
1163 v4u32 reg0, reg1, reg2, reg3; in ARGBMultiplyRow_MSA() local
1243 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1379 v4u32 reg0, reg1, reg2, reg3, rgba_scale; in ARGBShadeRow_MSA() local
1512 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; in ARGB1555ToARGBRow_MSA() local
1561 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in RGB565ToARGBRow_MSA() local
1660 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGB1555ToYRow_MSA() local
[all …]
/external/libvpx/libvpx/vpx_dsp/mips/
Didct32x32_msa.c44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_odd_process_store() local
354 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_even_process_store() local
434 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_odd_process_store() local
Didct16x16_msa.c16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_rows_msa() local
110 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_columns_addblk_msa() local
/external/v8/src/interpreter/
Dbytecode-register.cc97 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, in AreContiguous()
/external/libyuv/files/source/
Drotate_msa.cc85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
Drow_msa.cc481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
1085 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; in ARGBToUV444Row_MSA() local
1159 v4u32 reg0, reg1, reg2, reg3; in ARGBMultiplyRow_MSA() local
1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1373 v4u32 reg0, reg1, reg2, reg3, rgba_scale; in ARGBShadeRow_MSA() local
1506 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; in ARGB1555ToARGBRow_MSA() local
1553 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in RGB565ToARGBRow_MSA() local
1648 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGB1555ToYRow_MSA() local
[all …]
Dscale_msa.cc70 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
296 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
/external/vixl/src/aarch64/
Dmacro-assembler-aarch64.cc2908 const Register& reg3, in Include()
2922 const FPRegister& reg3, in Include()
2942 const Register& reg3, in Exclude()
2952 const FPRegister& reg3, in Exclude()
2962 const CPURegister& reg3, in Exclude()
Dassembler-aarch64.cc5938 const CPURegister& reg3, in AreAliased()
5977 const CPURegister& reg3, in AreSameSizeAndType()
5997 const CPURegister& reg3, in AreEven()
6018 const CPURegister& reg3, in AreConsecutive()
6046 const VRegister& reg3, in AreSameFormat()
6059 const VRegister& reg3, in AreConsecutive()
/external/vixl/src/aarch32/
Dinstructions-aarch32.h554 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3) in VRegisterList()
557 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3, VRegister reg4) in VRegisterList()
Dmacro-assembler-aarch32.cc449 CPURegister reg3, in Printf()
/external/v8/src/arm64/
Dassembler-arm64.cc219 const CPURegister& reg3, const CPURegister& reg4, in AreAliased()
256 const CPURegister& reg3, const CPURegister& reg4, in AreSameSizeAndType()
272 const VRegister& reg3, const VRegister& reg4) { in AreSameFormat()
280 const VRegister& reg3, const VRegister& reg4) { in AreConsecutive()
/external/pcre/dist2/src/sljit/
DsljitNativeARM_T2_32.c72 #define IS_3_LO_REGS(reg1, reg2, reg3) \ argument
/external/v8/src/arm/
Dmacro-assembler-arm.cc2367 Register reg3, in GetRegisterThatIsNotOneOf()
/external/v8/src/ppc/
Dmacro-assembler-ppc.cc2867 Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, in GetRegisterThatIsNotOneOf()
/external/v8/src/s390/
Dmacro-assembler-s390.cc2055 Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, in GetRegisterThatIsNotOneOf()
/external/v8/src/mips/
Dmacro-assembler-mips.cc5386 Register reg3, in GetRegisterThatIsNotOneOf()
/external/v8/src/mips64/
Dmacro-assembler-mips64.cc5784 Register reg3, in GetRegisterThatIsNotOneOf()