| /external/u-boot/board/freescale/ls1046ardb/ |
| D | cpld.c | 31 u8 reg4 = CPLD_READ(soft_mux_on); in cpld_set_altbank() local
53 u8 reg4 = CPLD_READ(soft_mux_on); in cpld_set_defbank() local
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| /external/u-boot/board/freescale/ls1043ardb/ |
| D | cpld.c | 31 u8 reg4 = CPLD_READ(soft_mux_on); in cpld_set_altbank() local
53 u8 reg4 = CPLD_READ(soft_mux_on); in cpld_set_defbank() local
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| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_odd_process_store() local
354 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_even_process_store() local
434 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_odd_process_store() local
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| D | idct16x16_msa.c | 15 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_rows_msa() local
109 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_columns_addblk_msa() local
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| /external/v8/src/interpreter/ |
| D | bytecode-register.cc | 98 Register reg4, Register reg5) { in AreContiguous()
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| /external/libyuv/files/source/ |
| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
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| D | row_msa.cc | 774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1506 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; in ARGB1555ToARGBRow_MSA() local
1553 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in RGB565ToARGBRow_MSA() local
1648 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGB1555ToYRow_MSA() local
1705 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in RGB565ToYRow_MSA() local
2666 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in I444ToARGBRow_MSA() local
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| D | scale_msa.cc | 133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
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| /external/libvpx/libvpx/third_party/libyuv/source/ |
| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
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| D | scale_msa.cc | 141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
766 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_0_Box_MSA() local
860 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_1_Box_MSA() local
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| D | row_msa.cc | 774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
1243 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1512 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; in ARGB1555ToARGBRow_MSA() local
1561 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in RGB565ToARGBRow_MSA() local
1660 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGB1555ToYRow_MSA() local
1717 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in RGB565ToYRow_MSA() local
2678 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in I444ToARGBRow_MSA() local
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| /external/u-boot/arch/arm/cpu/arm1136/mx35/ |
| D | generic.c | 196 u32 reg4 = readl(&ccm->pdr4); in mxc_get_main_clock() local
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.cc | 2909 const Register& reg4) { in Include()
2923 const FPRegister& reg4) { in Include()
2943 const Register& reg4) { in Exclude()
2953 const FPRegister& reg4) { in Exclude()
2963 const CPURegister& reg4) { in Exclude()
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| D | assembler-aarch64.cc | 5939 const CPURegister& reg4, in AreAliased()
5978 const CPURegister& reg4, in AreSameSizeAndType()
5998 const CPURegister& reg4, in AreEven()
6019 const CPURegister& reg4) { in AreConsecutive()
6047 const VRegister& reg4) { in AreSameFormat()
6060 const VRegister& reg4) { in AreConsecutive()
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| /external/u-boot/board/gdsys/common/ |
| D | osd.c | 203 u8 reg0, reg4, reg8, reg12, reg18, reg20; in ics8n3qv01_set() local
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| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 219 const CPURegister& reg3, const CPURegister& reg4, in AreAliased()
256 const CPURegister& reg3, const CPURegister& reg4, in AreSameSizeAndType()
272 const VRegister& reg3, const VRegister& reg4) { in AreSameFormat()
280 const VRegister& reg3, const VRegister& reg4) { in AreConsecutive()
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.cc | 450 CPURegister reg4) { in Printf()
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| D | instructions-aarch32.h | 557 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3, VRegister reg4) in VRegisterList()
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| /external/v8/src/arm/ |
| D | macro-assembler-arm.cc | 2368 Register reg4, in GetRegisterThatIsNotOneOf()
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| /external/v8/src/ppc/ |
| D | macro-assembler-ppc.cc | 2868 Register reg4, Register reg5, in GetRegisterThatIsNotOneOf()
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| /external/v8/src/s390/ |
| D | macro-assembler-s390.cc | 2056 Register reg4, Register reg5, in GetRegisterThatIsNotOneOf()
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| /external/v8/src/mips/ |
| D | macro-assembler-mips.cc | 5387 Register reg4, in GetRegisterThatIsNotOneOf()
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| /external/v8/src/mips64/ |
| D | macro-assembler-mips64.cc | 5785 Register reg4, in GetRegisterThatIsNotOneOf()
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