| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_odd_process_store() local
354 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_even_process_store() local
434 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_odd_process_store() local
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| D | idct16x16_msa.c | 16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_rows_msa() local
110 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_columns_addblk_msa() local
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| /external/u-boot/board/freescale/ls1046ardb/ |
| D | cpld.c | 34 u8 reg7 = CPLD_READ(vbank); in cpld_set_altbank() local
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| /external/u-boot/board/freescale/ls1043ardb/ |
| D | cpld.c | 34 u8 reg7 = CPLD_READ(vbank); in cpld_set_altbank() local
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| /external/libyuv/files/source/ |
| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
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| D | scale_msa.cc | 133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
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| D | row_msa.cc | 826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
2666 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in I444ToARGBRow_MSA() local
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| /external/libvpx/libvpx/third_party/libyuv/source/ |
| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
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| D | scale_msa.cc | 141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
767 v8i16 reg6, reg7, reg8, reg9, reg10, reg11; in ScaleRowDown34_0_Box_MSA() local
861 v8i16 reg6, reg7, reg8, reg9, reg10, reg11; in ScaleRowDown34_1_Box_MSA() local
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| D | row_msa.cc | 826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
1243 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
2678 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in I444ToARGBRow_MSA() local
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 5942 const CPURegister& reg7, in AreAliased()
5981 const CPURegister& reg7, in AreSameSizeAndType()
6001 const CPURegister& reg7, in AreEven()
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| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 221 const CPURegister& reg7, const CPURegister& reg8) { in AreAliased()
258 const CPURegister& reg7, const CPURegister& reg8) { in AreSameSizeAndType()
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