1 /*
2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 #include <arch.h>
7 #include <arch_helpers.h>
8 #include <arm_xlat_tables.h>
9 #include <assert.h>
10 #include <debug.h>
11 #include <mmio.h>
12 #include <plat_arm.h>
13 #include <platform_def.h>
14
15 extern const mmap_region_t plat_arm_mmap[];
16
17 /* Weak definitions may be overridden in specific ARM standard platform */
18 #pragma weak plat_get_ns_image_entrypoint
19 #pragma weak plat_arm_get_mmap
20
21 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid
22 * conflicts with the definition in plat/common. */
23 #if ERROR_DEPRECATED
24 #pragma weak plat_get_syscnt_freq2
25 #endif
26
27 /*
28 * Set up the page tables for the generic and platform-specific memory regions.
29 * The extents of the generic memory regions are specified by the function
30 * arguments and consist of:
31 * - Trusted SRAM seen by the BL image;
32 * - Code section;
33 * - Read-only data section;
34 * - Coherent memory region, if applicable.
35 */
arm_setup_page_tables(uintptr_t total_base,size_t total_size,uintptr_t code_start,uintptr_t code_limit,uintptr_t rodata_start,uintptr_t rodata_limit,uintptr_t coh_start,uintptr_t coh_limit)36 void arm_setup_page_tables(uintptr_t total_base,
37 size_t total_size,
38 uintptr_t code_start,
39 uintptr_t code_limit,
40 uintptr_t rodata_start,
41 uintptr_t rodata_limit
42 #if USE_COHERENT_MEM
43 ,
44 uintptr_t coh_start,
45 uintptr_t coh_limit
46 #endif
47 )
48 {
49 /*
50 * Map the Trusted SRAM with appropriate memory attributes.
51 * Subsequent mappings will adjust the attributes for specific regions.
52 */
53 VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
54 (void *) total_base, (void *) (total_base + total_size));
55 mmap_add_region(total_base, total_base,
56 total_size,
57 MT_MEMORY | MT_RW | MT_SECURE);
58
59 /* Re-map the code section */
60 VERBOSE("Code region: %p - %p\n",
61 (void *) code_start, (void *) code_limit);
62 mmap_add_region(code_start, code_start,
63 code_limit - code_start,
64 MT_CODE | MT_SECURE);
65
66 /* Re-map the read-only data section */
67 VERBOSE("Read-only data region: %p - %p\n",
68 (void *) rodata_start, (void *) rodata_limit);
69 mmap_add_region(rodata_start, rodata_start,
70 rodata_limit - rodata_start,
71 MT_RO_DATA | MT_SECURE);
72
73 #if USE_COHERENT_MEM
74 /* Re-map the coherent memory region */
75 VERBOSE("Coherent region: %p - %p\n",
76 (void *) coh_start, (void *) coh_limit);
77 mmap_add_region(coh_start, coh_start,
78 coh_limit - coh_start,
79 MT_DEVICE | MT_RW | MT_SECURE);
80 #endif
81
82 /* Now (re-)map the platform-specific memory regions */
83 mmap_add(plat_arm_get_mmap());
84
85 /* Create the page tables to reflect the above mappings */
86 init_xlat_tables();
87 }
88
plat_get_ns_image_entrypoint(void)89 uintptr_t plat_get_ns_image_entrypoint(void)
90 {
91 #ifdef PRELOADED_BL33_BASE
92 return PRELOADED_BL33_BASE;
93 #else
94 return PLAT_ARM_NS_IMAGE_OFFSET;
95 #endif
96 }
97
98 /*******************************************************************************
99 * Gets SPSR for BL32 entry
100 ******************************************************************************/
arm_get_spsr_for_bl32_entry(void)101 uint32_t arm_get_spsr_for_bl32_entry(void)
102 {
103 /*
104 * The Secure Payload Dispatcher service is responsible for
105 * setting the SPSR prior to entry into the BL32 image.
106 */
107 return 0;
108 }
109
110 /*******************************************************************************
111 * Gets SPSR for BL33 entry
112 ******************************************************************************/
113 #ifndef AARCH32
arm_get_spsr_for_bl33_entry(void)114 uint32_t arm_get_spsr_for_bl33_entry(void)
115 {
116 unsigned int mode;
117 uint32_t spsr;
118
119 /* Figure out what mode we enter the non-secure world in */
120 mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
121
122 /*
123 * TODO: Consider the possibility of specifying the SPSR in
124 * the FIP ToC and allowing the platform to have a say as
125 * well.
126 */
127 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
128 return spsr;
129 }
130 #else
131 /*******************************************************************************
132 * Gets SPSR for BL33 entry
133 ******************************************************************************/
arm_get_spsr_for_bl33_entry(void)134 uint32_t arm_get_spsr_for_bl33_entry(void)
135 {
136 unsigned int hyp_status, mode, spsr;
137
138 hyp_status = GET_VIRT_EXT(read_id_pfr1());
139
140 mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
141
142 /*
143 * TODO: Consider the possibility of specifying the SPSR in
144 * the FIP ToC and allowing the platform to have a say as
145 * well.
146 */
147 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
148 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
149 return spsr;
150 }
151 #endif /* AARCH32 */
152
153 /*******************************************************************************
154 * Configures access to the system counter timer module.
155 ******************************************************************************/
156 #ifdef ARM_SYS_TIMCTL_BASE
arm_configure_sys_timer(void)157 void arm_configure_sys_timer(void)
158 {
159 unsigned int reg_val;
160
161 #if ARM_CONFIG_CNTACR
162 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
163 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
164 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
165 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val);
166 #endif /* ARM_CONFIG_CNTACR */
167
168 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID));
169 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
170 }
171 #endif /* ARM_SYS_TIMCTL_BASE */
172
173 /*******************************************************************************
174 * Returns ARM platform specific memory map regions.
175 ******************************************************************************/
plat_arm_get_mmap(void)176 const mmap_region_t *plat_arm_get_mmap(void)
177 {
178 return plat_arm_mmap;
179 }
180
181 #ifdef ARM_SYS_CNTCTL_BASE
182
plat_get_syscnt_freq2(void)183 unsigned int plat_get_syscnt_freq2(void)
184 {
185 unsigned int counter_base_frequency;
186
187 /* Read the frequency from Frequency modes table */
188 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
189
190 /* The first entry of the frequency modes table must not be 0 */
191 if (counter_base_frequency == 0)
192 panic();
193
194 return counter_base_frequency;
195 }
196
197 #endif /* ARM_SYS_CNTCTL_BASE */
198